US3798609A

US3798609A - Dynamic shift register for staggered printing head

Info

Publication number: US3798609A
Application number: US00311490A
Authority: US
Inventors: H Frohbach
Original assignee: RAPIFAX CO
Current assignee: RAPIFAX CO
Priority date: 1972-12-04
Filing date: 1972-12-04
Publication date: 1974-03-19
Anticipated expiration: 1991-03-19
Also published as: GB1455690A; FR2209168A1; JPS5237939B2; DE2359395A1; DE2359395B2; DE2359395C3; CA983861A; NL7316507A; FR2209168B1; JPS4989445A

Abstract

A system for applying groups of data bits to an electrostatic writing head having two staggered lines of electrodes in which odd bits of a group are serially fed directly to the electrodes of one line and in which even bits of a group are fed to the electrodes of the other line through a dynamic shift register having a number of places equal to n where n is the number of bits in a group and in which means is provided for recirculating the bits through the shift register in response to a wait signal.

Description

United States Patent Frohbach [45] Mar. 19, 1974 DYNAMIC SHIFT REGISTER FOR 3.023.731 3/l962 Schwertz 1. 34617-8 ES STAGGERED PRINTING HEAD 3.071046 l/l963 Shull I 3,503 O63 3/1970 Starr 340/324 AD lnvenwri Hugh Frohbflsh, Sunnyvale. lif. 3.624.661 11/1971 Shebanon et al 346/74 ES {73} Assignee: The Rapifax Company, New York. P E P H H rrmary xammerau enon I Assistant ExaminerPaul R. Woods [22] Flled? 1972 Attorney. Agent, or Firm-Shenier & O'Connor [21] Appl. No.: 311,490

[57] ABSTRACT [52] us CL I I I I I I 340/1715 346/74 ES A system for applying groups of data bits to an elec- [51] Int Cl b 15/00 trostatic writing head having two staggered lines of 8 5 324 electrodes in which odd bits of a group are serially fed DIG directly to the electrodes of one line and in which even bits of a group are fed to the electrodes of the [56] References Cited other line through a dynamic shift register having a number of places equal to n where n is the number of UNITED STATES PATENTS bits in a group and in which means is provided for re- 2-95m2l 8/l960 Conrad 346/74 55 circulating the bits through the shift register in re 2,898 468 8/1959 McNaney 1 1 .1 346/74 ES sponge to a wait signal 2.930.847 3/1960 Metzger 1 4 4 .1 346/74 ES I 2.955.894 10/1960 Epstein 346/74 ES 12 Claims, 1 Drawing Figure EVGN Pm SELECTOR ODD PIN SELEC TOR IO IIT DYNA MIC SHIFT RGGISTER DYNAMIC SHIFT REGISTER FOR STAGGERED PRINTING HEAD BACKGROUND OF THE INVENTION There are known in the prior art electrostatic printing systems in which bits of information are fed to electrodes on a printing head. In response to the bits the printing head produces lines or rows of dots on the record medium. In order to achieve good reproduction, it is important that the dots be relatively dense. For example, good reproduction results when two hundred dots per inch are produced on a given line. However, the density of electrodes which can be provided on the recording head is limited by electrical breakdown between adjacent electrodes of styli. As a practical matter, if the electrodes have a diameter of five mils, only about one hundred electrodes per inch can be provided on the recording head if electrical breakdown is to be avoided.

In order to solve the problem outlined above, it has been suggested in the prior art that a recording head be provided with two staggered rows of styli or electrodes. To obtain the equivalent of two hundred dots per inch on the recording medium two rows of one hundred styli per inch each are employed. The rows are staggered five mils with respect to each other so that the styli of each row traverse different areas of the paper. Moreover, the rows are spaced ten mils apart.

It will readily be appreciated that in use of the head described above to produce a record having the equivalent of two hundred dots per inch some information must be stored. Where the data source puts out information sequentially in the order of P1, P2, P3, P4 Pn, Pl, PZ, P'3, P'4 Pn, P"l, P"2, P"3, P"4 P"n and a pair of "/2 step commutators exist for applying bits to the electrodes of the groups, respectively, it is apparent than an n bit delay is necessary for every other bit of a group such, for example, as the even bits since the odd bits may be printed at once. Stated otherwise, two lines of even bits must be stored if the system is to operate to produce the equivalent of 200 dots per inch on a given line.

In addition to the problem outlined above of storage of at least two lines of even bits, the source of information may stop putting out data at any element and wait. That is, it may put out a series of zeros which are not to be printed. This occurs for precisely mn element periods where m is an integer. It is indicated by the data source on a different channel from the channel which carries the output data.

From the foregoing it is clear that in use of a staggered printing head some form of storage device must be provided and that device must be capable of retaining the information for a relatively indefinite period of time. While a static shift register which has the capability of storing information for an indefinite period of time is capable of achieving the desired result, it is a relatively expensive piece of equipment.

I have invented a system incorporating a dynamic shift register which solves the problems outlined above. My system provides a relatively inexpensive arrangement utilizing a staggered printing head. My system is capable of retaining information during a wait" period without the use of a static shift register. My arrangement produces the equivalent of a two hundred dot per inch line in a relatively simple and expeditious manner.

SUMMARY OF THE INVENTION One object of my invention is to a provide a dynamic shift register for a staggered printing head.

Another object of my invention is to provide an electrostatic printing system employing a staggered printing head which system is relatively inexpensive.

A further object of my invention is to provide the equivalent of a two hundred dot per inch printed line in a simple and expeditious manner.

Other and further objects of my invention will appear from the following description.

In general, my invention contemplates the provision of a system for applying groups of data bits to an electrostatic writing head having two staggered lines of electrodes or styli in which the odd bits of a group from a data source are serially fed directly to the electrodes of one line and in which even bits of a group are fed to the electrodes or styli of the other line through a dynamic shift register having a number of places n equal to the number of bits in a group and in which means is provided for recirculating the stored bits through the shift register in response to a wait signal provided by the data source on a separate line.

BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawing to which reference is made in the instant specification, the FIGURE is a schematic view of my dynamic shift register for staggered printing head.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawing, a record medium 10 is adapted to be printed with lines of dots to make up the information coming from the input source to be described hereinbelow. The writing head includes two spaced lines or rows of styli or

electrodes

12 and 14 the electrodes 12 of which can be considered even electrodes and the electrodes 14 of which can be considered to be odd electrodes. In a specific embodiment the electrodes of a row may be spaced by a distance of about 10 mils and the distance between the two rows is about l0 mils. By way of illustration only, we have shown five electrodes in each of the two lines whereas in a practical embodiment there will be one hundred electrodes or styli in each line and each group of information bits contains 200 bits. In a manner to be described, the record medium 10 is adapted to be stepped relative to the

head having electrodes

12 and 14 through a distance corresponding to the distance between successive lines to be printed on the record medium in the direction of the arrow A in the drawing to bring lines of the record medium successively into registry with the row of electrodes 14 and the row of electrodes 12. In the particular example being considered each step is five mils.

An even pin selector 16 such as an n12 commutator is adapted to be indexed in response to a signal applied to an indexing section 18 successively to apply bits to the electrodes of the line of electrodes 12. Similarly, an odd pin selector 20 or commutator is adapted to be stepped in response to a signal at an indexing section 22 successively to apply bits to the electrodes of the row of electrodes 14.

The data source 24 of any suitable type known to the art is adapted to put out information bits on line 28 and synchronizing pulses on a line 26 at a rate of about 1,000 pulses per second. The data source also includes a section 42 which carries a normal" signal so long as the data source 24 is putting out information. When no information is being put out by the source 24 the signal from section 42 is not present.

A divide-by-two network 30 is adapted to receive the synchronizing pulses from line 26 and to put out a pulse every second synchronizing pulse. 1 apply the output of network 30 directly to the indexing section 22 of the selector 20 to step the selector 20 on every odd synchronizing pulse. A two-input AND circuit 32 receives the input data from line 28 and the output of circuit 30 to apply every odd bit of information from the data source to the selector 20. In this way, odd bits are directly sequentially applied to the electrodes or styli 14 by the odd pin selector or commutator 20.

I also apply the output of the circuit 30 to the inhibiting terminal 64 of an amplifier 62 to provide an input for the indexing section 18 of the even pin selector 16 on every even synchronizing pulse. 1 further apply the output of the circuit 30 to an inhibiting input terminal 38 of a two-input AND circuit 36 and the other input of which is supplied by line 28. Thus, every even bit of information is passed by the circuit 36 to one input terminal of a two-input AND circuit 44. 1 apply the output from the section 42 data source to the other input terminal of AND circuit 44. Thus, every even bit of information is passed to the input of a bit dynamic shift register 40, so long as the normal signal exists at the output of section 42.

Data source section 42 and network 30 provide the inputs for a two-input AND circuit 56 which provides a shifting signal to the shift section 58 of the register 40 so long as the normal signal exists. In this manner, the even bits of each group are applied to the register 40 and after 10 even bits have passed into the register 40, all of the places in the register are full. With the arrangement shown in which there are 10 styli or

electrodes

12 and 14, register 40 is full after two lines of bits have been produced by the source 24. On the occurrence of the next shift pulse, the first bit which moved into the register moves out of the register to one input terminal ofa two-input AND circuit 52, the other input of which is supplied by the data source section 42. From this point onward, the circuit 52 passes the even bits to a line 54 leading to the even pin selector 16.

While for the particular example we have illustrated there are only ten printing electrodes, in apractical embodiment of the system l'T00electrodes are used for pages of 8% inch width.

tion which must be retained if the system is to function properly.

I connect the output from section 42 to the inhibiting terminal 48 of a two-input AND circuit 46 the other input of which is provided by the output from the shift register 40. Similarly, I apply the output from source section 42 to an inhibiting input terminal of a two-input AND circuit 60 the other input of which is provided by the clock pulse line 26. Thus, when no signal exists on the output from data source section 42 AND circuit 46 couples the output from shift register 40 to the input thereto. At the same time, AND circuit 60 provides shift pulses for stepping the shift register 40 to preserve the data contained therein. Since the wait" signal or absence of a normal" from the section 42 exists for a period which is an integral multiple of the time occupied by a group of bits, when the wait period is over, the shift register 40 contains the same information in the same order when the wait period began. When the normal signal from network 42 resumes, the system continues to function as before.

The operation of my dynamic shift register for a staggered printing head can best be understood from the following table considering a plurality of groups of pulses P, P, P", P', of 10 pulses each from the beginning of the operation of the system. Considering the relative orientation of the record medium 10, and the

electrodes

12 and 14 being such that the row of styli 14 are aligned with line 1, odd pulses of the first group of pulses P, are passed directly by AND circuit 32 to the odd pin selector 20 and, in response to the indexing signal at input 22, they are applied sequentially to the electrodes 14. Even pulses of the group P are passed by AND

circuits

36 and 44 to the shift register 40 to fill up five places thereof.

At the end of the first group of pulses P, the head and record medium are stepped relative to each other through a distance equal to the distance between successive lines to be printed which is half the distance between the rows of

electrodes

12 and 14 so that the styli 14 are aligned with line 2. During the next group of pulses P, the odd pulses are again applied directly to the electrodes of the line 14 and the even pulses of the group are fed into shift register 40 to fill the register. The head and record medium are again stepped relative to each other so that the line of electrodes 14 is aligned with line 3. At the same time, the row of electrodes 12 is aligned with line 1. It will be remembered that this time the register 40 is full. Consequently, during the period occupied by this group of pulses P", the odd pulses are fed directly to the odd pins 14 as before. However, the even pulses of the first group which had been stored by the register 40 are now fed to the even electrodes of styli 12. That is to say, pulses P2, P4, P6, P8 and P 10 are fed to the respective styli 12 during this period of operation. it will readily be seen that the result is a complete line of information for line 1. In the course of the next group of pulses P', the odd pulses are fed directly to the styli 14 to print the odd information in the 4 while the pulses P'2, P'4, P'6, P8 and PM are fed to the even styli 12 to complete the line 2 of information.

The operation of my system for slightly more than the first three lines of information can best be seen from the following table:

74, the output of which is applied to the enabling input of AND circuit 60. During a "wait" period of 10 clock Shift register sync info Considering the operation described above, if a "wait" period occurs, the output from section 42 disappears at the end of a group of pulses and does not reappear for an interval of time which is an integral multiple of the time occupied by a group of pulses. During this wait" period, both the AND

circuits

46 and 60 are enabled so that the information contained in register 40 is not lost but is recirculated. At the end of the period of time, the information in register 40 will be as it was at the beginning of the period. Thus, when operation continues the even information stored therein will be fed to the even styli to complete the lines of information which were left incomplete when the "wait" period started.

While the spacing between the two staggered rows of styli is at least two lines, it will be understood that the row spacing may be increased to three or more lines as desired. In such event, the capacity of the shift register should be correspondingly increased. For example, register 40 should have a bit capacity for a row spacing of three lines. Furthermore during any "wait" period, where ten clock pulses or an integral multiple thereof are provided on line 26, register 40 must be shifted fifteen times or some integral multiple thereof.

This is accomplished by actuating switch 70 to its alternate position where clock pulses on line 26 are applied to a frequency multiplier 72 tuned to the third harmonic of the lock pulse frequency. If desired the output of frequency tripler 72 may be directly connected to the enabling input of AND circuit 60. Thus during a wait" period of ten clock pulses, register 40 would be indexed thirty times; and its entire contents would be recirculated twice. Preferably, however, frequency tripler 72 is coupled to a divide-by-two flip-flop pulses, register 40 will be indexed 15 times; and its entire contents will be recirculated once.

it will be appreciated that a dynamic shift register is of simpler and less expensive construction than a static shift register. However, a dynamic shift register can not retain stored data indefinitely as can a static shift register. Yet, I may effectively achieve an indefinite storage period for a dynamic shift register by continually indexing the register at a minimum rate the period of which is somewhat less than the static storage period of the dynamic shift register. For example, if the clock rate on line 26 is 5,000 pulses per second and the information rate on line 28 is correspondingly 5,000 bits per sec ond, register 40 will be indexed at a minimum rate of 2,500 times per second by flip-flop 30 through AND circuit 56. Accordingly the static storage period of dynamic register 40 must be at least 0.4 millisecond and is preferably not less than 0.6 to 0.8 millisecond. During a wait period, register 40 will be indexed 5,000 times per second for a two-line row spacing with switch in the position shown and 7,500 times per second for a three'line row spacing with switch 70 in the alternate position.

It will be seen that l have accomplished the objects of my invention. 1 have provided a dynamic shift register for a staggered printing head. My system enables me to use a staggered electro printing head in a system which is relatively inexpensive. My arrangement enables me to store information during periods when no information is being supplied by the data source. It is simple and relatively inexpensive to construct for the result achieved thereby.

It will be understood that certain features and subcombinations are of utility and may be employed without reference to other features and subcombinations. This is contemplated by and is within the scope of my claims. It is further obvious that various changes may be made in details within the scope of my claims without departing from the spirit of my invention. It is, therefore, to be understood that my invention is not to be limited to the specific details shown and described.

Having thus described my invention, what I claim is:

1. Printing apparatus including in combination a data source providing information in the form of data bit groups each representing a portion of a line to be printed, a printing head having two staggered rows of electrodes, means for applying alternate bits of each group to the electrodes of one row, and means including a dynamic shift register for applying the other bits of each group to the electrodes of the other row.

2. Apparatus as in claim 1 in which said register has a capacity equal to K times half the number of bits in a group, where K is an integer not less than two.

3. Apparatus as in claim 1 further including means for selectively recirculating the contents of said register.

4. Apparatus as in claim 1 further including means for selectively recirculating the entire contents of the register an integral number of times.

5. Apparatus as in claim 1 wherein the rows are spaced by two printing lines and wherein the register has a capacity equal to the number of bits in a group.

6. Apparatus as in claim 1 wherein the rows are spaced by three printing lines and wherein the register has a capacity equal to three-halves the number of bits in a group.

7. Apparatus as in claim 1 wherein the data source provides information at a certain bit rate, the apparatus further including means for indexing the shift register at half said rate.

8. Apparatus as in claim 1 further including means for normally indexing the shift register at a predetermined rate and means for selectively indexing the shift register at K times said rate, where K is an integer not less than two.

9. Apparatus as in claim 8 wherein the rows are spaced by two printing lines and wherein K equals two.

10. Apparatus as in claim 8 wherein the rows are spaced by three printing lines and wherein K equals three.

11. Printing apparatus including in combination a data source providing data bits representing a portion of a line to be printed, a printing head having a row of electrodes, a dynamic shift register having a certain static storage time, means selectively coupling the source to the register, means selectively coupling the register to the electrodes, means selectively recirculating the contents of the register, and means continually indexing the shift register at rates greater than the reciprocal of its static storage time.

12. Apparatus as in claim 11 wherein the data source includes means providing a signal of predetermined duration and wherein the recirculating means includes means responsive to said signal for recirculating the entire contents of the register an integral number of

Claims

12. Apparatus as in claim 11 wherein the data source includes means providing a signal of predetermined duration and wherein the recirculating means includes means responsive to said signal for recirculating the entire contents of the register an integral number of times.