US3764414A - Open tube diffusion in iii-v compunds - Google Patents

Open tube diffusion in iii-v compunds Download PDF

Info

Publication number
US3764414A
US3764414A US3764414DA US3764414A US 3764414 A US3764414 A US 3764414A US 3764414D A US3764414D A US 3764414DA US 3764414 A US3764414 A US 3764414A
Authority
US
United States
Prior art keywords
diffusion
open tube
iii
temperature
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
Inventor
J Blum
K Shih
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US24919772A priority Critical
Application granted granted Critical
Publication of US3764414A publication Critical patent/US3764414A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604Deposition from a gas or vapour
    • H01L21/31608Deposition of SiO2
    • H01L21/31612Deposition of SiO2 on a silicon body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase
    • H01L21/2233Diffusion into or out of AIIIBV compounds
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/065Gp III-V generic compounds-processing

Abstract

AN OPEN TUBE PROCESS IS USED OF ZN DIFFUSION IN III-V COMPOUNDS COATED WITH SIO2 FILMS TO FORM P-N JUNCTIONS. ELECTROLUMINESCENT DIODES MADE BY THIS METHOD HAVE HIGH BRIGHTNESS WITH NO ETCHING OF THE P-N JUNCTION SURFACE REQUIRED.

Description

OCL 9, 1973 J, M BLUM ljT AL OPEN TUHH DIFFUSION 1N lIlv'V COMPOUNDS B Sheets-Sheet Filed May l, 1972 :a ,i mi# @m35 mmm IH a Nw Oct. 9, 1973 J, M BLUM ET AL OPEN TUBE DIFFUSION IN III-v COMPOUNDS Filed May l, 1972 I I I I DEPTH, x3 (p) JUNCTION sio2=1oooII o CD JUNCTION DEPTH, Xj(;1)

SQUARE ROOT OF DIFFUSION TIME SQUARE ROOT OF DIFFUSION TIME B Sheets-Sheet 1*/2 (HoURsI/z) OC- 9, 1973 J. M. BLUM ETAL 3,764,414

OPEN TUBE DIFFUSION IN III-V COMPOUNDS Filed May l, 1972 B Sheets-Sheet l FIG. 5 f4 8 JUNCTION DEPTH,

6 TZn- TW-050 0 Sio2 THlCKNEss FIG. 6 8

JUNCT10N DEPTH, 4*

SOURCE TEMPERATURE, Tzn (C) Oct. 9, 1973 J. M BLUM ET AL 3,764,414

OPEN TUBE DIFFUSION 1N Il'L--V COMPOUNDS Filed May l, 1972 B Sheets-Sheet O m02: 2000K 00 A TZn=TW= 7000 v 7500 A O 000c "A El 05000 lm 70 D 7 O 1 00 O I 9 A u l O O 2 O f f 00- v Q E n: El

00 O LLI LLI I w n znAsZ 500005, 10 /mFFusED AT 0000 l l l l 0 2 4 6 0 10 12 JUNCTION DEPTH, Xj(p.)

Oct. 9, 1973 1 M, BLUM ET AL 3,764,414

OPEN TUBE DIFFUSION IN lll-V COMPOUNDS Filed May l, 1972 B Shees-Sheecv 5 lFIGB Jr: 1 HOUR SOURCE AND WAFER TE-MPERATURE Tzn=Tw OC. 9, 1973 Ml BLUM ET AL 3,764,414

OPEN TUBE DIFFUSION IN III-V COMPOUNDS Filed May l, 1972 B Sheets-Sheet 6 El I s402444) X405) P 0 500 5.4 A 5n 10 I .o C

J 42n- TW- 800 0 D LL 4:4 HOUR LLI LLI

LLl

10 llllllll IIIIIIIII Illllli CURRENT DENs4TY .14A/CM2) Oct. 9, 1973 Filed May 1, 1972 (FT. LAMBERTS) v Jul J. M. BLUM ET AL 3,764,414

OPEN TUBE DIFFUSION 1N LII-V COMPOUNDS a sheets-sheet v FIG. i0

sie, -zooo DIFFUSION TIME I (HOURS) OC. 9, 1973 1 M BLUM ETAL 3,764,414

OPEN TUBE DIFFUSION IN III-V COMPOUNDS Filed May 1, 1972 8 Sheets-Sheet I.

. A. TW 80000 I=I H000 BRIGHTNEss SI02= 2000A AT J= AoA/cIIII2 500 500 n l l l SOURCE TEMPERATURE TZn ICI FIG i2 DIFFUSION CONDITIONS 700- A A TZnIOcITWAcI Ahr sIozII O O 600 g A A00 000 A A 2000 Al A00 700 A 2000 0 000 000 A A000 s00 0' 000 000 0.5 2000 0 000 000 I 2000 BRIGHTNESS 400 0' 050 050 05 2000 AT J MCMZ 0 T50 T50 4 A000 *O E 050 050 2 A000 IFT. I AAABERTSI 000 200 E; g' g Al O A00- E O l l l I l 0 2 4 0 0 A0 A2 AA A0 JUNCTION DEPTH xi (IA) United States gPatent O 3,764,414 OPEN TUBE DIFFUSION IN lII-V COMPOUNDS Joseph M. Blum, Yorktown Heights, and Kwang K.

Shih, Ossining, N.Y., assignors to International Business Machines Corporation, Armonk, N.Y.

Filed May 1, 1972, Ser. No. 249,197 Int. Cl. H011 7/44 U.S. Cl. 148-189 8 Claims ABSTRACT OF THE DISCLOSURE An open tube process is used for Zn diffusion in III-V compounds coated with SiO-2 lms to form p-n junctions. Electroluminescent diodes made by this method have high brightness with no etching of the p-n junction surface required.

BACKGROUND OF THE INVENTION Zn diffusion into III-V compounds such as GaAs, GaAs1 xPx, GaP, etc. has commonly been carried out in sealed quartz ampoules or tubes. The vacuum and arsenic pressure in such a closed system are critical factors in the control of (a) junction depth and (b) surface concentration of the zinc dopant. Failure to control either vacuum or arsenic pressure within very close tolerances makes it difficult to attain reproducibility of uniformly diffused compounds. Additionally, zinc and arsenic vapors, when an oxide mask is used in conjunction with a Wafer undergoing diffusion, attack the window openings of such mask, further complicating the probability of achieving reproducibility in that subsequent processing of the wafer is made difficult by such attack.

Workers in the field of dealing with Zn diffused GaAs, as exemplified by an article by S. R. Shorts et al., appearing on pages 30G-|- in the 1964 issue of Transactions of the Metallurgical Society AIME 230 and an article by M. Beeke et al. which appeared on pages 307+ of the same publication, in order to reduce the surface Zn concentration for making transistors, employed a thin layer of SiO2 on the surface of their GaAs wafer. The thin layer of SiO2 also served as a film protecting GaAs from erosion due to the dissociation of GaAs. However, what was not appreciated by such prior workers in the field was that the use of a SiO2 erosion-preventing layer now removed the need for employing a closed tube diffusion process with its attendant ills, i.e., cumbersome, timeconsuming, expensive, etc. Besides, this process can be applied to other III-V compounds such as GaAs1 Px which yields high efficient, bright, light-emitting diodes with no surface etching required.

The process of fabricating planar monolithic II-V light emitting diodes and arrays is greatly simplified by sputtering an A1203 film as a mask against zinc on a III-V compound crystal wafer. Diffusion patterns are delineated in the A1203. Before diffusion of zinc is begun, a film of SiO2 is deposited over the wafer to prevent surface erosion during diffusion. The diffusions are done in an open tube furnace with forming gas, i.e., a gas mixture of 90% nitrogen and hydrogen, flowing in the furnace at a temperature of about 800 C. for a time varying from 30 minutes to an hour to give a diffusion depth of about 3-6,u..

Consequently, it is an object to diffuse dopants into III-V crystal wafers using open' tube apparatus.

It is yet another object that pure Zn can be used as a source in an open tube at high temperature.

It is yet another object to achieve planar monolithic doped III-V compounds using an open tube apparatus.

It is yet another object to use an open tube apparatus for doping III-V compounds coated with SiO2 films Without eroding the surface of such compounds.

3,764,414 Patented Oct. 9, 1973 It is a further object to obtain high bright efficient GaAs1 Px light emitting diodes with no surface etching required.

The foregoing and other objects, features, and advantages of the invention will be apparent from the following more particular description of the preferred embodiments of the invention as illustrated in the accompanying drawings.

DESCRIPTION OF THE DRAWINGS FIG. 1 is an open tube furnace employed in the diffusing of a dopant into a III-V compound with an accompanying graph plotting temperature as a function of distance into the furnace.

FIG. 2 is a showing of an A1203 mask, having an SiO2 layer in the windows of the mask, employed with a wafer of a III-V compound in an open tube diffusion apparatus.

FIGS. 3-12 are graphs depicting various characteristics of a Zn diffused GaAs1 X X by an open tube method as functions of SiO2 thickness, temperature of the furnace, time of diffusion, etc.

DESCRIPTION OF THE INVENTION The open tube diffusion system is applicable to many III-V materials, such as, but not limited to GaAs1 x `x, AlxGa1 xAs, GaAs or Gal?. For purposes of demonstrating the invention, extensive tests were made only on the compound GaAs 1 XPX, where x varied between 0.38-0.4. The latter choice of x was made so that the doped GaAs1 X x would, when made into a diode, emit in the visible region of the electromagnetic spectrum. The carrier concentration n was between `1 to 3 |101'7 cm.3. Additionally, the GaAsP wafer had a total thickness of vapor grown epitaxial layer of 76.9@ with -35.9`,u of it graded in composition and the remaining layer having constant composition.

The diusion apparatus shown in FIG. 1 consists of a two-zone furnace, zone 1 housing a souce `2 of dopant, which was chosen to be zinc, and a second zone, zone 2, that houses the wafers 4 of GaAsP.. A constant flow of N2 is maintained throughout the diffusion process, entering the furnace through inlet 6 and leaving through exit port 8. Zn pellets 2 of high purity are loaded in a boat 10 and the wafers 4 of GaAsP are loaded on a flat plate 12 in zone 2 of the furnace. N2 gas is turned off and forming gas is then turned on to fiow at a rate of about 400 cc./ min. for a half-hour to fiush the furnace. After fiushing, the Zn-containing boat 10 is pushed into zone 1 and, after ten minutes, the wafers 4 are pushed into zone v2, rods 14 and 16 being relied upon for locating Zn and wafers, respectively, in the furnace.

Prior to inserting a GaAsP wafer 4 into the furnace, a mask 18 (see FIG. 2) of A1203 is deposited over the Wafer 4 and the windows 20 of the mask, as well as the mask, are covered with a thin layer 22, of the order of 1000 A.2000 A. thick, of SiO2. The SiO2 layers are deposited by a pyrolytic decomposition process wherein SiO2 is deposited as a result of the decomposition of tetraethylorthosilicate (T EOS) in an oxygen atmosphere. SiO2 thicknesses of 500 A. to 4000 A. have been grown with a deposition rate of 60 A./min., with a thickness of 1000 A.2000 A. being preferred.

Diffusions of Zn, in the open tube furnace of FIG. l, have taken place where the temperature of the Wafer 4 was the same as that of the source 2 and the temperatures were chosen to be 700 C., 750 C., 800 C. and 850 C. and the times of diffusion varied from one half-hour to 4 hours in intervals of a half-hour. Results were obtained, and will be discussed hereinafter, using a fixed wafer 4 temperature of 800 C., but different Zn temperature of 700 C., 750 C. and 800 C., and a diffusion time of one hour.

After diffusion, the forming gas is turned of'and N2 is turned on prior to removal of the wafers 4 from the furnace. SiOz films 22 are removed by etching from the wafers 4 and the junction depth of a GaAsP wafer can be measured by developing a junction interface with a etch in a cleavage plane normal to the junction. Diodes are made by electroplating Au-Sn films or spots onto the substrate side of a wafer 4 after that substrate has been thinned to reduce series resistance. Small cleaved sections, having an area of about 10-3 cm?, are mounted on a header and aluminum wire is ultrasonically bonded to the p-surface of the cut wafer. Plots shown in FIGS. 3-12 are measurements of wavelength, A, external quantum efficiency, n, and brightness of such diodes that were manufactured from a doped GaAsP Wafer that was treated with SiO2 prior to being placed in a diffusion furnace.

Films of SiO2 with thicknesses of 500 A., 1000 A., 2000 A. and 4000 A. were deposited on the surfaces of the wafers to study the effect of Si02 thickness on other parameters. However, for SiO2 films around 4000 A. thick, the oxide sometimes cracked to give an erratic junction depth. On the other hand, if the oxide thickness was less than 500 A., a non-uniform junction depth often occurred. Hence, most of the data are from wafers deposited with 1000 A. and 2000 A. thick SiOz films.

The junction depth XJ for various Zn diffusions with the same source and wafer temperatures between 700 C. and 850 C. Iverus the square root of time are plotted inn FIGS. 3 and 4 for 1000 A. and 2000 A. thick SiOz films, respectively. An approximately linear relationship is observed which means that Ficks law is obeyed. This information is helpful for predicting the junction depths at other diffusion temperatures and times. Results of diffused junction depth Xj versus the SiO2 thickness when Zn temperature (Tzu) equals wafer temperature (TW) for a one hour of Zn diffusion are shown in FIG. 5. This figure indicates that at the lowest temperature (700 C.) the junction depth is almost independent of oxide thickness; While at higher temperatures (850 C.), the junction depth decreases drastically with increasing oxide thickness.

FIG. 6 shows the diffused junction depth as a function of source temperature for a one hour diffusion while the wafer temperature is kept constant at 800 C. The junction depth decreases when the source temperature decreases which implies that different junction depths can be also obtained by varying the source temperature.

The sheet resistance ps of the diffused layers of some of the wafers have been measured by the four point probe method. In FIG. 7, the sheet resistance versus junction depth for zinc diffused layers formed at different temperatures are plotted. The sheet resistance of the Zn diffused layers in GaAs1 XPX using ZnAs2 as a source diffused at 800 C. in a closed tube has been measured as denoted by a star in FIG. 7. One significant result is that at a given junction depth, the sheet resistance of the layers diffused in the open tube system is much higher than that using ZnAs2 source in a closed tube system. Hence the Zn concentration in the oxide coated GaAs1 xPX layers diffused by the open tube method must be lower than that in layers diffused by conventional ZnAs2 source closed tube method. The surface concentration C of some wafers were measured using plasma resonance method. For the wafers diffused at TZn=TW=800 C. with a 2000 A. thick SO2 film on the surface, C0 is approximately equal to 3.5 1019 cmfa. The lowest C0 measured is about 1.4 1019 cm.-3 when TZ\=TW=700 C. with a 1000 A. thick SiO2 film on the surface during diffusion. C0 is approximately equal to 1.1 102D cm.-3 if .4 j ZnAs2 source is used in a'closed ampoule diffused at 800 C. This result is consistent with the sheet resistance measurement.

The external quantum efficiency and wavelength of the diffused GaAs1 XPx diodes have been measured. It was found that the efficiency did not vary very much in our diffusion studies even though the temperatures of the source and wafers was changed between 700 C. to 850 C. The average efficiency was about l0-3 at 6600 A. for uncoated diodes. The highest value obtained was about 2.4 10*3 at 6650 A. for uncoated diodes. Values of the external quantum efficiencies of diodes made from wafers diffused for one hour at various temperatures and with TZ\=Tw are shown in FIG. 8. The results show that the efficiencies of diodes made with an SiOz thickness of 2000 A. are better than those with a thickness of 1000 A.

The brightness was measured with a Spectra Brightness Spot Meter Model UB viewing an 8 mil diameter area. The area of most of the diodes varied between .8X10-3 cm.2 and 1.2 10*3 cm. 2. So far, the highest brightness we have measured was about 1000 ft. Lamberts at a current density of 10 a./cm.2 and at 6650 A., without etching the surface of the diodes.

Typical curves of brightness versus current density of diodes made from wafers diffused at TZn=TW=8O0 C. for one hour with different oxide thicknesses are shown in FIG. 9. These results are to be expected. When the oxide thickness increases, the junction depth decreases and the brightness increases. FIG. 10 demonstrates the effects of diffusion time on brightness when the wafer 4 temperature and source temperature of Zn source 2 are equal. The brightness at current density 10 a./cm.2 is plotted for comparison. When the temperature increases from 700 C. to 800 C., the brightness also increases. A maximum value is obtained at 800 C. for a one hour diffusion. When the temperature increases further to 850 C., an adverse result is obtained which may either be caused by high free carrier absorption due to higher zinc solubility at that temperature or a detrimental heat treatment effect above 800 C. such as an increase of dislocations. In FIG. 11, the luminance is plotted versus source temperature (Tzn) for two different oxide thicknessess while the wafers were diffused for one hour at 800 C. It is apparent that some improvement in brightness can be obtained at a lower source temperature because the junction depth decreases with decreasing source temperature and results in less light absorption at the surface.

FIG. 12 demonstrates the effect of junction depth on the brightness of the diodes. At about the same shallow junction depth of about l to 2 am. deep (points A, A and B, B in FIG. 12), the brightness of the diodes can differ by a factor of 3 to 4 depending on the diffusion conditions. When the junction depth is about 4 to 5 am. deep, the difference in brightness can still be great depending on diffusion conditions. By comparing these diffusion conditions, it seems that some kind of heat treatment effect is involved so that a different wafer temperature and diffusion time could give a different result in brightness at the same junction depth. From FIG. 7 it was found that the sheet resistance of the wafers diffused in the open tube process with SiO-2 film on the surface is higher than that using the ZnAsz source Higher sheet resistance implies lower Zn concentration or lower p-type free carrier concentration in the diffused layer. Hence, the free carrier absorption in the layer is also reduced. When the junction depth is greater than 7 ,um. as shown by points D and E in FIG. 12, the brightness dropped very fast.

Point B in FIG. 12 corresponds to one hour diffusion at TZn=T :800 C. with a 4000 A. Si02 deposited on the surface, and point A in FIG. 12 corresponds to a one hour diffusion at Tzn=700 C. and Tw=800 C. with a 2000 A. SiO, deposited on the surface. Both diffusions give the same brightness with a shallow junction depth of about 2pm. Since a 4000 A. SiO2 film usually cracks during the diffusion process, the diffusion condition corresponding to point A is preferred. The shallow junction may cause high contact resistance which is not desirable for some applications. In case lower contact resistance is required, diffusion condition corresponding to point C in FIG. 12 which has a deeper junction depth (-4.8 am.) and higher surface Zn concentration can be used. The diffusion conditions for both points A and C are the same except the source temperature.

In conclusion, it has been shown that SiO2 films on the surface during diffusion offers surface protection allowing the retention of smooth surfaces. With this protection, open tube diffusions can be used. The surface zinc concentration is lowered by the SiOZ film so that the free carrier absorption is reduced. Therefore, high brightness results are achieved in these diodes with no etching of the surface required. This in fact is thus a truly planar process. In addition, the open tube approach enables many diffusions to be carried out in quick succession, avoiding the complications associated with encapsulation under vacuum which is necessary in the closed tube system. While only data on GaAs1 x x has been given herein, the process has been successfully applied to other III-V semiconductor materials such as: AlxGa1 xAs, GaP, and GaAs.

What is claimed is:

1. In a method for forming a p-njunction in an n-type Group III-V compound comprising the steps of:

(a) placing a zinc diffusant in one zone of a two zone open tube furnace and a Group III-V compound in the other zone of said furnace, said Group III-V compound having a zinc diffusion mask on its surface to be exposed to the diffusant,

(b) depositing a layer of pyrolytic SiOz on said mask, said layer being of the range between 500-4000 A. thick,

(c) flushing said open tube contents with forming gas at a rate of about 400 cc./ min. for about 1/2 hour, and

(d) maintaining said zinc zone at a temperature range of about 700 C. to 850 C. and the Group III-V compound at a temperature range equal to or greater than the zinc zone temperature whereby the eficiency of subsequent light emitting diodes made with such p-n junction is substantially increased.

2. The method of claim 1 wherein said zinc diffusant source is pure zinc.

6 3. The method of claim 1 wherein the Group III-V compound is GaAs1 X x.

4. The method of claim 3 wherein x varies from 0.38 to 0.4.

5. The method of claim 1 wherein the Group III-V compound is AlxGa1 xAs.

6. The method of claim 1 wherein the Group III-V compound is GaAs.

7. The method of claim 1 wherein the Group II-I-V compound is GaP.

8. In a method for forming a p-n junction in an n-type Group III-V compound comprising the steps of:

(a) placing a zinc diffusant in one zone of a two zone open tube furnace and a Group III-V compound in the other zone of said furnace,

(b) depositing a layer of pyrolytic SiO2 on said Group III-V compound, said layer being of the range between 500-4000 A. thick,

(c) flushing said open tube tube contents with forming gas at a rate of about 400 cc./min. for about l/2 hour, and

(d) maintaining said zinc zone at a temperature range of about 700 C. to 850 C. and the Group III-V compound at a temperature range equal to or greater than the zinc zone temperature whereby the efficiency of subsequent light emitting diodes made with such p-n junction is substantially increased.

References Cited UNITED STATES PATENTS 3,617,929 11/1971 Strack et al. 317--235 N 3,660,178 5/1972 Takahashi et al 148-189 3,298,879 1/1967 Scott et al. 14S-187 3,139,362 6/ 1964 DAsaro et al. 148-187 3,313,663 4/1967 Yeh et al. 148-189 X 3,158,512 11/1964 Nelson et al. 148-172 X 3,498,853 3/ 1970 Dathe et al. 148-187 GEORGE T. OZAKI, Primary Examiner U.S. Cl. X.R.

US3764414D 1972-05-01 1972-05-01 Open tube diffusion in iii-v compunds Expired - Lifetime US3764414A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US24919772A true 1972-05-01 1972-05-01

Publications (1)

Publication Number Publication Date
US3764414A true US3764414A (en) 1973-10-09

Family

ID=22942440

Family Applications (1)

Application Number Title Priority Date Filing Date
US3764414D Expired - Lifetime US3764414A (en) 1972-05-01 1972-05-01 Open tube diffusion in iii-v compunds

Country Status (1)

Country Link
US (1) US3764414A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3865655A (en) * 1973-09-24 1975-02-11 Rca Corp Method for diffusing impurities into nitride semiconductor crystals
JPS5081775A (en) * 1973-11-22 1975-07-02
US3979235A (en) * 1974-01-10 1976-09-07 U.S. Philips Corporation Depositing doped material on a substrate
JPS5227354A (en) * 1975-08-27 1977-03-01 Hitachi Ltd Impurity diffusion method for iii-v group compound semiconductor region
US4124417A (en) * 1974-09-16 1978-11-07 U.S. Philips Corporation Method of diffusing impurities in semiconductor bodies
US4129090A (en) * 1973-02-28 1978-12-12 Hitachi, Ltd. Apparatus for diffusion into semiconductor wafers
US4939103A (en) * 1984-05-18 1990-07-03 Mitel Corporation Method of diffusing plurality of dopants simultaneously from vapor phase into semiconductor substrate

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4129090A (en) * 1973-02-28 1978-12-12 Hitachi, Ltd. Apparatus for diffusion into semiconductor wafers
US3865655A (en) * 1973-09-24 1975-02-11 Rca Corp Method for diffusing impurities into nitride semiconductor crystals
JPS5081775A (en) * 1973-11-22 1975-07-02
US3979235A (en) * 1974-01-10 1976-09-07 U.S. Philips Corporation Depositing doped material on a substrate
US4124417A (en) * 1974-09-16 1978-11-07 U.S. Philips Corporation Method of diffusing impurities in semiconductor bodies
JPS5227354A (en) * 1975-08-27 1977-03-01 Hitachi Ltd Impurity diffusion method for iii-v group compound semiconductor region
US4939103A (en) * 1984-05-18 1990-07-03 Mitel Corporation Method of diffusing plurality of dopants simultaneously from vapor phase into semiconductor substrate

Similar Documents

Publication Publication Date Title
Williams et al. Luminescence and the light emitting diode: the basics and technology of LEDS and the luminescence properties of the materials
Lee et al. Effects of column III alkyl sources on deep levels in GaN grown by organometallic vapor phase epitaxy
US6342313B1 (en) Oxide films and process for preparing same
TW393785B (en) Method to produce many semiconductor-bodies
US6255669B1 (en) Visible light emitting device formed from wide band gap semiconductor doped with a rare earth element
US3089793A (en) Semiconductor devices and methods of making them
Logan et al. Efficient green electroluminescent junctions in GaP
CA1292550C (en) Epitaxial gallium arsenide semiconductor wafer and method of producing the same
TW577178B (en) High efficient reflective metal layer of light emitting diode
CA2136580C (en) Gallium oxide coatings for optoelectronic devices
US6518077B2 (en) Method for making optoelectronic and microelectronic devices including cubic ZnMgO and/or CdMgO alloys
Dupuis Metalorganic chemical vapor deposition of III-V semiconductors
US3601668A (en) Surface depletion layer photodevice
JP3270476B2 (en) Ohmic contacts, II-VI compound semiconductor devices, and methods of manufacturing these devices
US6180270B1 (en) Low defect density gallium nitride epilayer and method of preparing the same
JP3157690B2 (en) Method for manufacturing pn junction element
Zavada et al. Hydrogenation of GaN, AlN, and InN
US5217539A (en) III-V solar cells and doping processes
JP3078611B2 (en) Light emitting semiconductor device including IIB-VIA group semiconductor layer
US3959045A (en) Process for making III-V devices
US3881113A (en) Integrated optically coupled light emitter and sensor
CA1114050A (en) Manufacture of solar cells
US6791257B1 (en) Photoelectric conversion functional element and production method thereof
USRE29845E (en) GaAs1-x Px electroluminescent device doped with isoelectronic impurities
US6972438B2 (en) Light emitting diode with porous SiC substrate and method for fabricating