US3740532A - Digital counter averaging system - Google Patents

Digital counter averaging system Download PDF

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US3740532A
US3740532A US00146712A US3740532DA US3740532A US 3740532 A US3740532 A US 3740532A US 00146712 A US00146712 A US 00146712A US 3740532D A US3740532D A US 3740532DA US 3740532 A US3740532 A US 3740532A
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count
counter
auxiliary
average
line
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R Esch
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Kureha Corp
Warner and Swasey Co
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Kureha Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0634—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale
    • H03M1/0656—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence by averaging out the errors, e.g. using sliding scale in the time domain, e.g. using intended jitter as a dither signal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/02—Input circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/22—Analogue/digital converters pattern-reading type
    • H03M1/24—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip
    • H03M1/28—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with non-weighted coding
    • H03M1/30—Analogue/digital converters pattern-reading type using relatively movable reader and disc or strip with non-weighted coding incremental

Definitions

  • ABSTRACT An arrangement for averaging the count received from a bidirectional pulse source such as a measuring machine position transducer is disclosed in which a relatively small capacity auxiliary counter is utilized in conjunction with a main counter, and includes means for causing the incoming pulses in either direction to bypass the auxiliary counter and pass to the main counter whenever the auxiliary counter is full in the direction of the incoming pulse.
  • the count in the auxiliary counter is periodically sampled with the samples taken [56] References Cited at regular intervals and an update signal reflecting the UNITED STATES PATENTS direction of the average count being added to the main 3,644,718 2/1972 Osborne et al. 235/92 EA counter and subtracted from the auxiliary counter at 3,57l,575 3/1971 Barr et al. 235/92 EV regular intervals 3,209,130 9/1965 Schmidt 235/92 PL 3,353,161 11/1967 Toscano 235 92 PL 7 Claims, 12 Drawing Flgul'es 3,500,023 3/1970 AI'IOWOOd et al.
  • DIGITAL COUNTER AVERAGING SYSTEM BACKGROUND OF THE INVENTION Measuring machines which utilize position transducers producing a visual decimal display of the coordinate position of a probe are often subject to vibrations and other disturbances which render accurate reading of the decimal display difficult if not impossible. Such machines are usually designed to be insulated from such vibrations which typically originate from the operation of other machinery in the area, but none attenuate these sufficiently to solve the problem, in many installations.
  • auxiliary counter connected ahead of the main counter and decimal display.
  • the auxiliary counter has a relatively small capacity relative to the main counter and pulses received from the pulse source are gated to the auxiliary counter until it is full in either direction, and thereafter pulses in that direction are gated directly to the main counter, as long as the auxiliary counter remains full in that direction.
  • the count contained in the auxiliary counter is sampled at regular intervals, these samples being periodically averaged and the average count then being subtracted from the auxiliary counter and added to the main counter.
  • FIG. 1 is a block diagram of the basic arrangement of the present invention.
  • FIG. 2 is a block diagram of a preferred embodiment of the present invention.
  • FIG. 3a is a graphical representation of the operation of the synchronizer shown in FIG. 3.
  • FIG. 4 is a schematic representation of a typical logic network depicted in block form in FIG. 2.
  • FIG. 5 is a schematic representation of the auxiliary counter depicted in block form in FIG. 2.
  • FIG. 6 is a schematic representation of the overflow detector depicted in block form in FIG. 2.
  • FIG. 7 is a schematic representation of the sampleraverager circuit shown in FIG. 2 in block form.
  • FIG. 8 is a schematic representation of the averager counter shown in block form in FIG. 2.
  • FIG. 9 is a schematic representation of the clock and sequencing circuitry shown in block form in FIG. 2.
  • FIGS. 10 and 11 are graphical representations of the sequencing of the various operations controlled by the clock and sequence circuitry.
  • Pulses over lines 12 and 14 are connected to a gating network 16 which causes the pulses to proceed either directly to the main counter and display 18 via lines 20 and 22 or to the auxiliary counter 24 via lines 26, 28, depending on the state of the auxiliary counter 24.
  • Auxiliary counter 24 is an up-down relatively small capacity counter (i.e., four bit for example) with count up occurring with pulses on line 28 and count down occurring with pulses on line 26.
  • a sign flip-flop may be utilized in order to distinguish the count in the auxiliary counter as that corresponding to the forward or reverse direction.
  • an overflow signal sent via line 30 controls the gating network I6, so that if a pulse in addition to the limited number able to be counted in the auxiliary counter 24 is received over lines 12 or 14 and, which pulse would add to the count of the full capacity counter 24, the pulse is then directed via line 20 or 22 directly to the main counter and display 18.
  • the pulse is then routed by the gating network 16 thereto, and not to the main counter and display 18 so that only the auxiliary counter receives pulses from the bidirectional signal source.
  • the count contained in the auxiliary counter 24 is periodieally sampled by the sampler-averager 32, and the average of the samples taken is computed at regular intervals.
  • Many wellknown methods exist for performing this function and a particular system utilizing a sampling register, accumulator, adder, and divider is disclosed in some detail infra.
  • the sample average is then transmitted to a pulse generator 34 which outputs a pulse count of the correct sign such that the sample average will be closer to zero after the next averaging cycle via lines 36, 38 so as to be added to that contained in the main counter and display 18, and at the same time subtracts this count from the auxiliary via lines 40, 42.
  • This pulse count may be either a single pulse, or the integer value of the sample average.
  • the circuitry required is much simplified, but a relatively large number of averaging cycles may be required to reduce the auxiliary counter to zero. In the latter case, the system will settle in at most two averaging cycles, but the required circuitry would be more complex.
  • sampleraverager determines the average count by taking samples over an averaging interval, the true arithmetic average of flutter patterns which are asymmetric are correctly obtained.
  • the main counter In the typical system, the main counter must often be reset to zero or some offsetting value in order to begin measurements. If the resetting signal is applied at the time the system is subject to a vibration and if the signal arrives at the counter when the count is other than the average count corresponding to the vibration, the subsequent readings will be in error to the extent of the deviation from average. In the present system, if the reset signal from a signal source 40 sends a reset signal over line 42 to the main counter 18, and the system is vibrating, the main counter 18 will be unaffected by the phase of the reset signal and the vibrations.
  • the incoming forward and reverse pulses on lines 12 and 14 are converted into logic levels by the synchronizer S4, with these logic levels being set in synchronism with the rest of the system operations by means of clock pulses received over line 56 from the clock and control circuitry 48 as will be discussed in more detail infra.
  • the logic levels set by the synchronizer 54 controls, together with logic levels of the other components, the logic levels in a count directing logic network 58 which in turn controls the transmission of clock pulses received over lines 56, 60 from clock and sequencing circuitry 48 to the main counter and display 18, the auxiliary counter 24, and the average counter 64, to be described infra.
  • the auxiliary counter 24 which consists of a four bit bidirectional up-down counter together with an associ ated Sign flip-flop 64 is adapted to receive a limited number of pulses gated thereto by gating network 58 over lines 66 and 68 corresponding to forward and reverse pulses received on lines 12 and 14, until the auxiliary counter 24 reaches its full capacity in either the forward or reverse directions.
  • an overflow detector 72 transmits a logic level signal to the gating network 58 via line A or 708 indicating full capacity in either the forward or reverse direction.
  • the count and its sign contained in the auxiliary counter 24 is periodically sampled by the sampleraverager circuit 32 via lines 74 and 76 added into an accumulator and averaged at regular intervals, with the average and its sign being transferred into the average counter 62 and associated sign flip-flop 78 via lines 80, 82 after each averaging interval.
  • the average counter 61 includes an associated four input NOR gate (described infra) so that whenever the average is not zero a logic level input indicating such condition is transmitted to the gating network 58 via line 90, while the logic level of flip-flop 78 indicating the sign or direction of the average is transmitted thereto via line 92.
  • the synchronizer 100 is depicted in detail in schematic form in FIG. 3.
  • the forward and reverse pulses carried over lines 12 and 14 are fed into the T input of a pair of flip-flops A, and A respectively, so that the trailing edge of the pulse received over line 12 or 14 sets Q high and 6 low of its respective A flip-flop.
  • the next clock pulse received over line 56 and fed into the T input of the respective B flip-flop B or B causes the high state of Q and the low state ofOof the A flip-flop to read over lines 94, 96, 98, and 100 into the J and K inputs of its associated B flip-flops, to set the respective B flip-flop Q high and 6 low, so that a high state is read over either line 52 or 54 and a low state over either 52 or 54.
  • the absence of a clock pulse (a clock pulse inverted at 102) is used to reset the A flip-flops if either of the B flip-flops are set by the l ogic combination of reading the level state of 52 and 54 into OR gate 104 via lines I06, 108 and feeding the output of the OR gate to AND gate 110 with the inverted absence of the clock pulse over line 112. This insures that the A flip-flops are read into the B flip-flops before they are reset.
  • a pulse input on either line 12 or 14 results in a stateghange on either line 52 (and 33) or on line 54 (and 54) in synchronism with the clock pulses and of a duration of one clock cycle to provide proper functioning of the logic gating network.
  • FIG. 3a depicts this in graphical form.
  • FIG. 4 a schematic diagram of the logic network 58 is shown.
  • the gating network 58 controls the transmission of clock pulses received over line 56 to the main counter 18 via lines 20, 22 to the auxiliary counter 24 via lines 66 and 68, and to the average counter 62 via lines 94, 96.
  • this is accomplished by inputing the clock pulses to one input of a series of AND gates 114, 116, 118, 120, 122, and 124 with the other input reading logic levels read on lines 126, 128, 130, 132, 134, and 136 respectively.
  • the AND gates cause a pulse to be transmitted therethrough to its respective line. Since some of the devices utilized require low going pulses as shown on lines 66, 68, and 94, 96, the pulses are inverted for this purpose.
  • Line 94 (Average Counter 62 Forward): A pulse is produced if the average counter 62 indicates a reverse average AND a reverse count is indicated on 54 OR no forward count in 52 AND no forward overflow indicated by the overflow detector 72 and line 52.
  • Line 96 (Average Counter Reverse): A pulse is produced if a forward average is indicated AND a forward count is on 52 OR no reverse count on 54 AND no reverse overflow is indicated by the overflow detector 72 and line 5 4.
  • Line 20 (Main Counter Forward): A pulse is produced if the line 96 is to receive a pulse, OR a forward count is indicated on line 52 AND a forward overflow condition is indicated by the overflow detector 72 and flip-flop 64.
  • Line 22 (Main Counter Reverse): A pulse is produced if line 94 is to receive a pulse, OR a reverse count is indicated on line 54 AND a reverse overflow is indicated by the overflow detector 72 and flip-flop 103.
  • Line 66 (Auxiliary Counter Forward): A pulse is produced if a forward count is indicated on line 52 AND line 20 is notla receive a pulse, OR no reverse count indicated on 54 AND line 94 is to receive a pulse.
  • Line 68 (Auxiliary Counter Reverse): A pulse is produced if a reverse count is indicated on line 54 AND line 22 is not to receive a pulse OR no forward count is indicated on line 5 AND line 96 is to receive a pulse.
  • the logic network shown is a NAND-NOR type of logic in order to conveniently provide the low going pulses required of the auxiliary and average counters 24 and 62.
  • FIG. depicts the auxiliary counter 24 which is com prised of a four bit binary up-down counter 138 which receives count up pulses over the forward line 66 and count down pulses over the reverse line 68. Count up is done in a binary count while count down is done in a twos complement binary.
  • the counter 138 When the counter 138 is in the 0000 state and a pulse appears on line 68, the counter 138 generates a borrow pulse on line 140 while if it is in state 1111 and a pulse enters line 55 a carry pulse on line 19 is generated, both in the manner well known in the art.
  • the carry and borrow pulses are applied to the flipflop 64 so that line 152 is set to the high state whenever a pulse enters line 14 and set to the low state whenever a pulse enters line 140, so that a high state of line 152 (or low state of 1 5 2) indicates a positive or zero count in the counter 138 w hile a low state on line 152 (or a high state on line 152) indicates a negative count.
  • This logic level is used to generate the overflow detector signal and the average counts as described below.
  • the count contained in the auxiliary counter 24 is continuously monitored by the overflow detector 72 shown in FIG. 6 which consists of a four bit binary comparator 144 coupled with two NAND gates 146, 148. One side of the comparator is connected to the output of the counter via lines 76 and 150, while the other four bit input has the least significant bit connected to the logic one" and the three more significant bits connected to line 152 via line 74 and line 152 such that for a high logic level on line 152 indicating a zero or positive count in 138 the count is compared to binary 1 1 l 1 and for a low state on line 152 0001 indicating in twos complementary form a 15.
  • the lines 70A and 70B will be 'high so that a low state on 70A indicates counter 138 is in an overflow state in the forward direction and a low state on line 708 indicates an overflow condition in the reverse direction.
  • These signals are used as described in the logic gating network 58 to control the transmission of clock pulses.
  • FIG. 7 shows the sampler-averager 32 arrangement of the preferred embodiment in some detail.
  • This arrangement includes a five bit shift register 160 which receives the count in the auxiliary counter in parallel fashion on inputs A A A and A and the sign on line T52 into input A., upon the application of a control pulse for circuit 48 received over line 162. This count is then added in serial fashion into an accumulator 164 which is composed of a pair of eight bit shift registers 166 and 168 coupled together to form a 16 bit shift register.
  • the shifting of the registers 160, 166, and 168 is controlled by pulses received from circuit 48 via line 170, while the adding is carried out by adder 172 which carries stored in a .l-K flip-flop 174.
  • the correct higher order digits are automatically added into the accumulator 164 in shifts over the fourth flipflop, i.e., zeros for forward binary counts and ones for reverse counts in twos complementary form in which form the reverse counts are received from the auxiliary counter 24 as described supra.
  • the sample register 160 is then reset by a signal received over line 178 from the clock and sequencing circuitry 48 and the cycle repeats itself.
  • 128 samples have been transferred successively into the sample register 160 and added into the accumulator 164 so that the shift registers 166 and 168 contain the sum of the 128 samples.
  • the sample number 128 was chosen since it is a power 0f2 (2 and hence may be conveniently averaged by shifting the sum seven binary places to the right, which is accomplished in the present embodiment by reading the four flip-flops seven places to the left in the accumulator 164, over lines 80.
  • the sign of the average may be read at one of the higher order bits to the left of the average flip-flops as on line 82, since the higher order bits will either be all ones indicating a twos complement binary number, and a reverse count or zeros indicating a binary positive count and a forward count.
  • the average count read over line and its sign read over line 82 are entered into the average counter 62 and associated sign flip-flop 78 with the accumulator then cleared by a signal received from circuit 48 over line 80 to ready a new averaging cycle.
  • FIG. 8 shows the average counter 62 in some detail together with its associated sign flip-flop 78.
  • the average counter 62 consists of a four-bit up-down counter 182 with its inputs connected to lines 80 and its outputs connected to a four input NOR gate 184 such that a logic one appears on line whenever no count is contained in counter 182, to thus provide the non-zero signal discussed supra.
  • Count up of the register occurs on pulses received over line 94 (forward) and count down occurs on pulses receiver over line 96 as described above.
  • a forced zero control signal received over line 185 from the clock and sequence circuitry is applied to NOR gate 184 during data transfer to prevent false reading by the logic network 58.
  • the sign fed into flip-flop 78 results in a high signal on line 28 and a low signal on E with a forward count in the average register and a low signal on 28 and a high signal on 28 with these signals being fed into the gating network 58 for control of the clock pulses as described above.
  • the clock and sequencing control circuitry 48 is shown in detail in FIG. 9 and includes a source of square wave pulses 186 divided by a flip-flop 188, with the frequency of the pulses on line 56 being selected to be well above the maximum frequency at which pulses will be received from the transducer in order to insure proper functioning of the logic network 58.
  • the frequency of the source 186 was selected to be approximately 12 Mhz so that after division by a flip-flop 188 and AND gate 189 an 6 Mhz clock pulse runs on line 56.
  • the pulse train is further divided for control of the sampler-averager system by a one shot 190 shift register 192 combination.
  • the shift register shift input is connected to the 6 output of the shifted flip-flop 188 via line 194 so that it is shifted at a 6 Mhz rate.
  • the false output 4 of the one-shot 190 is connected to the serial input of the shift register 192, so that in the initial reset state, a one is fed into flip-flop of pin 3 of the shift register 190.
  • the oneshot is immediately triggered by the 1 transition of the flip-flop of pin 3 via line 196 so that the false output 4 is caused to go low for the duration of the one shots period, precluding any further counts from being entered into the shift register 192 for the duration of the astable period.
  • the one is propagated down the flip-flop and provides a sequenced timing signal at pins 5, 10, 12, and 13 for use in controlling the averaging circuitry.
  • Variation of the RC circuit 191 values will cause a variation in the period of the one shot to thereby cause a variation in the time interval of the sampling, i.e., the sampling rate. This will allow adjustment thereof to a sampling rate suited to the frequency of the disturbances in a particular installation.
  • Three four-bit binary counters 198, 200, and 202 are used to count the shift and add operations of the sample and average circuit 32.
  • the pulse from pin 30 of the shift register is transmitted via line 204 to line 170 to cause shifting of the shift registers as described infra, and with each such pulse a count is entered into counter 198 via line 206 to count the shifts.
  • the next pulse sets all the bits of counter 198 to zero, which condition is detected by AND gate 208 to thus produce a high state on line 210 after 16 shifts, which when combined with the sequencing pulse from pin 5 in the AND gate 212 produces the inverted control pulse on line 178 to reset the sample register.
  • the sixteenth shift signal on line 210 is also combined in AND gate 214 with a sequence pulse from pin 10, and a 12 Mhz clock pulse from the source 186, to produce a low logic level on line 216, which is in turn combined with the Q output of flip-flop 188 via line 218 in AND gate 220 such that a high pulse is produced on line 162 when AND gate 220 is qualified.
  • This pulse causes the transfer of data from the auxiliary counter to the sample register. it is selectively placed in time to insure a data transfer when the auxiliary counter is stable (not in process of changing state).
  • the sixteenth pulse also generates a carry pulse on line 222 to enter a count into counter 200, which is coupled to counter 202 via carry line 224.
  • a carry pulse on line 222 to enter a count into counter 200, which is coupled to counter 202 via carry line 224.
  • the 128th sample causes the bit on pin 11 of counter 202 to become one, which causes resetting of all three counters as well as providing a logic input to AND gate 226 via line 228 and a control signal (forced zero) on line 185 (inverted by 230).
  • a sequence pulse from pin of shift register 192 is combined in AND gate 226 to provide the control signal to lines 86 and 88. This signal transfers the shifted average to the average counter register 62.
  • the pin 11 bit level also is combined in AND gate 232 with a sequence pulse from pin 12 of the shift registor to produce the clear signal C on line 180.
  • a synchronizer and logic levels representing count pulses could be replaced by an arrangement in which a count pulse gating arrangement is combined with anti-coincidence circuits at the pulse summary junctions.
  • the average value of the samples taken of the count in the auxiliary counter may be added to the main register and taken from the auxiliary counter over a series of averaging cycles rather than in a single cycle as described in the specific embodiment.
  • any counter in which bidirectional signals, i.e., in which up down counting is performed, may advantageously utilize the principle of the present invention.
  • a counter averaging arrangement for averaging the net count of signals received from a bidirectional signal source comprising:
  • bidirectional main counter means for counting said bidirectional signals
  • bidirectional auxiliary counting means for counting said bidirectional signals; directing means for causing only said auxiliary counter means to receive and count said bidirectional signals until the capacity of said auxiliary counter means to count further signals in one or the other direction is reached, and causing additional source signals in said one or the other direc tion to be counted by said main counting means as long as said auxiliary counting means cannot count signals in said one or the other direction;

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Cited By (12)

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US3849635A (en) * 1973-04-12 1974-11-19 Rca Corp High speed programmable counter
US3956616A (en) * 1974-05-06 1976-05-11 Knollenberg Robert G Method and apparatus for generating a statistical basis
US3982107A (en) * 1974-09-09 1976-09-21 American Electronic Laboratories, Inc. Reversible measuring means
US4081661A (en) * 1976-09-13 1978-03-28 Durbin John R Flow line counter incorporating programmed reversal circuitry
EP0025724A1 (en) * 1979-08-31 1981-03-25 The Bendix Corporation Method of making measurements on an object by means of a movable probe
US4266215A (en) * 1978-11-16 1981-05-05 The Raymond Corporation Reversible incremental encoding method and apparatus
US4524346A (en) * 1981-07-03 1985-06-18 Texas Instruments Incorporated Circuit arrangement for converting an analog AC voltage signal to a digital signal
US4528682A (en) * 1980-03-14 1985-07-09 Mutoh Industry Ltd. Digital measuring instruments
US4982413A (en) * 1988-05-06 1991-01-01 Heidelberger Druckmaschinen Ag Method and device for evaluating signals of an incremental pulse generator
US5672863A (en) * 1995-06-07 1997-09-30 Owens-Brockway Glass Container Inc. Anti-dither optical container sensor with sensors separation measurement
US20160164616A1 (en) * 2014-12-08 2016-06-09 Walid Khairy Mohamed Ahmed Circuits, Systems and Methods of Hybrid Electromagnetic and Piezoelectric Communicators
US10756811B2 (en) 2017-09-10 2020-08-25 Mohsen Sarraf Method and system for a location determination using bi-modal signals

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DE3207093A1 (de) * 1982-02-27 1983-09-15 Kollsman System-Technik GmbH, 8000 München Schaltungsanordnung zur mittelwertsbildung

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US3353161A (en) * 1965-06-23 1967-11-14 Hughes Aircraft Co Electrical control system for machine tool device with overshoot correction feature
US3500023A (en) * 1966-11-09 1970-03-10 Atomic Energy Commission Stutter counting circuit for a digital control system
US3571575A (en) * 1967-06-28 1971-03-23 Rank Organisation Ltd Measurement devices
US3585372A (en) * 1969-10-01 1971-06-15 Hughes Aircraft Co Electrical control system
US3644718A (en) * 1968-05-20 1972-02-22 English Electric Co Ltd Pulse-counting arrangements

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US3209130A (en) * 1962-04-30 1965-09-28 Westinghouse Electric Corp Digital measuring device
US3353161A (en) * 1965-06-23 1967-11-14 Hughes Aircraft Co Electrical control system for machine tool device with overshoot correction feature
US3500023A (en) * 1966-11-09 1970-03-10 Atomic Energy Commission Stutter counting circuit for a digital control system
US3571575A (en) * 1967-06-28 1971-03-23 Rank Organisation Ltd Measurement devices
US3644718A (en) * 1968-05-20 1972-02-22 English Electric Co Ltd Pulse-counting arrangements
US3585372A (en) * 1969-10-01 1971-06-15 Hughes Aircraft Co Electrical control system

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3849635A (en) * 1973-04-12 1974-11-19 Rca Corp High speed programmable counter
US3956616A (en) * 1974-05-06 1976-05-11 Knollenberg Robert G Method and apparatus for generating a statistical basis
US3982107A (en) * 1974-09-09 1976-09-21 American Electronic Laboratories, Inc. Reversible measuring means
US4081661A (en) * 1976-09-13 1978-03-28 Durbin John R Flow line counter incorporating programmed reversal circuitry
US4266215A (en) * 1978-11-16 1981-05-05 The Raymond Corporation Reversible incremental encoding method and apparatus
US4550418A (en) * 1979-08-31 1985-10-29 The Warner & Swasey Company Method of making coordinate measurements
EP0025724A1 (en) * 1979-08-31 1981-03-25 The Bendix Corporation Method of making measurements on an object by means of a movable probe
US4528682A (en) * 1980-03-14 1985-07-09 Mutoh Industry Ltd. Digital measuring instruments
US4524346A (en) * 1981-07-03 1985-06-18 Texas Instruments Incorporated Circuit arrangement for converting an analog AC voltage signal to a digital signal
US4982413A (en) * 1988-05-06 1991-01-01 Heidelberger Druckmaschinen Ag Method and device for evaluating signals of an incremental pulse generator
US5672863A (en) * 1995-06-07 1997-09-30 Owens-Brockway Glass Container Inc. Anti-dither optical container sensor with sensors separation measurement
US20160164616A1 (en) * 2014-12-08 2016-06-09 Walid Khairy Mohamed Ahmed Circuits, Systems and Methods of Hybrid Electromagnetic and Piezoelectric Communicators
US9467235B1 (en) * 2014-12-08 2016-10-11 Walid Khairy Mohamed Ahmed Circuits, systems and methods of hybrid electromagnetic and piezoelectric communicators
US9787413B2 (en) * 2014-12-08 2017-10-10 Walid Khairy Mohamed Ahmed Circuits, systems and methods of hybrid electromagnetic and piezoelectric communicators
US20190245628A1 (en) * 2014-12-08 2019-08-08 Walid Khairy Mohamed Ahmed Method and Apparatus for a Wireless Charging and Communication System
US11115133B2 (en) * 2014-12-08 2021-09-07 Walid Khairy Mohamed Ahmed Method and apparatus for a wireless charging and communication system
US10756811B2 (en) 2017-09-10 2020-08-25 Mohsen Sarraf Method and system for a location determination using bi-modal signals

Also Published As

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IT955686B (it) 1973-09-29
DE2225462A1 (de) 1972-12-14
GB1353836A (en) 1974-05-22
CA936246A (en) 1973-10-30
FR2138960B1 (online.php) 1973-07-13
AR192784A1 (es) 1973-03-14
DE2225462B2 (de) 1978-10-26
FR2138960A1 (online.php) 1973-01-05
CH552850A (fr) 1974-08-15

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