US3739199A - Generator of a time interval as a multiple of a base period - Google Patents

Abstract

A standard time interval having a well-defined duration for use as a time measurement reference is delimited by two fronts separated by N periods of an oscillation having a preferably rectangular waveform and produced by a frequency standard oscillator. The generator comprises a trigger circuit which transmits clock pulses and synchronizes them with the fronts derived from the oscillator, a preset counting register operated by the clock pulses, two detectors for selecting the active clock-pulse fronts and each comprising a delay line, two amplifying circuits for collecting the active fronts and converting them into utilizable signals.

Description

mte tates ate 3 1 1 1111 3,739,199 Negrou June 12, 1973 [54] GENERATOR OF A TIME INTERVAL AS A 3,509,473 4/1970 Porta 328/129 X L I L OF A BASE PERIOD 3,564,426 2/1971 Anderson et al. 328/48 3,657,658 4/1972 Kubo 328/48 X Inventor: Jacques Negrou, Gesta, France Commissariat A LEnergie Atomique, Paris, France Dec. 16, 1971 Assignee:

Filed:

Appl. No.:

References Cited UNITED STATES PATENTS 11/1966 Poole 328/48 8/1950 Grosdoff 328/48 12/1960 Sterk 328/129 X 3/1966 Madsen et al 328/48 X 2/1968 Mester 328/48 Primary ExaminerStanley D. Miller, Jr. Attorney-William B. Kerkam, Jr.

[57] ABSTRACT A standard time interval having a well-defined duration for use as a time measurement reference is delimited by two fronts separated by N periods of an oscillation having a preferably rectangular waveform and produced by a frequency standard oscillator.

The generator comprises a trigger circuit which transmits clock pulses and synchronizes them with the fronts derived from the oscillator, a preset counting register operated by the clock pulses, two detectors for selecting the active clock-pulse fronts and each comprising a delay line, two amplifying circuits for collecting the active fronts and converting them into utilizable signals.

8 Claims, 8 Drawing Figures PD COUNTDOWN REGISTER AMPLIFIERS OOINCIDENCE cmculr l Patented June 12, 1973 4 Sheets-Shut 2 JREQUENCY OSCILLATOR MONOVIBRATOR 93%? NC I F42 DIFFERENTIATOR 70 AL M monv FIG-4 74/1 DIRECTBIAS CURRENT GENERATOR MEMORY CELLS DIODE SNAP-OFF Patented June 12, 1973 4 Shack-Shoo 3 nmol mOhumhwo HER "Kuhn-0mm ZBOOFZDOO Patented June 12, 1973 3,739,199

4 Sheets-Sheet 4 GENERATOR OF A TIME INTERVAL AS A MULTIPLE OF A BASE PERIOD This invention relates to the controlled production of a standard time interval, that is to say of a time interval having a duration which is defined and known with a high degree of accuracy in order txat it may be used as a time measurement reference.

It is already a known practice to make use of the socalled frequency standards such as oscillator devices which deliver a periodic signal having a particularly stable and well defined period T and to apply the potentialities offered by these devices to the production of time standards (atomic clock, for example). However, it is not possible to produce a standard time interval and one interval alone by means of these methods or by means of the devices for carrying them out and the duration of this interval cannot be varied at will.

This invention is directed to a standard time generator which employs as in the prior art a periodic oscillation having preferably a substantially rectangular waveform and a known period T, said oscillation being produced by a frequency standard oscillator. A number N of periods is counted from a predetermined instant which defines the beginning of the standard time interval and the instant which terminates the N" period defines the end of the standard time interval.

If the generator collects two frequency standard clock-pulse fronts which are spaced at a distance of N periods and employs these latter in order to initiate a certain number of operations in complex circuits, the standard obtained as an end result is finally delimited by electric signals produced by said circuits from the clock-pulse fronts.

A number of difficulties are encountered in the practical definition of the standard time interval and these are mainly as follows:

the two clock-pulse fronts which will serve to define the beginning and the end of the standard interval must be isolated without disturbing this latter;

the two channels for transferring said clock-pulse fronts into the generator must be identical from the electrical point of view and must especially have the same transit time;

each clock-pulse front which is employed must be translated in a highly reproducible manner up to the output of the circuits of the generator.

A preferred alternative embodiment of this invention is concerned with a standard time interval generator which makes it possible to overcome the disadvantages referred-to above and in which the clock-pulse fronts themselves define directly and without any intermediate generator circuit the limits of the standard time interval which it is desired to produce since the clock is coupled directly to the output circuits of the generator.

This alternative embodiment does not directly employ the pulse fronts collected at the output of detectors which serve to detect the first and N" pulse fronts but employs them as gate-control signals in order to obtain synchronization with the clock. In consequence, the n" and (N n.)" pulse fronts are transmitted to output amplification and shaping circuits.

The generator for producing a standard time interval 1' NT delimited by two fronts separated by N periods of a periodic and preferably substantially rectangular oscillation having a period T and generated by a frequency standard oscillator, is characterized in that it comprises in combination:

a circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator, only those pulses of said oscillator which come after an order given by said trigger circuit and are referred-to as clock pulses being transmitted by means of said circuit,

a counting register constituted by a count-down register which can be preset at the number N of periods intended to constitute the time standard, and the operation of which is initiated by the arrival of the clock pulses,

a first detector for detecting the n" active clockpulse front at the output of the synchronizing circuit and comprising a first matchable delay line,

a second detector for detecting the (N n)" active clock-pulse front, said detector being controlled by the counting register and comprising a second matchable delay line,

two identical output amplifying circuits for collecting respectively and directly said n and (N n)"' active clock-pulse fronts which the first and the second detectors have selected and allowed to pass in order to convert them into utilizable signals.

In accordance with a further characteristic feature of the generator which forms the subject of this invention, the first detector for detecting the n" active clockpulse front is constituted by a memory cell, a delay line and an AND-gate, the first input or so-called permission input of said gate being coupled to the output of the delay line and the second input being coupled to the clock.

In accordance with another preferred characteristic feature of this invention, said counting register which can be preset at the number N is a count-down register and said second detector for detecting the (N n)" active clock-pulse front comprises:

a detector for detecting the zero of the counting register, constituted by AND-gates which receive the indications of state of all the dividers constituting the register,

a second memory cell mounted immediately after said zero detector,

a second delay line,

and a second AND-gate of which the first input or socalled permission input is coupled to the output of said second delay line and the second input of which is coupled to the clock.

In accordance with yet another preferred characteristic feature of this invention, said circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator comprises a first synchronizing circuit constituted by a memory cell which receives the trigger pulse and is coupled to the permission input of an AND-gate of which the second input is coupled to the standard oscillator, and a second synchronizing circuit which is identical with the first and connected to the output of the first by means of a delay line, the output of the AND-gate of said second circuit being intended to generate said clock pulses.

The value of the time-delay d -r of said line is chosen so as to ensure that the time of transit of a pulse within the AND-gate of said first synchronizing circuit, said delay line and the memory cell of said second synchronizing circuit is longer than the width of the pulse of the frequency standard oscillator, with the result that the pulse which opens the AND-gate of said first synchronizing circuit cannot also pass through the AND-gate of said second synchronizing circuit.

In accordance with another basic design feature of the time interval generator which forms the subject of the invention, the n'" and (N n)" active clock-pulse fronts are transmitted respectively and directly to the two identical output amplifying circuits through said two AND-gates which form part respectively of the first and second detectors.

The adjustable time-delays chosen, namely d-r, and d-r respectively of the first and second detectors, are such that the n" active clock-pulse front should be the first to be detected by the first detector, that the (N n)" active clock-pulse front should be the first to be detected by the second detector and that the permission for opening each gate of the first and of the second detector respectively should be given a sufficient length of time beforehand with substantially the same phase lead with respect to the n" and to the (N n) active clock-pulse front respectively.

Finally, in accordance with the invention, each output amplifying circuit of the generator comprises a memory cell, a differentiating circuit, an amplifier proper, and a stage for injecting inverse current into a snap-off diode which is in turn under the control of a current having a variable bias as a function of the temperature. This last-mentioned feature makes it possible to maintain at identical values the respective transit times of the signal between the input and the output of each amplifying circuit.

As is apparent, one of the properties of this generator lies in the fact that the first detector must detect only the n" active clock-pulse front and preferably the second. This is necessary by reason of the fact that the synchronization is not perfect, that the first pulse front emitted by the clock after a triggering order is always of slightly variable occurrence and it is advisable not to consider the first period. (For example, in the case of a rectangular oscillation having a period T which is equal to ns, this random variation is of the order of 100 ps). Since the second detector is adjusted so as to detect the pulse front of the order (N n) and preferentially the front of the order (N 2), the difference between the two detected fronts in fact remains equivalent to NT periods in accordance with the desired object.

Further characteristic features of this invention will in any case become apparent from the following description of one example of application of the method and of the generator for obtaining standard time intervals in accordance with the present invention. This description, which is given by way of indication without any intended limitation, will be given with reference to the accompanying diagrammatic FIGS. 1 to 5, wherein:

FIG. I is a general arrangement diagram which serves to illustrate the principle of operation of the generator in accordance with the invention;

FIG. 2 shows a memory cell which is employed in the generator according to the invention, respectively in its state X (FIG. 2a) and in its state Y (FIG. 2b);

FIG. 3, which is split up into two parts 3a and 3b for the sake of enhanced clarity, is a detailed diagram of the electronic circuitry of the generator of FIG. 1;

FIG. 4 is a detailed electronic diagram of one of the amplifiers of FIG. I;

FIG. 4a is a detailed electronic diagram of a portion of FIG. 4.

FIG. 5 is a diagram showing the time-variation of the different pulses which travel within the main circuits, respectively in the two detectors D, and D and in the amplifiers A, and A of FIG. 1.

The general arrangement diagram which is given in FIG. 1 represents a standard time interval generator in accordance with the present invention. There are shown in this diagram a frequency standard oscillator OE, a trigger circuit DEC and a circuit M4) for synchronizing this triggering order, a count-down register RD made up of five decade scalers in which the first scaler is split up into two sections, namely a scale-of-two divider and a scale-of-five divider. There is also shown in FIG. 1 the detector D, which is constituted respectively by a memory point 32, a delay line LR, and an AND- gate 4, the detector D which is constituted respectively by a coincidence circuit 49, a memory point 62, a delay line LR and an AND-gate 5 as well as two amplifiers A, and A The operation of the system as thus described is as follows: the number N of clock pulses with which it is desired to constitute the standard time interval is first indicated in the count-down register RD. When an order for initiating the production of the standard time interval reaches the line 1 (this order can be given either manually or in conjunction with an external and random phenomenon, or alternatively in a periodic form by means of relaxation oscillations), the trigger circuit DEC and the circuit M for synchronizing this triggering order permits the passage in the line 2 of the pulses emitted by the standard oscillator OE after the triggering order has been given, thereby obtaining the clock H. Within the detector D,, the memory point 32 changes state at the time of arrival of the front of the initial pulse of the clock H on the line 22, but the delay line LR, introduces in the step produced by said change of state a time-delay d'r,, with the result that said step is caused to arrive on the line 3a only after the end of the initial clock pulse. At this moment the sensitized gate 4 is ready to permit the transmission of the second pulse as soon as it arrives on the line 3b, said pulse being delivered by the clock H as a result of the triggering order. A step I, then passes into the amplifying circuit A, which delivers at S, a pulse representing the time of appearance of the second clock-pulse front.

As the clock pulses arrive on the line 2, so the countdown register RD begins to count-down and is cleared at the N" pulse as established by the zero detector 49; the memory point 62 then sends a step towards the delay line LR This step is transmitted to the second AND-gate 5 by the delay line LR only after a time delay dr The time-delay dr is so calculated that the preceding step reaches the AND-gate 5 only after extinction of the clock pulse of the order (N I), thus conditioning said gate 5 and then enabling this latter to permit the transmission of the clock pulse of the order (N 2) into the amplifying circuit A in the form of the step I Said amplifying circuit delivers at its output a pulse S corresponding to the pulse front of the clock H of the order (N 2). The standard time interval produced by the generator is defined by the time which elapses between the two small-width pulses S, and S Before proceeding to a more complete description of the electronic diagram of FIG. 3, there will now be described an electronic unit which is frequently employed in this diagram of FIG. 3 and designated throughout this description as a memory cell. This circuit is a bistable device RS, that isto say a circuit having two stable states X and Y, the state X being shown in FIG. 2a and the sate Y being shown in FIG. 2b. This memory cell of known type is made up of two identical logic circuits, namely a gate A and a gate B which are mounted as shown in the figure. The output of each gate is connected to the input of the other and the second input of the gate B is coupled to a zero reset circuit RAZ. In the figures, the voltages (zero or one) corresponding to the stable states have been indicated in each case.

Reference will now be made to FIG. 3, in which the functional elements already represented in detail in FIG. 1 are again shown and surrounded by dashed-line rectangles. There can thus be seen (in FIG. 3a) the line 1 on which the triggering order initiates operation of the trigger circuit DEC proper composed of a monovibrator 6 followed by a differentiator 8 which delivers the trigger pulse. The synchronizing circuit M proper which immediately follows is double; the first stage is made up ofa memory cell 10 and a gate 14, the permission input of which is coupled to said memory cell; the second stage is composed of a memory cell 12 and of a gate 16, the permission input of which is coupled to the memory cell 12, the gate 14 and the gate 16 being connected to the clock H; a delay line 18 separates the two synchronization stages and couples the gate 14 to the input of the memory cell 12. The line 2 in which the clock pulses travel from the output of the synchronizing circuits Md) is connected at 22 (see FIG. 3b) to the input of the detector D said line 2 is also connected at 24 through an inverter gate 26 on the one hand to the input of the scale-of-two divider 28 and on the other hand to the input 30 which is common to the gates 4 and 5. The detector D comprises the memory cell 32 whose output S is connected through the delay line LR, and the line 3a to the permission input of the gate 4.

The count-down register RD is made up of the scaleof-two divider 28, the scale-of-five divider 34 and the four decade scalers 36, 38, 40 and 42. The scale-of-two divider 28 is made up in known manner of a memory cell 44 and of two AND- gates 46 and 48.

The coincidence circuit 49 is made up of the complete assembly of six AND- gates 50, 52, 54, 56, 58 and 60. The first five gates are coupled respectively to the scale-of-five divider 34 and to the four decade scalers 36, 38, 40 and 42 and are mounted between them in series. An AND-gate 60 receives both the signal delivered from the gate 44 of the divider 28 and the matched output of the AND-gate 50. The output of the gate 60 leads to a memory cell 62. The output E of said memory cell is connected through the delay line LR to one of the inputs of the gate 5.

The inputs of two memory cells 64 and 66 are driven from the output of the two AND- gates 4 and 5 and each form part of the amplifying circuits A, and A respectively; the description of one of these latter will now be given with reference to FIG. 4.

There is shown in FIG. 4 a memory cell 64 followed by a differentiator 65, an amplifier 68 proper and a current-injecting stage 70 formed by a transistor T which injects an inverse current I into a snap-off diode 72; an element 74 controls the operation of this diode 72 by producing a direct-biascurrent i, and by adjusting the value of this current in dependence on the ambient temperature in such manner as to ensure that the pulse transit time remains constant and identical in both amplifying circuits. Finally, a diode 76 is placed in the circuit in the forward direction towards the output S.

The element 74 comprises one or a number of diodes representing the temperature variation and connected to the input of an operational amplifier followed by an emitter-follower amplifier; the current delivered by this amplifier assembly varies as a function of the voltage developed across the terminals of said diode; this compensates for the variation in life-time of the carriers in the snap-off diode, with the result that the overlap time of the snap-off diode remains constant as a function of the temperature. The elements are identical in both channels. As seen in FIG. 4a, element 74 includes resistance r r r and r and a transistor T of the NPN type whose base is connected to the output of an amplifier A. The emitter of transistor T is connected through resistance r,,- to a source of potential -V,, and to the inverse entry of amplifier A through resistance r The collector of the transistor is connected to transistor 70. The diodes D compensate for temperature effects on the snap-off diode 72. Voltages V and V regulate the value of the current i and the gain of amplifier A (resistances R and R fixes the relation between the temperature and the current The amplifying device of FIG. 4 makes it possible to obtain a step which has an amplitude of 20 V and a rise time of approximately 300 ps while being in welldefined and stable phase relation with an active front of the clock; its output can be connected to a low impedance such as 50 ohms, for example.

The general operation of the system will now be described below with reference in particular to FIGS. 3a, 3b and 5. For the sake of greater clarity, the binary transitions from 1 to 0 or from O to l which take place at the different stages of this operation have been represented in situ by means of arrows.

At the time of arrival of a triggering order on the line 1 (FIG. 3a), the monovibrator 6 and the differentiator 8 emit a triggering pulse which causes a change of state of the memory cell 10 of the first stage of the synchronizing circuit Md); the gate 14 then permits transmission of the pulse which is derived from the standard oscillator OE and appears first; this latter is retarded by the delay line 18; the retarded pulse causes a reversal of state of the memory cell 12 of the second stage of the synchronizing circuit, thereby permitting the transmission through the gate 16 of the pulse derived from the following standard oscillator; synchronization is thus carried out and has permitted transmission to the line 2 of the clock pulses H as represented at D in FIG. 5. The design function of the delay line 18 is to prevent the pulse which has been transmitted by the gate 14 and has changed the state of the memory point 12 from again passing through the gate 16 by virtue of the speed of the circuits employed and of the width of the pulses of the standard oscillator OE. The assembly consisting of gate 14, delay line 18, memory point 12 makes it possible to ensure opening of the gate 16 at a correct instant, with the result that the first clock pulse which appears on the line 2 is strictly in phase with the pulse derived from the standard oscillator OE and that the initial clock period is strictly equal to that of the standard oscillator OE.

Before switching-on the apparatus, all the memory cells had been reset to zero by the circuits provided for this purpose and designated in FIGS. 3a and 3b by the letters RAZ and were consequently in the state X corresponding to FIG. 2a. It will be noted that the reset pulse which is applied to the memory points 10 and 12 prevents the pulses derived from the standard oscillator OE from arriving on the line 2. The arrival of the first pulse front of the clock H on the line 2 at the output of the synchronizing circuit Mqb causes a change of state of the memory cell 32 and there is found at the output the step which is indicated in FIG. 5 and displaced by a time interval 1', corresponding to overstepping of this circuit 32 with respect to the leading edge of the initial pulse of the clock H. The memory cell 32 of the detector D1 has changed to state land the change-over to the zero state at the output S permits with a time-delay a 'r introduced by the delay line LR the opening of the gate 4 by the following second pulse front of the clock H. The displacement d'r of the state of the line g with respect to the state S of the same line 81 is shown at D1 in the diagram of FIG. 5 and is chosen so as to be located after the initial pulse of the clock and nevertheless at a sufficient distance from the second to enable the circuit to prepare for the reception of this second pulse. Said second pulse gives rise at the output S, of the memory cell 64 to a pulse I which is delayed by 1- with respect to the second pulse E, this wave being in turn delayed with respect to H by the time interval T2. In the example described, the period D of the clock H is 10 ns; this clock is a quartz oscillator having a frequency of 5 Mc/s followed by a scale-of-twenty multiplier in order to attain a frequency of 100 Mc/s, the last stage of the multiplier being a quartz filter which operates at I00 Mc/s. It is apparent from the diagram of FIG. 5 that the time-delay of a -r which has been chosen is of the order of 3 ns.

The clock pulses on the line 24 arrive at the inverter gate 26 which delivers at its output, with a time-delay 7 resulting from the transmission through said gate 26, a signalfi which is shown in FIG. 5 at D and D At this moment, the count-down register RD comes into operation; as the different decade scalers are cleared, so the AND- gates 58, 56, 54, 52 come into operation until the gate 50 which is in turn sensitized causes the initial state on the line 78 constituting one of the inputs of the AND-gate 60 to change from one to zero. This change of state takes place after the point of the order (N l) with a time-delay 1- which is substantially equal to 8 ns corresponding to the propagation time within the scaleof-two divider 28, the first flip-flop of the scale-of-five divider 34 and the gate 50. When the scale-of-two divider 28 also arrives at zero and when the second input of the gate 60 changes state from one to zero on the line 80, this gate in turn transmits a signal in the form of a change of state from zero to one within the memory cell 62. This change of state takes place at N'" pulse with, as indicated in FIG. 5 at D reference 80, a timedelay 1-,, of approximately 8 ns with respect to the front of the N"' pulse I-I resulting from the passage of the pulses within the scale-of-two divider 28.

There appears at the output of the memory cell 62 the step S? which is delayed by 1 with respect to the signal Q1 by reason of the time of transit within the AND-gate 60 and the memory cell 62; there then appears at the input of the gate 5 the step S as deducted from the preceding by the time-delay d'r which is introduced by the line LR The amplitude (172 of this timedelay is chosen in such manner that the step C takes place after the disappearance of the pulse of the order (N l) of the clock H. At the output 8, of the memory cell 62, there is then obtained the pulse 1 (at A of FIG. 5) which occurs only after a time interval which is displaced by -r with respect to the leading edge of the pulse of the order (N 2) of the clock H by reason of the transit time within the AND-gate 5 which is identical with the AND-gate 4 and within the memory cell 66 which is identical with the memory cell 64.

Finally, the third portion (A and A of the diagram of FIG. 5 shows how the final pulses S1 and S2, the spacing of which defines the time standard produced, are obtained through amplifiers A1 and A2 in accordance with the diagram of FIG. 4 from pulses l1 and I2 which are delivered respectively by the memory cells 64 and 66.

I claim:

1. A generator for producing a standard time interval 1' NT delimited by two fronts separated by N periods of a periodic and preferably substantially rectangular oscillation having a period T and generated by a frequency standard oscillator, wherein said generator comprises in combination:

a circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator, there being transmitted by said circuit only those pulses of said frequency standard oscillator which come after an order given by said trigger circuit as clock pulses,

a counting register constituted by a count-down register which can be preset at the number N of periods to constitute the time standard, and the operation of which is initiated by the arrival of the clock pulses,

a first detector for detecting the n'" active clockpulse front at the output of the synchronizing circuit,

a second detector for detecting the (N n)" active clock-pulse front, said detector being controlled by the counting register,

two identical output amplifying circuits for collecting respectively and directly said 11 and (N n)" active clock-pulse fronts which the first and second detectors have selected and allowed to pass in order to convert them into utilizable signals.

2. A generator according to claim 1, wherein the first detector for detecting the n active clock-pulse front is constituted by a memory cell, a delay line and an AND-gate, the first permission input of said gate being coupled to the output of said delay line and the second input being coupled to the clock.

3. A generator according to claim 1, wherein said counting register which can be preset at the number N is a count-down register and said second detector for detecting the (N n)"' active clock-pulse front comprises:

a detector for detecting the zero of the counting register constituted by AND-gates which receive the indications of state of all the dividers constituting the register,

a second memory cell mounted immediately after said zero detector,

a second delay line,

and a second AND-gate of which the first permission input is coupled to the output of said second delay line and the second input of which is coupled to the clock.

4. A generator according to claim 1, wherein said circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator comprises a first synchronizing circuit constituted by a memory cell which receives the trigger pulse and is coupled to the permission input of an AND-gate of which the second input is coupled to the standard oscillator, and a second synchronizing circuit which is identical with the first and connected to the output of the first by means of a delay line, the output of the AND-gate of said second circuit being intended to generate said clock pulses.

5. A generator according to claim 2, wherein the adjustable time-delays d'r and 111- of the delay lines of the first and of the second detector respectively are chosen in such manner that the n" or the (N n)" active clock-pulse front is the first to be detected by the corresponding detector and that the permission for opening each gate of the first and of the second detector respectively is given a sufficient length of time beforehand with substantially the same phase lead with respect to the n" or the (N n)"' active clock-pulse front respectively.

6. A generator according to claim 1, wherein each output amplifying circuit comprises a memory cell, a differentiating circuit, an amplifier proper, and a stage for injecting inverse current into a snap-off diode.

7. A generator according to claim 6, wherein the snap-off diode of each output amplifying circuit is under the control of an element for producing a current having a variable bias as a function of the temperature in order to maintain at identical values the times of transit of the signal between the input and the output of each of the two amplifying circuits.

8. A generator according to claim 7, wherein said element comprises at least one diode, an operational amplifier whose input is connected to the terminals of said diode and an emitter-follower amplifier.

Claims (8)

1. A generator for producing a standard time interval Tau NT delimited by two fronts separated by N periods of a periodic and preferably substantially rectangular oscillation having a period T and generated by a frequency standard oscillator, wherein said generator comprises in combination: a circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator, there being transmitted by said circuit only those pulses of said frequency standard oscillator which come after an order given by said trigger circuit as clock pulses, a counting register constituted by a count-down register which can be preset at the number N of periods to constitute the time standard, and the operation of which is initiated by the arrival of the clock pulses, a first detector for detecting the nth active clock-pulse front at the output of the synchronizing circuit, a second detector for detecting the (N + n)th active clock-pulse front, said detector being controlled by the counting register, two identical output amplifying circuits for collecting respectively and directly said nth and (N + n)th active clockpulse fronts which the first and second detectors have selected and allowed to pass in order to convert them into utilizable signals.

2. A generator according to claim 1, wherein the first detector for detecting the nth active clock-pulse front is constituted by a memory cell, a delay line and an AND-gate, the first permission input of said gate being coupled to the output of said delay line and the second input being coupled to the clock.

3. A generator according to claim 1, wherein said counting register which can be preset at the number N is a count-down register and said second detector for detecting the (N + n)th active clock-pulse front comprises: a detector for detecting the zero of the counting register constituted by AND-gates which receive the indications of state of all the dividers constituting the register, a second memory cell mounted immediately after said zero detector, a second delay line, and a second AND-gate of which the first permission input is coupled to the output of said second delay line and the second input of which is coupled to the clock.

4. A generator according to claim 1, wherein said circuit for triggering and synchronizing with the fronts derived from the frequency standard oscillator comprises a first synchronizing circuit constituted by a memory cell which receives the trigger pulse and is coupled to the permission input of an AND-gate of which the second input is coupled to the standard oscillator, and a second synchronizing circuit which is identical with the first and connected to the output of the first by means of a delay line, the output of the AND-gate of said second circuit being intended to generate said clock pulses.

5. A generator according to claim 2, wherein the adjustable time-delays d Tau 1 and d Tau 2 of the delay lines of the first and of the second detector respectively are chosen in such manner that the nth or the (N + n)th active clock-pulse front is the first to be detected by the corresponding detector and that the permission for opening each gate of the first and of the second detector respectively is given a sufficient length of time beforehand with substantially the same phase lead with respect to the nth or the (N + n)th active clock-pulse front respectively.

6. A generator according to claim 1, wherein each output amplifying circuit comprises a memory cell, a differentiating circuit, an amplifier proper, and a stage for injecting inverse currenT into a snap-off diode.

7. A generator according to claim 6, wherein the snap-off diode of each output amplifying circuit is under the control of an element for producing a current having a variable bias as a function of the temperature in order to maintain at identical values the times of transit of the signal between the input and the output of each of the two amplifying circuits.

8. A generator according to claim 7, wherein said element comprises at least one diode, an operational amplifier whose input is connected to the terminals of said diode and an emitter-follower amplifier.

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