US3717757A

US3717757A - Traffic simulator

Info

Publication number: US3717757A
Application number: US00148757A
Authority: US
Inventors: D Falvert; J Clot; A Giraud; A Raciazek; G Authie
Original assignee: Compagnie Generale dAutomatisme SA
Current assignee: Compagnie Generale dAutomatisme SA
Priority date: 1971-06-01
Filing date: 1971-06-01
Publication date: 1973-02-20
Anticipated expiration: 1990-02-20

Abstract

Traffic simulator for vehicles on a unidirectional route, comprising a plurality of reversible counters for which the contents of each corresponds to the number of vehicles on a section of given length of the route, a plurality of analog converters each associated with a reversible counter, and a plurality of generators corresponding to two successive sections of the route and furnishing ''''substract'''' transfer pulses to the reversible upstream counter and ''''add'''' transfer pulses to the downstream counter, the upstream and downstream counters corresponding to the two sections concerned.

Description

United States Patent 1191 Falvert et al. [451 Feb. 20, 1973 54 TRAFFIC SIMULATOR 3,315,065 4/l967 Auer ..235 150.24 3,397,305 8/l968 Auer ..235/l50.24 [75] lnventorsl Dame Antony; 3,536,900 10 1970 lwamoto et al ..235 150.24

Raciazek, Paris; Gerard Authie, Toulouse; Jean Clot Montaudrani Primary Examiner-Felix D. Gruber Q Giraud Toulouse of Attorney-Sughrue, Rothwell, Mion, Zinn & Macpeak rance [73] Assignee: Compagnie Generale DAuto- ABSTRACT m'msmer Pans France Traffic simulator for vehicles on a unidirectional [22] Fil d; J 1 1971 route, comprising a plurality of reversible counters for I which the contents of each corresponds to the number [2]] Appl 148757 of vehicles on a section of given length of the route, a plurality of analog converters each associated with a [52] U.S. Cl. 235/184, 235/92 CV, 235/92 T reversible counter, and a plurality of generators cor- 23 5 1 5024 340/23 responding to two successive sections of the route and [51] Int. Cl. ..G06g 7/48, G06f15/48 furnishing substraet n f pulses to the reversible [58] Field of Search ....235/150.24, 184, 185, 92 CV, upstream unt a t ansf r pu to th 235/92 TC; 340/23 downstream counter, the upstream and downstream counters corresponding to the two sections concerned. 56 R f 1 e erences Clted T 8 Claims, 3 Drawing Figures UNITED STATES PATENTS 3,601,586 8/1971 Slavin ..235/92 CV M H Vs Vs PL'ER SUBTRACTOR MULTPL'ER SUBTRACTOR em 51 Gi si+T- Vi-T Vi X N VS-V1 AIM) .y

[CONVERTER Ai CONVERTER CONVERTER Ci "SUBTRAC on 1 11 1| 1| 1 1| 11 T 11 3 OuN ER DSUBTFACT COUNTER T ADD COUNTER P I P P I P P INDICATOR INDICATOR INDICATOR PULSE GEN.

PATENTEUFEBZOIHTS Ai CONVERTER I "SUBTRACT CONVERTER :ICOUNTER bcp C p INDICATOR INDICATOR INDICATOR I Vs Vi 1 'suER/xcToR .l/ X I v \10. V

AMPLIFIER 11 FIG. 2

INTEGR}ATOR, l 2

CONVERIEWQ S LOGIC v=v -1'= o [REG|STEn CLOCK INVENTORS f DANIEIL FALVERT ANDRE RACIAZEK 15 GERARD' AUTHIE' JEAN 'CLOT ALMN GIRAUD ATTORNEYS PATENTEDFEBao 191s I 7 l 7, 7 57 SHEET 20F 2- G 1-2 1 V's v v SUBTRACTOR MULTIPLIER 5' l ICONVERTER A'2/ C COUNTER CONVERTER P l )1 v P c2 P1 I A1 COUNTER ZDcp C112 POTENTIOMETER Cp COUNTER I SUBTRACTOR CONVERTR I" MULTIPLIER 8"2 A u TRAFFIC SIMULATOR The present invention concerns a traffic simulator, which may be used to simulate the flow of traffic units on a traffic route.

In our copending U.S. application, Ser. No. 17,104, filed Mar. 6, 1970, now U.S. Pat..-No. 3,686,492 there is described apparatus for simulating traffic on a network of traffic routes, each route being split into successive sections. To each section there corresponds an electrical capacitance whose capacitance value is representative of the traffic unit capacity of the route section concerned. The number of traffic units in each section corresponds to the instantaneous charge on the relevant capacitance, and the flow of traffic units from one section to the next is represented by the transfer of charge from one capacitance to the next.

With this apparatus, due to possible losses of charge which cannot be detected or compensated, the traffic simulation may not provide a required degree of preci- SIOII.

The present invention is intended to provide an improved traffic simulator.

In accordance with the present invention, a traffic simulator includes a respective reversible counter for each successive section of a uni-directional traffic route, each pair of successive counters having the counter outputs connected through respective digital to analog converters to respective inputs of a respective function generator providing at its output pulses applied to a subtract" input of the upstream counter of the pair and to an add input of the downstream counter of the pair.

A reversible counter is one in which pulses applied to one input, referred to in this specification as the add input, cause the instantaneous counted value to increase. Pulses applied to another input, referred to in this specification as the subtract input, cause the instantaneous count to decrease. Thus, at any particular time, the instantaneous count is the difference between the total number of pulses which have been applied to the add input and the total number applied to the subtract input.

The invention will now be described in more detail by way of examples only, and with reference to the accompanying diagrammatic drawings in which:

FIG. 1 is a diagram of a traffic simulator;

FIG. 2 shows part of the simulator in more detail; and

FIG. 3 shows a second form of simulator.

Referring to FIG. 1, a traffic simulator includes respective reversible counters C, C,, C, for each of three successive sections of a unidirectional traffic route.

It is to be understood that in practice a traffic route will be composed of a larger number of sections each provided with a respective counter C. Each pair of successive counters C has the counter outputs connected through respective digital-to-analog converters A to respective inputs of respective function generators, each such generator including a multiplier G and a subtractor S.

Each function generator provides at its output pulses applied to a subtract input of the upstream counter of the pair and to an add input of the downstream counter of the pair.

Thus, counters C, and C, have their outputs connected through respective converters A, and A, to

respective inputs of a generator comprising multiplier G, and subtractor S,.

Counters C, and C have their outputs connected through respective converters A, and A to respective inputs of a generator comprising multiplier G, and subtractor S,,,.

The output of multiplier G, is connected to the subtract input Dcp of counter C, and also to the add input Cp of counter C,. The output of multiplier G, is connected to the subtract input Dcp of counter C, and to the add input Cp of counter C Pulses at a desired frequency are applied to the C, or ADD" input of the first counter (e.g. counter C, by means of an adjustable pulse generator 9, for example.

Thus, as pulses are added to the count in counter C,, they are simultaneously deleted from counter C, to represent the passage of traffic units from the upstream route section to the downstream route section.

The converters A, A, and A provide respective analog output signals V, V, and V,,,, each reflecting the instantaneous count in the corresponding counter. This in turn is indicative of the number of traffic units currently on the corresponding route section.

Each subtractor S receives an input signal V s significant of the maximum number of traffic units which can be allowed on the corresponding route section. In each case, the subtractor S evaluates the difference between signal V which need not be the same for all route sections, and the output signal of the downstream converter A.

This difference signal is applied to one input of the corresponding multiplier G, the other input receiving directly the output of the upstream converter.

The device described permits traffic flow from an upstream to a downstream route section to be simulated, the flow being a function of the traffic concentration in the upstream section, but limited by the concentration in the downstream section.

If the number of units on the downstream section reaches the saturation value, the flow becomes zero.

Each function generator provides at its output pulses at a frequency proportional to the value of the signals applied to its inputs.

FIG. 2 shows in block diagram form one of the function generators. The subtractor S is indicated at 10 being connected to receive input signals V, and V It effects the difference of these two signals and the difference signal V V, is applied to one input of an analog relaxation amplifier 11 acting as the multiplier G,

The subtractor 10 includes a voltage-to-frequency converter providing at its output a stream of pulses at a frequency f, proportional to the difference V V,.

On a second input, the amplifier 11 receives the signal V, At its output, the amplifier 11 provides the product Q= K (V -V,)V, where K is a predetermined constant. This output signal consists of current pulses at the frequency f, dependent on V V, and with amplitude dependent upon the value of V,

The pulses are integrated in an integrator circuit 12 whose output is connected to a current-to-frequency converter 13 providing at its output pulses at a frequency f, constituting the output pulses applied to the subtract input of the upstream counter and to the add input of the downstream counter.

- These pulses maybe applied directly to the counters as shown in FIG. 1, but the system may be modified as shown in FIG. 2, by applying the pulses first to a shift register .15. The rate of advance of the shift register is controlled by a clock circuit 16, to simulate starting of the traffic units...

Each register such as is also provided with a logic circuit 17 connected to receive the instantaneous counts of the downstream and upstream counters; Itis arranged to indicate when their respective values are zero and equal to the maximum number of traffic units for the respective route section. When either of these situations occurs, the register 15 is reset to zero. The register 15 is also reset to zero by logic circuit 17 when the latter receives on ah input FR a signal indicating that the traffic units on the upstream section have been halted, for example by a red traffic light.

So far, the traffic simulator has been described with reference to a single continuous traffic route. Where the route is forked, or where another type of junction occurs, the simulator is modified. The counter associated with the last upstream route section before such a junction has its subtract input connected to a set of function generators each representing the passage of traffic units from the upstream section to one of the downstream sections. To this end, a circuit, suitably a potentiometer, is arranged to distribute the signal V from the single upstream section to each of the downstream sections.

A suitable circuit is shown in block diagram form in FIG. 3.

In FIG. 3, counter C is that for the last upstream route section before a junction, in this case a bifurcation. Counter C and C" are respectively associated with each of the downstream sections immediately following the last upstream section.

The output of counter C is connected through a digital-to-analog converter A to a potentiometric circuit P where the output signal V of converter A is converted into two equal signals, for example, V' and Vill- I Signal V' is applied to one input of a multiplier G and signal V" is applied to a corresponding input of a multiplier G Counters C, and C", have their outputs connected through respective digital-to-analog converters A, and A", to first inputs of respective subtractors S, and S" These are connected to receive" on respective second inputs signals V, and V These signals represent respectively the saturation values on each of the downstream route sections.

In the manner which has been described in more detail with reference to FIGS. 1 and 2, each of the rnultipliers G provides its output pulses applied to the "subtract input of counter C and simultaneously to the add input of the corresponding counter C The simulator of FIG. 3 may be provided with a register and logic circuit assembly such as that

compris ing elements

15, 16 and 17 in FIG. 2.

Each counter may be connected to a visual indicator arranged to display the instantaneous count. In this way changes in the state of each counter may be followed visually.-

One application envisaged for the simulator is the control of traffic control signals, such as those controlling traffic lights at road junctions in cities, for example.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that'various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims.

We claim:

1. A traffic simulator for a plurality of sections of a unidirectional traffic route along which simulated traffic units are assumed to be travelling in the direction from an upstream section to a downstream section comprising:

a. a plurality of reversible counters, each assigned to one of said sections;

b. a plurality of digital-to-analog converters;

c. means connecting the outputs of each pair of successive reversible counters to the inputs of respective ones of said converters;

d. a plurality of function generators for providing output pulses, the output pulses fromeach'generator having a frequency representative of the difference between the maximum number of traffic units allowed in the corresponding route section and the output of the adjacent downstream converter;

. means connecting the outputs of said converters to the inputs of respective ones of said function generators; and

. means for applying said output pulses to a subtract input of the upstream reversible counter of each pair of successive counters and to an add input of the downstream reversible counter of each pair of successive counters.

2. A simulator as claimed in claim 1 in which each function generator comprises a multiplier and a subtractor, said multiplier having one input connected to receive the output from said subtractor which provides an analog signal representing the difference between the maximum number of traffic units on the downstream section and the instantaneous count of the downstream counter, said multiplier having a second input connected to receive the output of the upstream digital-to-analog converter.

3. A simulator as claimed in .claim 2 in which each function generator further comprises an integrator and an analog-to-digital converter and means connecting the multiplier output through to said integrator and the integrator output to said analog-to-digital converter which provides at its output the pulses at a frequency proportional to the product of the two input signals of said multiplier.

4. A simulator as claimed in claim 3 in which each function generator further comprises a shift register and a clock circuit for controlling the rate, of advance of said shift register to simulate the starting up of the traffic units, means connecting the output of said analog-to-digital converter to said shift register, and means for applying the output pulses from each register to the subtract input of said upstream counter of said pair of successive counters and to the add input of said downstream counter.

5. A simulator as claimed in claim 4 further comprising for each shift register a respective logic circuit connectcd to receive the respective instantaneous counts of the downstream and upstream counters, and for indicating when they are respectively equal to zero and to the maximum number of traffic units for the respective route section, the logic circuit also providing an indication that the traffic on the upstream section has been required to halt, and means connecting the outputs of the logic circuit to return-to-zero inputs of said shift register.

6. A simulator as claimed in claim 1, in which the counter associated with the last upstream route section before a junction with two or more downstream sec- LII imum capacity is equal to the maximum number of traffic units on the respective route section.

Claims

1. A traffic simulator for a plurality of sections of a unidirectional traffic route along which simulated traffic units are assumed to be travelling in the direction from an upstream section to a downstream section comprising: a. a plurality of reversible counters, each assigned to one of said sections; b. a plurality of digital-to-analog converters; c. means connecting the outputs of each pair of successive reversible counters to the inputs of respective ones of said converters; d. a plurality of function generators for providing output pulses, the output pulses from each generator having a frequency representative of the difference between the maximum number of traffic units allowed in the corresponding route section and the output of the adjacent downstream converter; e. means connecting the outputs of said converters to the inputs of respective ones of said function generators; and f. means for applying said output pulses to a subtract input of the upstream reversible counter of each pair of successive counters and to an add input of the downstream reversible counter of each pair of successive counters.

3. A simulator as claimed in claim 2 in which each function generator further comprises an integrator and an analog-to-digital converter and means connecting the multiplier output through to said integrator and the integrator output to said analog-to-digital converter which provides at its output the pulses at a frequency proportional to the product of the two input signals of said multiplier.

4. A simulator as claimed in claim 3 in which each function generator further comprises a shift register and a clock circuit for controlling the rate of advance of said shift register to simulate the starting up of the traffic units, means connecting the output of said analog-to-digital converter to said shift register, and means for applying the output pulses from each register to the subtract input of said upstream counter of said pair of successive counters and to the add input of said downstream counter.

5. A simulator as claimed in claim 4 further comprising for each shift register a respective logic circuit connected to receive the respective instantaneous counts of the downstream and upstream counters, and for indicating when they are respectively equal to zero and to the maximum number of traffic units for the respective route section, the logic circuit also providing an indication that the traffic on the upstream section has been required to halt, and means connecting the outputs of the logic circuit to return-to-zero inputs of said shift register.

6. A simulator as claimed in claim 1, in which the counter associated with the last upstream route section before a junction with two or more downstream sections forming a fork or other junction has its subtract input connected to a set of said function generators each representing the passage of traffic units from the upstream section to one of the downstream sections.

7. A siMulator as claimed in claim 1 further comprising visual indicators for displaying the instantaneous counts in each counter.