US3702470A

US3702470A - Constant writing rate character generation and display system

Info

Publication number: US3702470A
Application number: US76912A
Authority: US
Inventors: Joseph E Bryden
Original assignee: Raytheon Co
Current assignee: Raytheon Co
Priority date: 1970-09-30
Filing date: 1970-09-30
Publication date: 1972-11-07
Anticipated expiration: 1989-11-07
Also published as: CA946962A

Abstract

A character generator in which strokes are generated to form characters wherein each stroke is treated as a vector whose end points are stored digitally. The characters are formed from a variable number of strokes which are of varying periodicity such that a constant writing speed is obtained regardless of the number of strokes required per character; the time for writing a particular stroke is proportional to the stroke length. Two sets of digital to analog converters sum analog signal outputs in two channels such that digital control signals are loaded into the digital to analog converters alternately while X and Y axis beam steering and appropriate blanking and unblanking signals are employed for stroke writing.

Description

United States Patent I OFFSQET' OFFSET CONTROL Bryden 1 Nov. 7, 1972 I [54] CONSTANT WRITING RATE 3,474,439 I I D/1969 Miners"; ..340/324 A CHARACTER GENERATION AND v DISPLAY SYSTEM 7 Primary Examiner-John W. Caldwell I Assistant Examiner-Marshall M. Curtis [72] Inventor: Joseph Bryan Frammgham Attorney-Milton D. Bartlett, Joseph D. Pannone, Mass- I '4 v I Herbert W; Arnold and David M. Warren 4 73 Ass nee: Ra theon Corn an Lexin on, I l 1 lg Ma ss. p y [571 ABSTRACT- [22] Filed; Sept 30, 1970 A character generator in which strokes are generated to form characters wherein each stroke is treated as a [21] PP 76,912 vector whose endpoints are stored digitally. The f 1 characters are formed from a variable number of 52 U.s. Cl. .340/324 A, 320/1 strokest'which are of varying Periodicity such that a 51 Int Cl ..G06t3/14' Writing speed is Obtained regardless of the [58] Fig." 340/324 320/] number of strokes required per character; the time for v writing a particular strokeis proportional to the stroke length. Two sets of digital to'analog converters sum [56] References analog signal outputs in two channels such that digital UNITED. STATES PATENTS control signals'are loaded into the digital to analog converters alternately while X and Y axis beam steer- 3'325'802 2 Bacon ing and appropriate blanking and unblanking signals A 3:296,609 1/1967 Wilhelmsen 340/324 A 5 Claims, 8 Drawing Figures 's fl I xggmggo SIGNAL 36 1/2 TRANSLA I20 EVEN 'X D/A /2a MULTIPLIER SIZE TRIANGLE AMPLIFIER X OUTPUT GENERATOR D/A PLIE 32 $24 CLAMP CLOCK D/A EVEN Y GENERATOR PUER 30 000 EVEN CLOCK IFIER OUTPUT D/A MULTIPLIER BLANK/ UNBLANKING CONTROL P'A'TENTEDNHT' 7 m2 A 3-.702.4 70

SHEET 1 (IF 5 /8 I CHARACTER /4 GENERATOR A T B LOCAL a LOCAP VECTOR h r BUFFER MEMORY GENERATOR i I POSITION CENTRAL l GENERATOR AIR COMPUTER TRAFF|C Q- DATA I i 2a /30 5 36 i CHARACTER I GENERATOR EL; f LOCAL LOCAL g VECTOR BUFFER T MEMORY GENERATOR\ 32 DISPLAY v POSITION GENERATOR Rf t +V 'f(t)) EVEN u 532 TO D/A v f(T)+v v flL) MULTIPLIERS.

TO OTHER 602 v STAGES V, /4 BIT INPUT 5-- P'A'TENTEDnuv 11912 sum 2 or 5 I X CHANNEL TIME FIG. '2,

FIG. 3

eousrsnrrwnrrructnxrnenamcrrnn g tGE-NERA IQNANH BP. SY

BAQ GR UND oarrriiNvaNnoN j This; inventionrelates; to:-,af constant;-speed gcharact'er generator in r-whichkcha'racters are developed f from a ,plurality of generated -.strokes';rwhichimay he ad- .vantageously lutilizeda in' zhigh datadensity=display,' such -asare usediniairtraffic controlsystems. t

, RInorder'to.-achieve';.highrefficiency in a cathode ray,

-.-tube., display. orstrok'e,;generator, it is important-that the writing speedzbe maintained substantially constant and that the blank ,beam l'ostitime gis minimizedi These criteria i are satisfied in a character -generator" in acicordance with the tpr'inciples of -the apresent invention :byselectingl a writing-timewhich.isclosely proportional to;the.writtenlineilength of thecharacterto be written.

, :suMM av OFTHE INVENTION stroke ,-generator for] character t-genera'ti'on is described in which 'azvariable numberlof'strokesis utilizedin; thez generation of characters for visual display. :Thetimeduration of individual strokes is" variable and {proportional to the. stroke length such that constant -writing-spe ed is'maintainedregardless of-the numberof stroke s'per character orthe strokelength. This variable :periodicity of f the :generatedstrokes? is obtained in a combined digital and analog system in which segment 7 z periodicity data, segment end pointdata, timing and The character-is composed of Iamumber-of @sectors'bf varying number and length :in accordance with the .characterdetail. Theltotalitime required to write agpar- =ticular character is maintained the :same regardless of the number :of strokes or the length :of ithe "strokes required :therefore by varying the segment tperiodicity,

or thetimeirequired fdr-thegeneration of:the particular stroke'orsegment.

' Aproblem of the prior artiscumulativelossiof-accuracy which occurs when the-end positions of seg- .ments are connected to form characters. The present invention -;uses a technique of combining positive and v negative going ramps 'of different amplitudes in idem, .cal time periods to define the itwo end positions and all intermediatepositions. The required amplitude is obtained byamultiplying digital :to analog converter co'ntrolled :by data-in :bit form obtained from read only memory. The advantage of using digital to analog converters to control the magnitudeiof the input-ramp is that large lquantities of digital words may be stored in i extremely compact devices. Furthermore, this selection ofv characters isobtained directly ffromthe digital numbers and no analog switching is required.

' ln systemsfof the prior art constant writing speedcould only be obtained by the use of complex and costly brightness control circuitry since the writing timeiis not porportional to the written line length in suchfsystems. L

In another system of the prior art a beam current in a cathode ray tube'displayis generated porportional to a control signal'definingthe length'of the vectorto be generated, thus, the intensity of 'the beam current is controlled as a function of the beam velocity to afford a uniform display intensity irrespective of the length or of the velocity of the vector, Howeyer, in such systems zunblanking-. data are digitally generated and suppliedto analog character generation circuitry. TheIrate supply ing'new digital wor'dszis "slow relativefto the rate at -whichthe-datais clocked intofthe analogcircuitry.

The digital signals received bythe analog circuitry lproduce coordinated 'X and Y channel waveforms and a blank/unblank signal to control the beam of a cathode ray tube to display cursive ly written charactersi The beam-on to beam offtime ratio'is maximized by generating just therequired numberof segments for 'any'particular character, and-writing withsubstantially a constantspeed. A widera'nge'of'seg'ment lengthis obtainablesucht'hata single segment is used for a straight line regardless ofits' le'ngth. Referencing is-provided to either-thecenteror acorner of thecharacter.

. Two triangular waveforms are generated "to form a bipolar output which is summed-to obtain a "resultant waveform which isa ramp connecting the segment end :points. A .novel triangle generator is described in which a positive or a negative voltage is developed depending upon whether a positive or negative ramp analog out- ;put is required. The value of current from selected positive and negative current sources is determinative of' the segment periodicity and is controlled digitally froma read only memory- The current sources are operative alternately, and duringinoperative periods,

data is'received tochange the triangle generator output to1digitaltoanalogniultipliersto thevalue required for the generation of the next-segment.

The triangle generator after amplification drives four digitalto analog multiplierswhich operate in pairs with their multiplying factor being controlled by a digital input and changeable only when there is zero analog in- .put. Thus, the digital word to the digital-to-analog multipliers is clocked in at alternate segment periods. For

example, while one multiplier of a pair is generating an odd" segment, the register of the other multiplier of complex intensity control circuitry is required and variably periodicity is not provided.

" In other systems of the prior art'the current required for stroke generation is proportional to the velocity of the specific embodiment in which the characters are formed from a plurality of individual strokes and which i used in connection with an air traffis 9m system, it is to be understood that the techniquesof the present 1 the stroke. While a character generator is described in invention couldapply equally w ell to other systems requiring a constant speed-character generator of high accuracy. L .With constant writing speed it':

:unblank' the beam and nbbrigh'tnss compensation signals are required 'for the cathode ray tube.

is only necessary to the pair is receiving new digital data for the generation of the next segment, or the evensegment; which is clocked in as the analog signal passes through zero.

BRIEF DESCRIPTION OF THE DRAWlNGS ofFlG. 2.

cordance withthepresent invention.

' FIG. 8 is a circuit diagram of a digital to analog multiplier in accordance with the principles of the present invention. I DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1 a block diagramof an air traffic control system embodying the present invention is illustrated generally at 10. Data from air terminals at various locations such as weather conditions, flight patdescribed with reference to FIG. 5. Toobtain constant writing speed, the periodicity of the ramps'must be present invention is shown generally at 100. A size and tern information, aircraft position and other data normally utilized by air controllers is inputted to a central computer '12'over a plurality of data channels A, B N at which point the data is stored and the appropriate information is relayed to the local airterminals and air.

controller points such as 14 where a local buffer interface transfers the appropriate data to a local memory 16 which supplies positional, character and vector information to a' character generator 18, a vector generator 20 and a positional generator 22 in accordance with the present invention. Vector generator 20 may be of conventional design as is the position generator 22 for controlling the deflection of the electron display beam of display 24 which may comprise a cathode ray tube. Other aircraft control points may be supplied in a similar fashion with a local buffer 26 receiving data in a parallel channel from the central computer 12 for transfer to a local memory 28 into the associated character generator 30, vectorgenerator 32 and position generator 34 for the. control of characters and vector-information on adisplay 36. I I

Referring now to FIGS. 2 and 3, the principle of character generation employed by the present invention is illustrated. Two triangular waveforms, V fU) and V (l-flt)) are multiplied by a gain function i'n digital to analog multipliers 50 and '52 respectively and varied, and the'condition forconstant writing speed is that (6X 5Y*)/'(3T is a constant, where ST is the period-.oftransition for 8X and BY. The SK and 6Y are.

the "deflection increments as scaledat "the display screen; The period of transitionjs determined by a seven-bit word that is predetermined and stored in a digital memory. Of course, the number of bits determinative' of the transition may be any amount desired. A-n unblankingbit is also stored in the digital memory in order to allow common formats for characters to be chosen which may be stored with'the digital. words. The

digital word may effectively consist of five bits for X,

five bits for Y, seven hits representative of time and three bits for unblanking for a total of 20 bits for each line segment. The three bits for unblanking allows choice of three unblanking sequences for a single writing pattern. I I I v g Referring now to FIG. 4 a block diagramof the analog portion of the character generator of the offset voltage control is inputted to a character size voltage generating circuit 102 and a character offset voltage generating circuit 104 for developing V and V respectively. A triangle generator 106 generates triangular pulsesof constant peak to peak amplitude with changing periodicity as is described with reference to FIG. 6. Thisseries of triangular pulses is generated only when an unclamping, signal inputted, to the triangle generator via line 108 is low, otherwise no triangular output is generated. The clamping control is described I with reference to FIG. 6. The amplitude of the generated triangular waveforms is determined by V with the slope of the positive going ramp determined by a seven-bit control signal received from a stroke segment memory via line 1 10 at digital to analog converter summed in a summing network 54. Digital inputs containing stroke end point data are applied to the digital to

analog multipliers

50 and 52 via data lines 56 and S8 respectively. Waveform Vgflt) is shown as A in FIGS."2 and 3 and is one input for the X channel of the stroke generator. Wavefonn V (l--f(t)) is shown as B in FIGS. 2 and 3 and is the other input for the X channel of thestroke' generator. The outputs of the digitalto

analog multipliers

50 and 52 are shown as A and B. The resultant R- is a ramp connecting the endpoints which are determined 'by the multiplying factor;

As is apparent from FIG. 3, the amplitude of R, at the beginning and end of each segment isdeterrnined by the gain factors of the :digital to analog multipliers 50 and '52 with the A and B channels alternately providing the end point values. The gain factors are controlled by 112 which is coupled to'a positive constantcurrent sourcein the triangle generator while the slope of the negative goingramp is likewise controlled by a sevenbit control signal inputted via line 116 to a digital to analog converter 114 which is coupled to a negative constant current sourcein the triangle generator control signal 116.

- A phase inverter 500 develops two phases of the triangular pulses as is described with reference to FIG. 7 and is capable of driving four digital to

analog multiplier

120, 122, 124 and 126 of the type described with respect to FIG. 8. Digital to analog multipliers through 126 each require five data bits to control the signal attenuation in a simple ladder network. The outputs of each pair of multipliers are summed atthe inputs to

line amplifiers

128 and 130. The outputs of

line amplifiers

128 and 130 are the drive signals supplied to the X and Y axes respectively of the character display. The offset voltage V,, developed'in offset generator 104 proportionalto the size of the character and to the character size voltage V is also added to the line amplitier's 128 and 130.

A comparator in the triangle generator 400 produces a square wave which is negative during the period of positive going ramps and zero, during the period of negative going ramps. This waveform is used to control gates for selecting the two phase blank/unblank signals obtained from the digital memory described 'with clock pulses from the risingedge of thesqua'rew'ave which are .coupled'to the D/ih'multiplierstoithe digital timingand. control logic. These 'clock pulses' cause the digital signals X and. Y to be loaded'into the live bit D/A multip iers 20 thr ieh mia d a also used to 1 activatethe digital'logicand memories. 1

. v The unblankingsignal is selected at unblanking gates at amplifier 13.4 from a" digital control signal from the digital timing and control 'logicand is amplified in the unblanking line amplifier 134.,Dot unblanking isobtained from a. monoshot circuit ,in'thetiming and control logic {fed to the unblank gates? g The digi al to analog'ml ltipliers 120 through 1 126 operate in pairs and are fedjfrom the two phase outputs from the phaseinverter 5.00.1t will be'obseryed thatthe multiplying factor controlled byfthe digitalinput to the digital to analog multipliers'is only changed when its analog input is at zero, in other words, the multipliers a e t d l in t ha seda th c mmsm ms wf alternate segment periods, hence-the terminology odd andevenX and :Y inputs to the BIA multipliersIThus, when a five bitsignal is 'being clockedthroughfa D/A multiplier after translation insignal translator 136, the other five-bit signalis being inputted to the other D/A multiplier for the same axis. The'outputs of each pair of multipliers are summed in a resistance network and amplified to drive a75ohm unbalanced lin v a R r i g n t G- 5 ls' d s al'p flion 9f h character generator is illustrated generally at 200. Timing'and control logic in the digital circuitry generates suitable clock pulses for unloading a read-only segment memory in whichthe; various stroke data is stored into the digital to analog converters in a timing sequence. Additionally,- the timing and control logic serves .to count the. number. of segment words for comparison with the number of words allocated for. any particular character and is automatically reset when that number has been reached..When reset, new characters may be generated upon receipt of load and start signals by the control logic. r

Data in the form of a six bit character codeplus pari ty enters the system "through the input logic shown generally at 202 which includes conventional shift registers 204 and the character address and control for a segment memory from which various control signals are derived as will be explained. In addition to the character code, size and offset control signals are received by a character code register 204, which are inverted by inverters 206 and Y208 with the. inverted signals'b'eing supplied to the analog size and offset circuitry described with reference to FIG. ,4. t o I A parity bit is received in a conventional manner at a parity checking circuit 210 of conventioiial 'design. If parity is correct, the six bit character code-and the size and offset signals, which are treated as data, are loaded into the character codere'gister 204 in accordance with 1* .6 is resetIto-all zeros. Even and .odd parity is imparted to the timing -andcontrol logic via lines 214 and 216 respectively, with the-appropriate clearingsignal being received-via line 21.8 from the timing andcontrol logic 220 at the character code-register.

The character codeis imputted to a read only startingaddre'ss and control memory .222'via line 2241if parity is correct. Memory 222 is formed of integrated circuit logic modules of conventional design, and may beconsidered to be a codetranslator that permits the association of any starting address for-the stroke segment memory with any six-ibitcharacter code. Thus,

where the input character code is standard ASCII, memory222 provides an address to the initial word in the segment memory, data'specifying the number of segment .words in the selected character, the location 1 of the desired two 'bit (blanking) within the segment word, and data to distinguish between normal cursively written characters, a dot, andu'nused character codes.

' Memory 222 is continuouslyaccessed by the character, code register 204 which supplies an enabling [signal in addition to the character, code. The memory portionof address and control circuitry222 effectively comprises four 256-bit memory chips of 64 words, each of 16-bit length. A common format occurs when the same portions of the segment memory are used for the generation of different characters, for example, the vertical line present in an.E,-an F,and-an l... Y

.1 The output portion'of the startingaddress and control memory comprises-four four-bit MSl generalpurpose Y registers which may beloaded simultaneously withone word fromthe memoryfor each character to baccessed f Y I a The segment memory 230 is a read only memory that containsall the data necessary to display the complete compliment of cursively written characters as well as a parity error symbol. The" segment memory is divided into six blocks of 32 words each giving a total capacity of 1 92 words, with each word defining two 20-bit-segments. The number of words per character format may vary, for:example'=, from one to eight with the present coding but may be as large as 16. While theoretically a format could be placed anywhere within the memory, in actual practice the'format location is limited to a single l6'-,wordsecti on so thatonly thefour least significant bits "of the address received on line 232 from the segment memory address register 234 are required to change during the display of a single character.

While the present design provides 41 formats including the parity error symbol it is to be understood that the memory may be expanded as desired in accordance with cor'iyentional integrated circuit techniques merely by adding additional memory circuit modules. For the displayof a given character the starting address and control memory 222 supplies the segment memory address register 234 with an eight-bit starting address. The register 234 is: a down-counter which .then proceeds to count down sequentially until it is commanded to clear to all zeroes by the timing and control logic 220 via the clear segment memory address re- "'gister line 236 JSincethere'is a logic inversion in each Thethree most significantbits of the comp'let'e'address are decoded in anaddress decoder 238 and'inputted via line 240 to enable one of the six blocks of tli'e segment memory. The reset word is located at the final address of the first block of the segment memory and 1 under normal operation the segment memory'will segment, each of which -bit half words comprises five bits to specify the horizontal or X end point of the segment, five bits to specify the vertical orY end point of the segment, seven bits tospecify a time number denoting the time duration of the segment and three bits, one for each of three possible characters within a format to specify whether the segment is blanked (a logical one) or unblanked (a logical zero) with the latter three bits being the blanking bits, or 2 bits.

Both halves of the memory output word are loaded into the'segement data memoryregisters at the same time. The segments however are processed sequentially through the rest of the circuitry with the first segment being the odd segment and the second segment being the even segment. The format may contain an odd or an even number of segments, if desired, while the second half of the last memory word isthe same asthe reset word. Z-bit, or blanking location information stored in the starting address and control memory 222 is loaded into the operation control register 242 in,

response to a loading signal online 244 from the timing and control logic. This blanking or Z-bit control is inputted on -line'246 to the Z bit selection'circuit 248 which is an MSI logical unit that performsa dual selection of a'pair (odd and even) of Z-bits from the sin Z- bits in the segment memory output supplied to. the Z-bit selector 248 on data line 250; The control signal online 246 comprises two bits which have the same value for all the words in ony character format. The outputs of the Z-bit selection logical unit 248 are cconnected to segment data registers 262and 264 of the output registers shown generally at 260 as will be explained; Timing signals are receivedby the word count register 266 from the control logic 220 on line268 and each zero count is received by the timing logic on line 270. The timing signals necessary for dot generation are received by the operation control register 242 via line 272 and dot command signals are inputted to the timing and control from the operation control register 242 via

lines

274 and 276. v

The output registers 260 or the segment data registers, consist of l l four-bit MSI shift registers. Five of these registers shown representatively as 280 are loaded in parallelwith ten odd and ten even bits of X and Y end point data, five bits for X, and five bits for Y, withthe odd segment bits alternating with the even'segmentbits.

Data lines

282 and 284 from the segment memory couple ten-bit outputs which are alternate physical locations of the stroke end point data to registers 2 80 andare connected directly tothe analog circuitry as described with reference to FIG. 4 via lines 286'arid 288 where they are received at the appropriate time by either of two odd br even high speed registers. The outputsof registers 280 will contain the odd seg'-' 8 ment data immediately after the segment data registers have "been loaded from the segment memory output were! At the next step in-the operating sequence registers 280 will receive a shift clock pulse from the timingand control logic 220 vialine 290 which causes the evehsegmem data't'o appear on the ten output lines. Froin'then on data lines 286 and 288 to the analog circuitrywill altemate with oddand even segments until a reset from the segmentmemory is loaded in response to a clock signal from the timing and controlling logic via line 292. Lines 286 and 288 which represent the segmerit end pointswill then remain-at a logical zero until the next character is processed. Since I there is no master clear it is necessary' to process at least one character after power turn on to arrive at the above logical zero condition.

SixMSI registers illustratively shown as

registers

262, 264, and 294 each of which comprisestwo registers, are used to process the time periods and blankingdata received via '

lines

296 and 250 respectively 2 (seven for time and one for blanking) corresponding to the odd segment eight bits corresponding to the even segment. The eight outputs from registers .264 which contains the odd segment data'are connected directly to the analog circuitry via line 298. The eight outputs from registers 262 and 294containing the even segment time and blanking data are coupled to the analog circuitry via line 30.0.

The even Z bit is inverted by inverter 302 before it is loaded into register 294. The first set of-two'registers, 262 for the evensegment data is labeled A registers while thesecond set-294 is labeled-B registers. The 2- bit .output from the B registers is connected via an inverting gate (not shown) in the timing and controllogic 220-to the analog circuitry while theother seven bits of the B register are connected directly to the analog circuitry. The even segment data linesto the analog circuitry are changed at alternate intervals from the odd segment data lines. to the analog circuitry, however, both remain steady for two segmentperiods. At the end of the display for one symbol, the segment

time period lines

298 and 300 for the odd segment period and even segment periods respectively will remain at logical zero while the blanking lines 304 for odd blanking and 188 for even blanking will remain at logical one. This logical one condition of the blanking lines in the case of the odd segment data results from the reset word from segment memory 230 while in the case of the even segment data the contents of the even B registers 294 are either that of the last memory word to be used in the character format when the total number of segments in the character is odd or that of the reset order when the total number of segments is even.

The timing and control logic 220 of the digital module provides all the clock signals and control levels required to implement the operations previously prescribe'd.This logic is the source of all the timing pulses required by the digital module which together with theodd clock and the even clock input lines from the 9 analog circuitry determine the: order-and time duration of th'evarious operations required'ijn addition this logic unclamps and clampsthe analogfcircuits, controls unblankingand providesvarious-indications onthe data console. The timing-and control logic comprises conventional MSl logicmodules. Clamp signalsare applied to the analog circuitry-vialine-306lwith dot'blanking on .line 308'-.which:the odd andievenxclocksare-receivedon lines;3-10 and3l2 respectively. Varioussignals'from the central "computer are also -'received bythe timing and'control logic, such as enabling signals for data loading, and a central clock if desired-on line 314,316

and Y318. An. end of character signal is coupled on line 320 to the analogcircuit.

Referring how 01 16.6 the trianglegenerator is' shown generally at .400. The triangular waveform generator 400 and thegphase inverter 500 generate-two while transistor "428 Y is on and transistorv 428 switches off whiletransistor 430 ison in order that currentloadingfromthe positive andnegative current sources 404 and 406respectively to the 'comparator is kept-approximatelyconstant. The voltagefacross the capacitor 402 :is :amplifiedand'phase inverted to provide the two ,phases' required by the BIA multipliers as described with reference to -FIG. 4. The triangle waveform generatorsupplies both the X and Y D/A multipliers 120 through 1:26and the triangle waveform is phase invertedand referenceto V to minimize transients when V is changed by varying the character size with the voltage V addedto the supply voltage B-i-Q A-clamp circuit indicated: generally at 440 arrests'the action of the triangular waveform generator on completion of a character which holds the voltage across capacitor 402 at zero under the command of phases of triangular pulsesof constant peak amplitude but with changing lperiodicity. i In the triangular waveform generator, a capacitor "402 is charged from either a positive or negative constant current source 404 or 406:respectively. The choice of source depends upon whethera positive or negative slope is required. A differential circuit in a comparator 408alternately compares the voltage across capacitor 402 with zero volts andwith the peak positive value V QThis com- I parator 408 switches "the constanteurrent'

sources

404 and 406 such that when the voltage across capacitor 402 starts at zero the positive constant current source 1404 is operative and'the capacitor is charged until the comparator detectsthe value as being equal-to Y at which. point the positive. current source .is then switched off and the negative current source 406 is switched on.;Capacitor 402 is then discharged to zero .and the whole cycle recommences'z- 402 to vary between zero and V); and is set by the seven-bit digital to analog converters and

controlled'via lines

298 and 300 by the even segment period-and the odd segment period .data :from registers300 and-.298 respectively of theoutput registers of the digital circuitry. Since only one ,gonstant current source-is operative at a time, during the inoperative periods it is possible tochange the'inputto the seven-bit digital to'analog converters to the value ,requiredfor the next-segment. The alternate inputs zero and V supplied tothe comparator 408 are switched bya switching transistor4l2. The voltage across the charging capacitor .402 is large compared with either V or zer'o'a Thus, if compared with zero this voltage must be negative and if compared with V it must be positive. The transistor pairs 4 14 and 416-and 418 and 420 are differentially "connected to form the comparator while transistor 422 acts as the positive current source and transistor 424 as anegative current source. v t The peak positive voltage V f-is amplified by an emitter follower transistor 326 prior to comparison in comparator 409 Signal translation from the capacitor lQ tI'Ol signals from thetiming and control logic 220 I received at 442. Diodes 4,44 and 446 act asrestraining diodes for the clamp circuit, the output'of which is of course applied to the capacitor -402-.-

Transistors

448 and 450 form a differential amplifier, the output of which is coupled through emitter'follower452 to clamp the emitter voltageof transistor 2454. Five-volt outputs are providedat the collectors of

transistors

454 and 456 respectively, a supply voltage isprovided at 458, and a potentiometer (not shown) providea clamp level control at 460. Tr'ansistors462 and 4614; provide signal translation for the reference outputs to the positive Y- bit -D/A converter at 466, 468 and'f470 while reference output tothe negative seven-bit D/A converter are provided by aconnection totheemitter of transistors 424 81111432 and tapsacross a zenerdiode 472 at 474, 476 and ,478-respectively. Transistor-480 and zener diode .482 provide biasingifor the comparator 408. A negative 11.4 volts is supplied at 484. I, -Referring now to FIG. 7 the-phase inverter is shown generally at 500. The peak signal amplitude or dc size control .V,; which is a function of time is a unipolar signalinputted to the base of transistor .502 on line 504. A supply voltage which may effectively be 24 volts is applied through resistor 506 byan emitter follower circuit 508 through thecollector of transistor 502 while I the negative supply voltage is applied through resistor 5 l0tothe emitter of transistor 502 thereby producing abipolar output on

lines

512 and 514 with V f,(t)+V on line 512 and +V f(t)+V online 514 with V being the dcoffset-voltage. Capacitors 5-16 and 518 allow dc isolation to permit the triangular waveforms to be do restoredgto new reference leads, V and zero.

Diode emitter followers

528 and 530 respectively to provide an even segment triangle voltage outputon line 532 to the even D/A converters and an odd segment triangle voltageoutputon line 534 to the odd D/A converters.

Referringnow to-FIG. 8 aportion of a typical digital to analog multiplier of the present invention capable of accepting a-single bit of data is illustrated generally at 600. The digital to analog multipliers operate in pairs as described with reference to FIG. 4 and are fed from the two phaseoutputs, on

lines

532 and 534 from the phase ll inverter 500. The multiplying factor of theD/A multiplier is controlled by a digital input, and; is only changed when its analog input is at zero. In ,other words, the multipliers have the digital input changed at the beginning of alternate segment periods. Theout- I puts of each pair of multipliers are summed in a resistance ladder network 630 and amplified to drive a 7'5-ohm funbalanced line. FIG. 8 is illustrative of the .,by said ramp generation means by one of said r v digital-control signals of said storage means for linear transistor pair of

switches

618 and 620, which In the character generator described, X, Y, blanking,

and period data are all digitally stored; however, this data could of course first be received on a communication line before local storage.

While particular embodiments of the invention have been shown and described, various modifications thereof will be apparent to those skilled in the art and therefore it is not intended that the invention be limited to the disclosed embodiments or to details thereof and 3 departures may be made therefrom within the spirit and scope of the invention as defined in the appended claims.

What is claimed is: i l. A character generation system comprising:

7 means for generating a ramp function signal, said generation means providing a positive ramp function and a negative ramp function, said generation means being responsive to digital control signals of a storage means for controlling the temporal duration of each of said ramp signals such that each of said durations is predetermined in accordance with said digital control signals;

means for storing said digital control signals, said storage means being responsive to a computer supplied address for selecting a set of such digital con- .trol signals corresponding to a selected character which is to be generated;

first means for multiplying a ramp signal generated scaling said ramp signal; means for complementing a ramp said ramp generation means; v

Qsecond means, coupled to said complementing means, for multiplying said complemented ramp signal by a second, one of said digital control signals of said storage means for sealing said comme aiii s f o i' rii i riiri g aii cl scaled ramp signals of said first and said second multiplying means to provide the instantaneous value of a coordinate of a segment of said selected character; t a means coupled to said combining means andresponsive to said coordinate for displaying said character; and i I said ramp generation means signaling said storage means to update the values of respectiveones of said control signals to said first and said second multiplying means when each of said scaled ramp signals of respectively said first and said second multiplying means has a zero value, successive ones of said coordinates thereby being provided such that one coordinate is initiated immediately upon termination of a preceding coordinate. 2. The system according to :claim 1 wherein said signal provided by ramp generation means comprises a capacitor and a pair of current source means for charging and discharging said capacitor, each of said current source means providing for a continuously variable duration of said ramp signals in response to said control signals of said storage means.

3.- The system according to claim 2 wherein said ramp generation means comprises comparator means for comparing the magnitude of said ramp signal to a reference signal, said comparator means terminating such ramp signalwhen said value of said ramp signal equals the value of said reference signal, and means for varying said reference signal in response to one of said control signals of said storage means to provide a continuously variable maximum amplitude to said ramp signals.

4. The system according to claim 2 further comprising means for computing air traffic control data, said computing means processing said data to provide a format for said data wherein said data appears in two portions, one of said portions being suitable to be applied as a control signal to said first multiplying means and said second portion being suitable to be applied as said digital control signal to said second multiplying means, 5. The system according to claim 2 further comprising means responsive to said control signal of said reference and coupled to said combining means for off-

Claims

1. A character generation system comprising: means for generating a ramp function signal, said generation means providing a positive ramp function and a negative ramp function, said generation means being responsive to digital control signals of a storage means for controlling the temporal duration of each of said ramp signals such that each of said durations is predetermined in accordance with said digital control signals; means for storing said digital control signals, said storage means being responsive to a computer supplied address for selecting a set of such digital control signals corresponding to a selected character which is to be generated; first means for multiplying a ramp signal generated by said ramp generation means by one of said digital control signals of said storage means for scaling said ramp signal; means for complementing a ramp signal provided by said ramp generation means; second means, coupled to said complementing means, for multiplying said complemented ramp signal by a second one of said digital control signals of said storage means for scaling said complemented ramp signal; means for combining said scaled ramp signals of said first and said second multiplying means to provide the instantaneous value of a coordinate of a segment of said selected character; means coupled to said combining means and responsive to said coordinate for displaying said character; and said ramp generation means signaling said storage means to update the values of respective ones of said control signals to said first and said second multiplying means when each of said scaled ramp signals of respectively said first and said second multiplying means has a zero value, successive ones of said coordinates thereby being provided such that one coordinate is initiated immediately upon termination of a preceding coordinate.

2. The system according to claim 1 wherein said ramp generation means comprises a capacitor and a pair of current sourcE means for charging and discharging said capacitor, each of said current source means providing for a continuously variable duration of said ramp signals in response to said control signals of said storage means.

3. The system according to claim 2 wherein said ramp generation means comprises comparator means for comparing the magnitude of said ramp signal to a reference signal, said comparator means terminating such ramp signal when said value of said ramp signal equals the value of said reference signal, and means for varying said reference signal in response to one of said control signals of said storage means to provide a continuously variable maximum amplitude to said ramp signals.

4. The system according to claim 2 further comprising means for computing air traffic control data, said computing means processing said data to provide a format for said data wherein said data appears in two portions, one of said portions being suitable to be applied as a control signal to said first multiplying means and said second portion being suitable to be applied as said digital control signal to said second multiplying means.

5. The system according to claim 2 further comprising means responsive to said control signal of said reference and coupled to said combining means for offsetting the center of a displayed character.