US3699512A

US3699512A - Apparatus for allocating and timing a plurality of load intervals

Info

Publication number: US3699512A
Application number: US812480*A
Authority: US
Inventors: Frank W Hill; Peter G Bartlett; Larry K Clark
Original assignee: EW Bliss Co Inc
Current assignee: EAGLE SIGNAL CONTROLS CORP A CORP OF DE; EW Bliss Co Inc
Priority date: 1968-08-20
Filing date: 1968-08-20
Publication date: 1972-10-17
Anticipated expiration: 1989-10-17
Also published as: BR6911741D0

Abstract

Apparatus is disclosed herein for sequentially allocating and timing a plurality of intervals during which different loads are energized within each of a plurality of groups of such intervals. This apparatus includes a common timer circuit associated with all of the groups and having a first timing means for timing a first interval and then providing a first interval termination signal, and second timing means for timing a second interval and then providing a second interval termination signal. The apparatus also includes a common interval sequencer circuit associated with all of the groups and having first actuator means for actuating the second timing means and second actuator means for actuating the first timing means.

Description

United States Patent Hill et a1.

APPARATUS FOR ALLOCATING AND TIMING A PLURALITY OF LOAD INTERVALS CONTROL ea TIMER CONTROL 51 Oct. 17, 1972 Primary Examiner-William C. Cooper Attorney-Meyer, Tilberry and Body [57] ABSTRACT Apparatus is disclosed herein for sequentially allocating and timing a plurality of intervals during which different loads are energized within each of a plurality of groups of such intervals. This apparatus includes a common timer circuit associated with all of the groups and having a first timing means for timing a first interval and then providing a first interval termination signal, and second timing means for timing a second interval and then providing a second interval termination signal. The apparatus also includes a common interval sequencer circuit associated with all of the groups and having first actuator means for actuating the second timing means and second actuator means for actuating the first timing means.

20 Claims, 7 Drawing Figures GROUP 0R PHASE ON SELECT CIRCUIT PATENTED B 171972 3 699 .51 2

SHEET 1. BF 3 FIG. I

Ipa

i I L.C.-i 04 FULL -- ACTUATED LOCAL CONTROLLER LC-Z L (DB ON iv A ON A TIMER q) 7 2 SELECT cIRcuIT "W W; 46 is IoRgb OR INVENTORS.

FRANK w. HILL, LARRY K. CLARK a BY PETER e. BARTLETT I (III-:3 TIMER CONTROL Mew 7 3 3 ATTORNEYS PATENTED 17 I973 3.699.512

SHEET 2 BF 3 a 48 v A ON q) 54 g (M GREEN AG 5O No fi T 'WLOAD SWITCH g f GREEN +NOR 56 (DA YELLOW/LS'Z M y :jji NoR p 0+LOAD SWITCH YELLOw NOR 1 RED/LS4) AR HQ 5 NOR LOAD SWITCH 5s b 48 4- I N NOR 54 (pa GREEN B6 g jNORgl "TLOAO SWITCH GREEN HNOR 56 OR YELLOW BY I 1 y JHNOR9 LOAD SWITCH YELLOW Lv FIG 4 Mm) SWITCHI FROM TIME CONTROL TC-l, Tc-2 ETC. YELLOW JC LRJTI :1 H FIG. 5 TO 1s (44) j' 4| J E CONTTQBETE-T-ET l /TO IS (46) I w 1 HKNTZ i INVENTORS. I 3 FRANK W. HILL, 40 LARRY K. CLARK a l T 1 NOR PETER G. BARTLETT I J Mm, 711W, x M,

A'TTORN EYS APPARATUS FOR ALLOCATING AND TIMING A PLURALI'IY F LOAD INTERVALS This invention relates to the art of electrical controls and, more particularly, to electrical controls for sequentially allocating and timing a plurality of load intervals within each of a plurality of groups of load intervals. The term load interval" is used in the specification and claims to designate the interval during which a specific load is energized such as a red lamp, a yellow lamp, a green lamp, a turn-arrow lamp and so forth in traffic systems, for example.

The invention is particularly applicable to the art of traffic control and will be described with particular reference thereto; although, it is to be appreciated that the invention has broader applications, such as in process control or other control arts, wherein means are desired for sequentially allocating and timing a plurality of load intervals within each of a plurality of groups of load intervals.

In the past, past, load interval sequence controllers, such as traffic controllers, have frequently incorporated a different timing circuit for timing each load interval. An electromechanical step switch or an electronic ring counter has been used to sequentially energize each timing circuit in a series fashion. For a large number of intervals to be allocated and timed, the expense of a correspondingly large number of timing circuits may be considerable.

In morerecent years, some traffic control circuits, such as that disclosed in the US. Pat. to N. A. Bolton, No. 3,251,031 have utilized a single timer circuit with a different timing I resistor being placed in circuit therewith by a ring counter for each load interval to be allocated and timed. Thus, the ring counter will require one stage for each resistor to be thus placed in circuit with the timer circuit. As the number of load intervals increases in number so does the complexity of such a ring counter. Thus, for example, an eight phase traffic controller would require at least sixteen stages, two for each phase to provide both go and caution intervals, for selecting sixteen different resistors to be placed in circuit with the timer circuit.

In traffic control applications, as well as other load sequence control applications, the various intervals to be allocated and timed may be divided into groups, each having a plurality of intervals to be sequentially allocated and timed. In the eight phase traffic controller application discussed above there are eight groups of intervals involved; to wit, one group per phase. Within each group the sequence is the same, that is, the go interval is allocated and timed and then a caution interval is allocated and timed.

The present invention is directed toward a load sequence controller which sequentially allocates and times a plurality of load intervals within each of a plurality of groups of load intervals without requiring a ring counter, or the like, having one stage for each interval to be allocated and timed.

In accordance with the present invention, apparatus is provided for sequentially allocating and timing a plurality of load intervals within each of a plurality of groups of load intervals and comprises: a common timer circuit associated with all of the groups and hav ing first timing means for timing a first interval and then providing a first interval termination signal and second means for timing a second interval and then providing a second interval termination signal; and, a common interval sequencer circuit associated with all of the groups and having first means for starting the second timing means and a second means for starting the first timing means.

In accordance with a more limited aspect of the present invention, a timer control circuit is provided for each of the groups, with each circuit having first timing control means and second timing control means for respectively controlling the durations of the first interval and the second interval, and group selection means for selectively energizing one of the timer control circuits.

In accordance with another aspect of the present invention, there is provided a traffic controller for controlling signal light means for go and caution intervals of at least two traffic phases and comprising: a common timer circuit associated with all of the traffic phases and having go timing means for timing a go interval and then providing a go termination signal, and timing means for timing a caution interval and then providing a caution termination signal; and, a common traffic interval sequencer circuit for all of the traffic phases and having first means for starting the go timing means and second means for starting the caution timing means.

In accordance with a still more limited aspect of the present invention, the traffic controller further includes a timer control circuit for each traffic phase, each circuit having go timing control means and caution timing control means for respectively controlling the durations of the go and caution intervals.

In accordance with a still further aspect of the present invention, the traffic controller includes phase on selection means for selectively energizing one of the timer control circuits.

The primary object of the present invention is to provide an improved solid state load sequencer controller which is relatively inexpensive to manufacture and relatively economical to operate.

Another object of the present invention is to provide an improved solid state load sequencer circuit for sequentially allocating and timing a plurality of load intervals within a plurality of groups of load intervals.

A still further object of the present invention is to provide an improved traffic controller for controlling traffic signal lights.

A still further object of the present invention is to provide an improved load sequencer which does not require a ring counter, or the like, having one stage for each interval to be allocated and timed.

A still further object of the present invention is to provide an improved traffic controller having a common timer circuit and a common traffic interval sequencer for all of the traffic phases.

These and other objects and advantages of the invention will become apparent from the following description of the preferred embodiments. of the invention as read in connection with the accompanying drawings, in which:

FIG.,1 is a schematic illustration of the invention as applied to a traffic control system incorporating a two phase pretimed traffic controller;

FIG. 2 is a combined schematicblock diagram illustration of one preferred embodiment of the invention;

FIG. 3 is a schematic illustration of load control circuitry forming a part of the invention;

FIG. 4 is a schematic illustration of additional load control circuitry forming a part of the invention;

FIG. 5 is a schematic illustration of the timer circuits found within FIG. 2;

FIG. 6 is a schematic illustration of the invention as applied to a traffic control system incorporating a two phase full actuated traffic controller; and,

FIG. 7 is a combined schematic-block diagram illustration of another preferred embodiment of the invention.

Referring now to the drawings, wherein the showings are for purposes of illustrating the preferred embodiments of the invention, and not for the purposes of limiting same, FIGS. 1,2, 3, 4 and 5 illustrate one embodiment of the invention in the form of a pretimed, two phase traffic controller LC-l. This controller serves to control signal light means S for sequentially allocating and timing main street (phase A) go and caution intervals and cross street (phase B) go and caution intervals. The controller, as best shown in FIG. 2, generally comprises: a common timer circuit T for all of the traffic phases and which includes a go timer T1 and a caution timer T2; a common traffic interval sequencer circuit IS: a phase A timer control circuit TC-l; a phase B timer control circuit TC-2; and, an interval group or phase on select circuit PS.

TIMER CONTROL CIRCUIT Timer control circuits TC-l and TC-2 are substantially identical and, accordingly, like components are identified with like character references for simplifying the description of the invention. The description that follows is given with particular respect to timer control circuit TC-l. As shown in FIG. 2, timer control circuit TC-I includes an NPN transistor having its collector connected to a 8+ power supply source and its emitter connected to a go timing potentiometer 12 and a caution timing potentiometer 14. As shown, these two potentiometers have their resistance portions connected together in parallel between ground and the emitter of transistor 10. The wiper arm of potentiometer 12 is coupled through a diode l6, poled as shown, to timer circuit T1. Similarly, the wiper arm of potentiometer 14 is connected through a diode 18, poled as shown, to timer circuit T2. It will be noted that timer control circuits TC-l and TC-2 are connected together in parallel and in the event the controller serves to control more than two traffic phases the additional timer control circuits will also be connected in parallel with timer control circuits TC-l and TC-2. Briefly, whenever transistor 10 in timer control circuit TC-l is activated into conduction, essentially B+ potential is applied across the resistance portions of

potentiometers

12 and 14. The wiper arms on these two potentiometers are adjusted to provide voltages for application to timer circuits T1 and T2, which voltages respectively control the time duration that these two timers perform their timing functions.

COMMON TIMER CIRCUIT The common timer circuit T incorporates a go timer T1 and a caution timer T2, having their inputs respectively coupled to the commonly connected outputs of all go and

caution timing potentiometers

12 and 14 in the timer control circuits TC-l and TC-2, etc. In addition, another input to timer T1 and to timer T2 is obtained from an output terminal g of sequencer circuit IS. Another input to timer T1 is taken from an output y of sequencer circuit IS.

Reference is now made to FIG. 5 which schematically illustrates timer circuits T1 and T2. As shown there, timer circuits T1 and T2 are substantially identical and, accordingly, like components are identified with like reference numbers. The description which follows is specifically given with reference to timer circuit T1. As shown, timer circuit Tl includes an NPN transistor 20 having its base connected to output circuit v of sequencer IS and its emitter connected to ground. The collector to emitter circuit of transistor 20'is connected in parallel with a timing capacitor 22. The junction of the collector of transistor 20 and one side of capacitor 22 is connected through a timing resistor 24 to a B+ voltage supply source. Capacitor 22 is coupled to a comparator circuit in the form of a differential amplifier, including transistors 26'and 28, having their emitters connected together in common and thence through a resistor 30 to ground. The collectors of

transistors

26 and 28 are respectively connected through

resistors

32 and 34 to the B+ voltage source. The base of transistor 28 is connected to the commonly connected cathodes of diodes 16 in timer control circuits TC-] and TC-2. The collector of transistor 28 is connected to the input of a timer memory circuit TM. This timer memory circuit includes two NOR

gates

36 and 38 connected together to define a two input bistable multivibrator circuit. The input to the timer memory circuit from the collector of transistor 28 is taken to the input of NOR gate 36. A second input to the timer memory circuit TM is taken from output circuit g of sequencer circuit IS, through a capacitor 40, and thence to one input of NOR gate 38. The output gate 38 serves as the output of the timer memory circuit TM and is applied to one input of AND gate 41.

Timer circuit T2 differs from timercircuit Tl only inasmuch as the base of transistor 20 is connected to output circuit 3 of sequencer circuit IS and that the base of transistor 28 is connected tothe commonly connected cathodes of diodes 18in the timer control circuits TC-l and TC-2. Also, the output of NOR gate 38 in timer circuit T2 is connected to the second of two inputs of AND gate 41.

PHASE ON SELECT CIRCUIT The phase on select circuit PS, shown FIG. 2, takes the form of a bistable multivibrator circuit having a single trigger input and two output circuits a and b. Each received trigger pulse, of a negative going polarity, serves to trigger the bistable multivibrator circuit and shift it from one condition to the other, i.e., to provide a positive potential on either output circuit a or on output circuit b. Such multivibrator circuits are well known, one example being shown, for instance in US. Pat. application Ser. No. 640,654, filed May 23, I967, now Pat. No. 3,466,618. Such a multivibrator circuit may be considered a binary counter, since it serves to count trigger pulses and, in the form of a simple bistable multivibrator circuit, sequentially energizes output circuits 0, b, 0, etc., with successively received trigger pulses. In the embodiment illustrated, a binary counter capable of counting to two is required for selecting either timer control circuit TC-l or timer control circuit TC-2. In the event, however, a multiphase traffic controller is provided with, for example, eight phases, the phase on select circuit PS may take other forms, such as, for example, a binary counter capable of counting to eight.'Also, eight output circuits a, b, etc., would be required, each to be energized in accordance with its decimal number for energizing an associated timer control circuit. In the event a multistage binary counter is used, some interface equipment, such as a binary to decimal decoder circuit may be required in order to provide the correct number of output circuits.

As shown, however, in FIG. 2, the binary counter or phase on select circuit PS has the capability of counting to two to energize output circuit a or output circuit b in accordance with the number of pulses received at its input circuit. These pulses are received from the output of a NOR gate 42 which serves as a signal inverter and has its input connected to the output of AND gate 41. Each time AND gate 41 provides a binary 1 signal, representative that both timer T1 and timer T2'have completed their timing functions, the output of NOR gate 42 goes from a positive direct current level toward ground potential, and thereby provides a negative going signal to serve as a trigger pulse for triggering the phase on select circuit PS from one condition to the other. Output circuits a and b of phase on select circuit PS are respectively coupled to the base electrodes of transistors in timer control circuits TC-l and TC-2. Also, these two output circuits are connected to output terminals phase A ON and phase B ON.

INTERVAL SEQUENCER CIRCUIT The interval sequencer circuitIS serves to control the sequence of the intervals to be allocated and timed within a particular group, or in the case of traffic control, within a particular phase. Thus, in a two phase, pretimed traffic controller wherein each phase is allocated a go signal and then a caution signal, the sequencer serves to ensure that when, for example, the phase A operation commences, timer Tl completes its timing function before timer T2 commences its timing function The sequencer circuit IS may take various forms and, as shown in FIG. 2, it includes two NOR

gates

44 and 46 connected together to define a two input bistable multivibrator circuit. One input is taken from the output circuit of timer T1 and is applied to the input of NOR gate 44. The other input is taken from the output of timer circuit T2 and is applied to the input of NOR gate 46. The output of NOR gate 44 is connected to output circuit g. Similarly, the output of NOR gate 46 is connected to output circuit y.

SIGNAL LIGHT CONTROL CIRCUITS Signal light control circuits are shown in FIGS. 3 and 4 for energizing go, caution and stop signal lights associated with phases A and B. Thus, as shown in FIG. 3, a circuit is provided for energizing the phase A green light AG, or the phase A yellow light AY, or the phase A red light AR. The circuit includes NOR

gates

48, 50 and 52 having their inputs respectively coupled to the phase A on circuit (output circuit a) of phase on select circuit PS, output circuit g and output circuit y. NOR

gates

54 and 56 each have two inputs. The inputs of NOR gate 54 are coupled to the outputs of NOR

gates

48 and 50 and the inputs of NOR gate 56 are coupled to the outputs of NOR

gates

48 and 52. The outputsof,

NOR

gates

54 and 56 are coupled to the input of a NOR gate 58 as well as to load switches LS-l and LS-2. The output of NOR gate 58 is coupled to load switch LS-3. The outputs of NOR

gates

54, 56 and 58 serve to trigger load switches LS-l, LS-2 andLS-3. These load switches may, for example, take the form of triacs having their gates connected to the outputs of the associated NOR

gates

54, 56 and 58. As is well known, once a positive signal is applied to the gate of such a triac, the triac is gated into conduction for purposes of switching an alternating current voltage source across a load. Alternating current voltage source V is coupled to each of the load switches LS-l, LS-2 and LS-3 which, when gated into conduction by their respective NOR gates, serve to couple the voltage source across the selected signal light AG, AY or AR.

The circuit illustrated in FIG. 4 is substantially the same as that shown in FIG. 3 and accordingly like components are illustrated with like character references. The differences made, however, are that load switches LS-l, LS-Z and LS-3 are respectively coupled to phase B lights BG, BY and BR. Also, the input to NOR gate 48 is coupled to the phase'B ON terminal. To avoid confusion, the like components are identified with a primed character reference.

OPERATION OF FIRST EMBODIMENT In the operation of the controller it may be assumed that output circuit a of phase on select circuit PS FIG. 2) is energized to provide a phase on signal. This is a positive signal which serves to forward bias transistor 10 in timer control circuit TC-l into conduction. Thus,

potentiometers

12 and 14 apply control potentials to timer circuits T1 and T2 in the common timer circuit T. During the previous interval the output circuit y of sequencer circuit IS provided a positive potential to forward bias transistor 20 into conduction to short circuit timing capacitor 22. However, when timer circuit T2, during that previous interval completed its timing function the output circuit y, which is connected to the output of NOR gate 46, became a. binary 0" or ground potential, thereby removing this short circuit. Accordingly, timer circuit T1 commences to time by permitting capacitor 22 to charge toward the B+ potential. Since the base of transistor 28 (FIG. 5) is coupled to potentiometer 12 in timer control circuit TC-l, a potential as determined by the adjustment of the wiper arm of potentiometer 12 is applied between ground and base of transistor 28. When the voltage stored by capacitor 22 exceeds that applied between ground and the base of transistor 28, transistor 28 will be reverse biased and a positive, i.e., a binary l signal is applied to the input of NOR gate 36. Thus, the output of NOR gate 36 becomes a binary 0 signal causing the output of NOR gate 38 to become a binary 1 signal. This binary l signal is applied to one input of AND gate 41. Also, this binary 1" signal is applied to one input of NOR gate 44 in sequencer circuit IS. This de-energizes output circuit 3 and, in turn, causes the output of NOR gate 46 to carry a binary l" signal. Since the output of NOR gate 46 carries a binary l signal, output circuit v is energized to carry a positive signal. This forward biases transistor 20 in timer circuit T1 to maintain that timer reset by short circuiting capacitor 22. Since outsignal at the output of NOR gate 38 and this signal is applied to the second input of AND gate 41 as well as to the input of NOR gate 46 in the sequencer circuit IS. This causes the sequencer circuit [S to revert to its original condition wherein output terminal g is energized. Since a binary l signal is received on both inputs of AND gate 41, its output circuit now applies a binary l signal to the input of NOR gate 42. NOR gate 42 serves as an inverter and provides a negative trigger pulse to the single input of the phase on-select circuit PS, causing its output terminal a to become de-energized and its output terminal b to be energized and carry a phase on signal. So long as a phase on signal is carried by output circuit b of the phase on select circuit PS, the phase B operation will continue in the same fashion as explained above with reference to the phase A operation.

During the phase A operation described above, the phase A ON terminal is energized and, at different times, output circuit 3 and output circuit Y of the ,sequencer circuit'IS are energized, During the period that output circuits a and g are energized, the outputs of NOR

gates

48 and 50 of the circuit shown in FIG. 3

carry binary signals, whereupon the output circuit "energized. When sequencer output circuit y becomes ,energized during the period that the phase A ON terminal is energized, then the output circuit of NOR gate 56 carries a binary l signal for actuating load switch LS-2 into conduction to energize phase A yellow light AY. Whenever thephase A 0N terminal is not energized or for some reason it is energized but neither output circuits 3 nor y is energized, then the output circuits of NOR gates 54 and S6 carry binary 0 signals, causing the output circuit of NOR gate 58 to carry a binary l signal to actuate load switch LS-3 into conduction to energize the phase A redlight AR.

The operation which ensues during the phase B operation is the same as described above with reference to the phase A operation and no further description is deemed necessary for a complete understanding of the invention.

SECOND EMBODIMENT Reference is now made to FIG. 6 which shows a second embodiment of the invention as applied to a g 7 two phase, full actuated traffic controller LC2. This controller, like controller LC-l, serves to allocate and time go and caution signals to phase A and phase B.

' However, both phases A and B are traffic actuated vehicle is detected. Alternatively, the detectors may take the form of presence detectors which may be used in a counting operation for providing a pulse for each detected vehicle. It is also contemplated that the detectors may take the form of true presence detectors which provide a presence signal so long as a vehicle is present within a zone of influence. Such presence detectors may be either loop detectors or ultrasonic detectors, both of which are well known to those skilled in the art.

Reference is now made to FIG. 7 which is quite similar to that circuit shown in FIG. '2, and, ac-

cordingly, like components are identified with like tor circuit includes a detector memory circuit DMl for remembering a traffic detection in phase A and a detector memory circuit DM 2 for remembering a traffic detection in phase B. It is to be appreciated that such memory circuitry is shown on the premise that the detectors are spot detectors. If the detectors are presence detectors, then memory circuits DM1 and DM2 may be eliminated. As shown, however, each of the detector memory circuits DM1 and DM2 includes a pair of NOR

gates

60 and 62 connected together to define a two input bistable multivibrator circuit. One of the inputs to detector memory circuit DMl is taken from the phase A 0N terminal to one input of NOR gate 60. The other input is taken from the output of a NOR gate 64 to the input of NOR gate 62 in detector memory DMl. NOR gate 64 has its input coupled through a resistor 66 to v the B+ voltage potential. The junction of resistor 66 and NOR gate 64 is coupled to the normally open switch DA. Similarly, one input of NOR gate 60 in detector memory DM2 is connected to the phaseB ON terminal and one input of NOR gate 62 in detector memory DM2 is connected to the output of a NOR gate 68. .The input to NOR gate 68 is connected to the normally open switch DB as well as through a resistor 70 to a 8+ voltage supply source.

In addition to the foregoing circuitry, the additional circuitry added in FIG. 7 includes a detector logic circuit DL. This detector logic circuit includes a NOR gate 72 having its input coupled to the output of timer circuit T1 and its output coupled to one input each of NOR

gates

74 and 76, respectively. The output of'detector memory DMl is coupled to one input of NOR gate 74, and, similarly, the output of detector memory DM2 is connected to one input of NOR gate 76. The output circuits of NOR

gates

74 and 76 are connected together in common and thence to the input of NOR gate 44 in the sequencer circuit IS.

OPERATION OF SECOND EMBODIMENT In the description which follows only that operation which results from the addition of the detector circuits added in FIG. 7 is described, the remaining operational steps having been described hereinbefore with reference to FIG. 2. Briefly, in this embodiment if a green signal is being allocated to phase A and thetimer located to phase A and the controller will automatically be sequenced to allocate and time a green signal to phase B. p

It may be assumed that A has been allocated a green signal and that timer Tl hascompleted its timing function. Thus, the output circuit of timer Tl appliesa binary l signal to the input of NOR gate 72 which inverts the signal to apply a binary 0 signal to the inputs of NOR

gates

74 and 76. If no vehicle actuation has taken place in phaseB, then a binary 1 signal is applied to the input of NOR gate 68 through resistor 70. NOR gate 68, in turn, applies a binary 0 signal to one input of NOR gate 62 and its output circuitapplies a binary l signal to the input of NOR gate .76. Also, it will be noted that since phase B ON terminal is deenergized, a binary 0 signal is applied to the input of NOR gate 60 in detector memory DM2. Since a binary .1 signal from detector memory DMZ is applied to the input of NOR gate 76, the output of that circuit carries a binary 0 signal which will not cause sequencer circuit is to be actuatedfrom one condition to the other. If, however, a traffic detection occurred in phase B, then switch DB would have closed at least momentarily to apply a binary 0" signal to the input of NOR gate 68. This momentary pause would have caused the output of NOR gate 68 to apply a binary l signal pulse to the input of NOR gate 62. The output of NOR gate 62, in turn, would have provided a binary .0-" output which would have remained even though detector switch DB provided only a momentary closure. The binary 0 output from detector memory DM2 is applied to the input of NOR gate '76. Since timer T1 has timed out, the output of NOR gate 72 is also a binary 0 signal. Hence, NOR gate 76 applies a binary 1 signal to actuate the sequencer is to de-energize its output circuit 3 and energize its output circuit y.Thereafter, timer T2 will operate-in a manneras described hereinbefore to time the caution interval after which the controller would allocate and time ago interval tophase B. Theoperation which ensues for phase B is the same as described above with reference to phase A and, accordingly, no further description is deemed necessary for a complete understanding of the invention.

Although the invention described in connection with preferred embodiments, it will be readily apparent to those skilled in theart that various changes in form and arrangements of parts may be made to suit requirements without departing from the spirit and scope of the invention as definedby the appended claims.

What is claimed is:

1. Apparatus for sequentially allocatingand timing a plurality of intervals during which different loads are energized within each of a plurality of groupsof intervals, and comprising:

a common timer circuit for all of said groups of intervals having first timing means for timing a first interval and then providing a first intervaltermination signal and second timing means for timing a secondinterval and then providing a second interval termination signal; and t a common interval sequencer circuit for all of said groups of intervals and having first means for starting said second timing means in response to a said first termination signal and second means for starting said first timing means in response to a said second termination signal.

2. Apparatus as set forth in claim 1 and including:

a timer control circuit for each said group, each said circuit having first timing control means and second timing control means for respectively con trolling the durations of the said first interval and said second interval.

3. Apparatus as set forth in claim 2 including group selection means for selectively starting one of said timer control circuits.

4. Apparatus as set forth in claim 3 wherein said group selection means is a binary counter means having outputs 1 through N respectively coupled to 1 through N said timer control circuits of N .said groups, said binary counter means having an input for receiving trigger pulses whereby said outputs 1 through N are sequentially energized for respectively energizing said 1 through N timer control-circuits.

5. A traffic controller for controlling signal light means during go and caution intervals for a predetermined number of traffic phases and comprising:

a phase select circuit capable of being triggered by an input signal and sequentially producing a number of output signals corresponding to the predetermined number of traffic phases;

a common timer circuit for all of said phases and having go timing means for timing a go interval and then providing a go termination signal and caution timing means for timing acaution interval and then providing a caution termination signal; and

a common traffic interval sequencer circuit for all of said phases and having first means for starting said go timing means in response to any output signal from said phase select circuit and second means for starting said caution timing means in response to said go termination signal, said phase select circuit being triggered in response to said caution termination signal.

6. A traffic controller as set forth in-claim 5 and including:

a timer control circuit for each said phase, each said circuit having go timing control meansandcaution timing control means for respectively controlling thedurations of said gointerval and said caution interval.

7. A traffic controller as set forth in claim 6 wherein eachsaid go timing control means and saidcaution timing control means are adjustable for adjustingthe-durations of said go intervals and said caution intervals.

8. A traffic controller for controlling signal light means duringlgo and caution intervalsfor at least two traffic phases and comprising:

a common timer circuit associated with .all of :said phases andhavinggo timing means fortiming a go interval andthen providing a go termination signal and caution'timing meansfor timing a caution in- .terval and then providing a cautionterminal signal;

and

a common traffic interval sequencer circuit for all of said phases having first means for starting said go timing means, and

a timer control circuit for each said phase, each said circuit having go timing control means and caution timing control means for respectively controlling the durations of said go interval and said caution interval,

each said go timing control means and said caution timing control means being adjustable for adjusting the durations of said go interval and said caution interval, said adjustable go timing control means andsaid adjustable caution timing control means being each a potentiometer having a resistance portion and a movable wiper arm, a movable contact with said resistance portion, said resistance portions being connected together in parallel, and each said timer control circuit further including switching means for applying a fixed voltage across each of said resistance portions in that said timer control circuit, whereby the wiper arms associated therewith carry voltages of values determined by the positions of said wiper arms on said resistance portions.

9. A traffic controller as set forth in claim 8 wherein said go timing means and said caution timing means are .respectively coupled to all the said potentiometer wiper arms associated with go timing control means and to all the said potentiometer wiper arms associated with said caution timing control means.

10. A traffic controller for controlling signal light means during go and caution intervals for at least two.

traffic phases and comprising:

a common timer circuit for all of said phases and having go timing means for timing a go interval and then providing a go termination signal and caution timing means for timing a caution interval and then providing a caution termination signal; a common traffic interval sequencer circuit for all of said phases and having first means for starting said go timing means in response to said caution termination signaland second means for starting said caution timing means in response to said go termination signal; a timer control circuit for each of trigger'pulses and at least two output circuits, one for each said phase, which are sequentially energized to respectively carry a phase on signal in'accordance with the number of trigger pulses counted.

V 12. A traffic controller as set forth in claim 11 including trigger pulse means for applying a said trigger pulse to said input each time said common timer circuit wherein said triggerpulse means includes an AND circuit inter osed between the input of said binary counter cans and the said go and cautiontlmmg means in said common timer circuit. 1

14. A traffic controller as set forth in claim 11- wherein said first and second actuating means in said common interval sequencer circuit respectively have an output circuit for carrying a go signal for starting said go timing means and an-output circuit for carrying a caution signal for starting said caution timing means.

15. A traffic controller as set forth in claim 14 including signal light control means for controlling energization of go, caution and stop signal lights associated with each said phase, said signal light control means including logic circuit means coupled to said output circuits of said binary counter means and said output circuits of said first and second startingmeans in said common interval sequencer circuit for controlling energization of the go and caution signal lights associated with one phase and the stop signal lights associated with the other phases in dependence upon which binary counter output circuit is energized to carry a said phase on signal and which of the sequencer output circuits is energized to carry either a said go signal or a said caution signal.

16. A traffic controller as set forth in claim 11 wherein each said timer control means includes switching means coupled to a different one of the output circuits of said binary counter means so as to be energized by a said phase on signal.

17. A traffic controller as set forth in claim 10 wherein said phase on selection means has a plurality of output circuits, one for each said phase, respectively coupled to an associated one of said timer control circuits, each of said output circuits adapted to carry a phase on signal for energizing its associated one of said timer control circuits.

18. A traffic controller as set forth in claim 17 including traffic detector circuit means coupled to one of the output circuits of said phase selection means and adapted to be coupled to detector means for detecting traffic in a phase associated with said one output circuit for providing a phase calling signal when traffic is detected bysaid detector means during a period that a phase on signal is not carried by said one output circuit of said phase selection means.

19. A traffic controller as set forth in claim 18 including detector logic means associated with at least another of said phases for providing a sequencer actuation signal only when both a said phase calling signal and a said go termination signal are concurrently present. I

20. A traffic controller asset forth in 'claim 19 wherein said sequencer circuit second means is coupled to and controlled by said detector logic means for starting said cautiontiming means in response to a said sequencer signal.

' a 12 s a a

Claims

1. Apparatus for sequentially allocating and timing a plurality of intervals during which different loads are energized within each of a plurality of groups of intervals, and comprising: a common timer circuit for all of said groups of intervals having first timing means for timing a first interval and then providing a first interval termination signal and second timing means for timing a second interval and then providing a second interval termination signal; and a common interval sequencer circuit for all of said groups of intervals and having first means for starting said second timing means in response to a said first termination signal and second means for starting said first timing means in response to a said second termination signal.

2. Apparatus as set forth in claim 1 and including: a timer control circuit for each said group, each said circuit having first timing control means and second timing control means for respectively controlling the durations of said first interval and said second interval.

4. Apparatus as set forth in claim 3 wherein said group selection means is a binary counter means having outputs 1 through N respectively coupled to 1 through N said timer control circuits of N said groups, said binary counter means having an input for receiving trigger pulses whereby said outputs 1 through N are sequentially energized for respectively energizing said 1 through N timer control circuits.

5. A traffic controller for controlling signal light means during go and caution intervals for a predetermined number of traffic phases and comprising: a phase select circuit capable of being triggered by an input signal and sequentially producing a number of output signals corresponding to the predetermined number of traffic phases; a common timer circuit for all of said phases and having go timing means for timing a go interval and then providing a go termination signal and caution timing means for timing a caution interval and then providing a caution termination signal; and a common traffic interval sequencer circuit for all of said phases and having first means for starting said go timing means in response to any output signal from said phase select circuit and second means for starting said caution timing means in response to said go termination signal, said phase select circuit being triggered in response to said caution termination signal.

6. A traffic controller as set forth in claim 5 and including: a timer control circuit for each said phase, each said circuit having go timing control means and caution timing control means for respectively controlling the durations of said go interval and said caution interval.

7. A traffic controller as set forth in claim 6 wherein each said go timing control means and said caution timing control means are adjustable for adjusting the durations of said go intervals and said caution intervals.

8. A traffic controller for controlling signal light means during go and caution intervals for at least two traffic phases and comprising: a common timer circuit associated with all of said phases and having go timing means for timing a go interval and then providing a go termination signal and caution timing means for timing a caution interval and then providing a caution terminal signal; and a common traffic interval sequencer circuit for all of said phases having first means for starting said go timing means, and a timer control circuit for each said phase, each said circuit having go timing control means and caution timing control means for respectively controlling the durations of said go interval and said caution interval, each said go timing control means and said caution timing control means being adjustable for adjusting the durations of said go interval and said caution interval, said adjustable go timinG control means and said adjustable caution timing control means being each a potentiometer having a resistance portion and a movable wiper arm, a movable contact with said resistance portion, said resistance portions being connected together in parallel, and each said timer control circuit further including switching means for applying a fixed voltage across each of said resistance portions in that said timer control circuit, whereby the wiper arms associated therewith carry voltages of values determined by the positions of said wiper arms on said resistance portions.

9. A traffic controller as set forth in claim 8 wherein said go timing means and said caution timing means are respectively coupled to all the said potentiometer wiper arms associated with go timing control means and to all the said potentiometer wiper arms associated with said caution timing control means.

10. A traffic controller for controlling signal light means during go and caution intervals for at least two traffic phases and comprising: a common timer circuit for all of said phases and having go timing means for timing a go interval and then providing a go termination signal and caution timing means for timing a caution interval and then providing a caution termination signal; a common traffic interval sequencer circuit for all of said phases and having first means for starting said go timing means in response to said caution termination signal and second means for starting said caution timing means in response to said go termination signal; a timer control circuit for each of said phases, each said circuit having go timing control means and caution timing control means for respectively controlling the durations of said go interval and said caution interval; and phase-on selection means for selectively energizing one of said timer control circuits.

11. A traffic controller as set forth in claim 10 wherein said phase on selection means is a binary counter means having at least one input for receiving trigger pulses and at least two output circuits, one for each said phase, which are sequentially energized to respectively carry a phase on signal in accordance with the number of trigger pulses counted.

12. A traffic controller as set forth in claim 11 including trigger pulse means for applying a said trigger pulse to said input each time said common timer circuit has successively provided both a said go termination signal and a said caution termination signal.

13. A traffic controller as set forth in claim 12 wherein said trigger pulse means includes an AND circuit interposed between the input of said binary counter means and the said go and caution timing means in said common timer circuit.

14. A traffic controller as set forth in claim 11 wherein said first and second actuating means in said common interval sequencer circuit respectively have an output circuit for carrying a go signal for starting said go timing means and an output circuit for carrying a caution signal for starting said caution timing means.

15. A traffic controller as set forth in claim 14 including signal light control means for controlling energization of go, caution and stop signal lights associated with each said phase, said signal light control means including logic circuit means coupled to said output circuits of said binary counter means and said output circuits of said first and second starting means in said common interval sequencer circuit for controlling energization of the go and caution signal lights associated with one phase and the stop signal lights associated with the other phases in dependence upon which binary counter output circuit is energized to carry a said phase on signal and which of the sequencer output circuits is energized to carry either a said go signal or a said caution signal.

18. A traffic controller as set forth in claim 17 including traffic detector circuit means coupled to one of the output circuits of said phase selection means and adapted to be coupled to detector means for detecting traffic in a phase associated with said one output circuit for providing a phase calling signal when traffic is detected by said detector means during a period that a phase on signal is not carried by said one output circuit of said phase selection means.

19. A traffic controller as set forth in claim 18 including detector logic means associated with at least another of said phases for providing a sequencer actuation signal only when both a said phase calling signal and a said go termination signal are concurrently present.

20. A traffic controller as set forth in claim 19 wherein said sequencer circuit second means is coupled to and controlled by said detector logic means for starting said caution timing means in response to a said sequencer signal.