US3698011A - Polarity phasing of strap line for higher bit packing density of plated wire - Google Patents

Polarity phasing of strap line for higher bit packing density of plated wire Download PDF

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Publication number
US3698011A
US3698011A US132947A US3698011DA US3698011A US 3698011 A US3698011 A US 3698011A US 132947 A US132947 A US 132947A US 3698011D A US3698011D A US 3698011DA US 3698011 A US3698011 A US 3698011A
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US
United States
Prior art keywords
strap
current
strap lines
straps
lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US132947A
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English (en)
Inventor
Anthony M Apicella Jr
John T Franks Jr
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Lockheed Martin Tactical Systems Inc
Original Assignee
Goodyear Aerospace Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Publication of US3698011A publication Critical patent/US3698011A/en
Assigned to LORAL CORPORATION reassignment LORAL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: GOODYEAR AEROSPACE CORPORATION
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18—Bit line organisation; Bit line lay-out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • ABSTRACT A system for connecting the strap drivers to their respective straps of a plated wire memory array which substantially reduces the effects of the fields induced by current flow through the straps on adjacent memory elements. Adjacent pairs of strap lines are connected to their respective drivers at their opposite ends. Within each pair the strap lines are connected at the same end to their respective drivers.
  • the present invention relates to plated wire memory arrays and more particularly to a novel arrangement for driving the strap lines of such arrays which substantially reduces the disturbing effects which result when several strap lines are driven at the same time.
  • a further object of the invention is the provision of a strap line drive arrangement of a plated wire memory array which permits a more compact array without disturbance of adjacent memory. regions.
  • FIG. 2 is a view similar to that of FIG. 1 but showing the strap lines connected in accordance with the principles of the present invention.
  • the reference numeral 10 of FIG. 1 designates a conventional'plated wire memory array.
  • the array 10 includes a block or slab 12 of a dielectric material which is provided with a series of parallel bores 14 each of which receives one thin plated wire 16.
  • Current straps 18a-18 are provided in the outer surface of the block 12 with the straps being parallel to one another and extending at right angles to the plated wires 16. Each point of crossing of the wires 16 and current straps 18 comprises a bit in the memory.
  • the coating of the wire 16 is a magnetizable material and information is stored at each bit on the wire with the information being represented by the orientation of the magnetic field of the coating at that region of the wire.
  • the magnetic orientation of selected regions of the wire can be aligned to record data. Also, by the passage of the current through selected ones of the straps 18a-18h and the detecting of the resultant current in selected ones of the wires 16 data can be read from the memory array.
  • Each of the straps l8a-h is provided with a strap driver 20a-20h, respectively.
  • the memory array 10 When the memory array 10 is used in an associative processor or associative memory device where parallel read and write operations are performed, it is possible for several of the straps l8q-l8h to be energized at the same time. Since all of the straps 18a-18h are connected to their respective drivers at the same ends, the current flow through all of the straps is in parallel and in the same direction. As a result, the field which is set up around each of the energized straps during current flow is also in the same direction. If one strap, for example the strap 18d is not energized while the adjacent straps are energized, the fringes of the fields induced around the adjacent straps 18c and 18:: will overlap in the region of the unenergized strap 18d.
  • the resulting field in the region of the nonenergized strap 18d may be of sufficient strength to effect the magnetic orientation of the bits on the plated wires 16 in alignment with the strap 18d.
  • This resultant field may be of sufficient strength to alter the magnetic orientation of these bits, destroying or damaging the information previously stored there.
  • the present invention provides a novel arrangement for driving the straps and this arrangement is shown in FIG. 2.
  • the memory array 22 may be of the same general construction of that of FIG. 1, consisting of a dielectric block 24 provided with parallel bores 26 each receiving one plated wire 28, and straps 30a-30h arranged in parallel fashion to one another and at right angles to the wires 28. Each strap has an input 32a-32h, and an output 34a-34, respectively.
  • Drivers 36a-36h in a novel manner. The first two drivers 36a and 36b are connected to the inputs of their respective straps 30a and 30b. The next two drivers 36c and 36d are connected to the outputs of their respective straps 30c and 30d.
  • the remaining drivers are connected to their associated straps.
  • the drivers are connected so that alternate pairs of straps are driven in the opposite direction.
  • Current flow within each strap of the pairs of straps is in the same direction, thus current flow in the straps 30a and 30b is in the direction of the arrows 38a and 38b.
  • the adjacent pairs of straps are connected so that current flow is in the opposite direction.
  • current flow in the straps 30c and 30d is opposite to that in the straps 30a and 30b as well as opposite to that of the straps 30e and 30]".
  • any one of the straps for example, the strap 30d is not driven while the adjacent straps 30c 30c are driven, the current flow in the two adjacent straps will be in opposite directions.
  • the fields induced are thus also in opposite directions.
  • the overlapping fields in the region of the inactive strap 30d are therefore in opposition to one another and cancel one another in this region.
  • the data encoded on the plated wire 28 in the region of the strap 30d is thus unafiected by the fields surrounding the current straps 30c and 30e.
  • a 50 percent reduction of the disturbing field has been achieved'with the novel driving arrangement of the present invention.
  • the present invention permits the closer spacing of the current strap lines since it is not necessary to provide large separations between adjacent strap lines to prevent the disturbing of data in adjacent regions.
  • This closer possible spacing of the current strap lines results in a more compact memory array.
  • this higher packing density of the bits on the plated wire achieves a larger signal/noise ratio since a shorter sense line is now used. The signal propagation time is also decreased.
  • each current strap line the drive means being connected to their respective current strap lines in such manner that the first two current strap lines are driven in a first direction, the next two current strap lines are driven in the opposite direction and successive pairs of current strap lines are driven in alternate directions.

Landscapes

  • Insulated Conductors (AREA)
  • Dot-Matrix Printers And Others (AREA)
  • Printers Or Recording Devices Using Electromagnetic And Radiation Means (AREA)
  • Semiconductor Memories (AREA)
US132947A 1971-04-12 1971-04-12 Polarity phasing of strap line for higher bit packing density of plated wire Expired - Lifetime US3698011A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13294771A 1971-04-12 1971-04-12

Publications (1)

Publication Number Publication Date
US3698011A true US3698011A (en) 1972-10-10

Family

ID=22456304

Family Applications (1)

Application Number Title Priority Date Filing Date
US132947A Expired - Lifetime US3698011A (en) 1971-04-12 1971-04-12 Polarity phasing of strap line for higher bit packing density of plated wire

Country Status (8)

Country Link
US (1) US3698011A (enrdf_load_stackoverflow)
BE (1) BE781905A (enrdf_load_stackoverflow)
CA (1) CA939060A (enrdf_load_stackoverflow)
CH (1) CH564242A5 (enrdf_load_stackoverflow)
DE (1) DE2217890A1 (enrdf_load_stackoverflow)
FR (1) FR2132801A1 (enrdf_load_stackoverflow)
GB (1) GB1370718A (enrdf_load_stackoverflow)
IT (1) IT952353B (enrdf_load_stackoverflow)

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Proceedings Fall Joint Computer Conference, 1966 pg. 293 304. *

Also Published As

Publication number Publication date
GB1370718A (en) 1974-10-16
FR2132801A1 (enrdf_load_stackoverflow) 1972-11-24
DE2217890A1 (de) 1972-10-19
IT952353B (it) 1973-07-20
CA939060A (en) 1973-12-25
CH564242A5 (enrdf_load_stackoverflow) 1975-07-15
BE781905A (fr) 1972-07-31

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AS Assignment

Owner name: LORAL CORPORATION,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:GOODYEAR AEROSPACE CORPORATION;REEL/FRAME:004869/0167

Effective date: 19871218

Owner name: LORAL CORPORATION, 600 THIRD AVENUE, NEW YORK, NEW

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GOODYEAR AEROSPACE CORPORATION;REEL/FRAME:004869/0167

Effective date: 19871218