US3674997A - Right shifting system with data stored in polish stack form - Google Patents

Right shifting system with data stored in polish stack form Download PDF

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Publication number
US3674997A
US3674997A US11385A US3674997DA US3674997A US 3674997 A US3674997 A US 3674997A US 11385 A US11385 A US 11385A US 3674997D A US3674997D A US 3674997DA US 3674997 A US3674997 A US 3674997A
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time
space
register
registers
contents
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US11385A
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Goro Hamano
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/017—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising using recirculating storage elements

Definitions

  • the system has a first shift register means, a second shift register means which receives output signals from the first shift register means, an input gate means which feeds input signals from both shift register means and for which two signal paths are provided, the first path receiving output signals from the first shift register means and the second path receiving output signals from the second shift register means, and a control circuit means which is coupled to the input gate means and which controls input signals to the input gate means from the two signal paths selectively so that the right shifting operation of the contents of at least two time-space registers of the plurality of time-space registers is completed.
  • NSTI'RUOF GEN NSTI'RUOF GEN.
  • a conventional electronic desk calculator into which numbers are set by the use of-a IO-key figure keyboard has a plurality of time-space registers, the contents of which are stored in a circulating register comprising adelay line and shift registers, in series of bits, in time division series of time-space registers, and in series of digits.
  • a multiplication operation initiated by an instruction from a function keyboard the contents of the two time-space registers which hold the multiplier and the sum of the partial product are required to be shifted to the right.
  • any register is shifted to the right by forcing the output signal of the delay line to bypass the shift registers having a capacity of R X B bits, where R is the number of the time-space registers, the contents of which are stored in the circulating register, and B is the number of bits forming a digit. Therefore, the circulating register has a delay line and a long shift register, the length of which depends upon the number of the time-space registers and the number of bits forming a digit. Such a circulating register and recirculating control circuits become complicated and expensive.
  • This invention seeks to provide a circulating register having shift registers with a shorter length than that of the shift registers in the conventional circulating register for the given number of time-space registers and seeks to provide a new right shifting method for the registers.
  • FIG. 1 is a flow chartof the multiplication operation of a conventional electronic desk calculator
  • FIG. 2 is a block diagram of conventional right shifting means for an electronic desk calculator having four timespace registers, each of which has a 10 digit capacity;
  • FIG. 3 is a fiow chart of the multiplication operation of an electronic desk calculator in accordance with the invention.
  • FIG. 4 is a block diagram of right shifting means for an electronic desk calculator having four registers, each of which has a 10 digit capacity, in accordance with the invention
  • FIG. 5 is a diagram showing the clock pulses in the electronic desk shown in FIGS. 2 and 4;
  • FIGS. (SA-6C are diagrams showing the data in the timespace registers for explanation of the operations of the right shifting means of the electronic desk calculator shown in FIG. 4, in accordance with the invention.
  • time-space registers each of which has a 10 digit capacity and holds numbers in binary coded decimal (BCD) code.
  • BCD binary coded decimal
  • the first time-space register holds the multiplier
  • the second time-space register holds the multiplicand
  • the third time-space register holds the product
  • the fourth time-space register is used as a memory timespace register which does not concern the multiplication operation.
  • space register i.e., 8-10, are zero in an action
  • the multiplicand is stored in the second timespace register and the multiplier is in the third time-space register before the arithmetic operation.
  • the contents of the first, the second, the third, and the fourth time-space registers are represented by A, B, C and D, respectively.
  • the contents of the first and second digits of each time-space register are represented by A-l, B-l, C--l, D--l, A-2, 8-2, C-2 and D-2.
  • the rest of the contents of each register are represented in the same way as above.
  • each bit position corresponding to code 1, code 2", code 4 and code 8 of each time-space register are represented by R,, R R and R
  • the arrangement of the contents of the four time-space registers is in the order ofA,-l, A,l, A,-l, A,-l, ll-l, 2 r 4 r l r 1 r l r d a 8 r 1 r D2 1, D l, D,l, A,2, A,-2, A --2, A,2 and so on.
  • FIG. 1 is a flow chart illustrating various action steps. Each of said various action steps is dependent upon states of the control circuit (not shown) and is governed by the program control circuit (not shown).
  • the calculator is a fixed decimal point position type. The decimal point position of the calculator is predetermined and the decimal'point position of the product has to be equal to the predetermined decimal point position after the multiplication operation.
  • the contents of a counter K are used to control the decimal point position of the product. Therefore, the counter K holds the number showing the digit capacity below the decimal point position before the multiplication operation. For, example, the counter K is cleared to zero before the multiplication operation when the decimal point position of the calculator is predetermined to be zero.
  • the program control circuit and/or the control circuit test whether the contents of the IO-th digit of the second timestep (a). When 8-10 is zero, the program control circuit selects the actions steps (b) and (c) in order.
  • a counter K counts up by one.
  • the contents of the second timespace register are shifted to the left by one digit.
  • the program control circuit again selects the action step (a) and then the same operation as above is repeated.
  • the program control circuit selects an action step (d) as a next step.
  • a multiplier in the third time-space register is transferred to the first time-space register and the third register is cleared.
  • an action step (e) a test is made as to whether the contents of the least significant digit of the first register are zero. If they are not zero, the program control circuit selects an action step (0 as a next step, in which the contents of the least significant digit of the first register are reduced by one.
  • a next action step (g) the contents of the second time-space register are added to the contents of the third time-space register. After the action step (g), the program control circuit again selects the action step (e).
  • the contents of the second time-space register are added repeatedly to the contents of the third time-space register for a number of times equal to the number of the least significant digit of the multiplier by repeating the action steps and (g)- If the contents of the least significant digit of the first timespace register are zero in the action step (e), the program control circuit selects action steps (h), (i), (j) and (k) in order, and then again selects the action step (e).
  • step (h) the contents of the first time-space register are shifted to the right by one digit.
  • a test is made to determine whether the contents of the counter K are zero. If they are zero, the program control circuit selects the end step of the arithmetic operation. If they are not zero, the counter K counts down by one in the action step (i) and the contents of the third timespace register are shifted to the right by one digit in the action step (k).
  • the multiplication operation is carried out while the program control circuit is repeating the above actions.
  • the contents of the first register and the third time-space register are shifted to the right in the action steps (h) and (k), respectively.
  • an output signal of a l44-bit serial shift register 1 is fed to a four-bit shift register 3.
  • the l44-bit serial shift register 1 can usually be replaced by a magnetostrictive delay line.
  • An output signal of the four-bit shift register 3 is fed to four-bit shift registers 4, 5 and 6 which are connected to each other in tandem.
  • An output signal from the four-bit shift register 6 is fed to an input terminal of the 144-bit shift register 1 through an INHIBIT gate 7 and an OR gate 8 so that the five shift registers l, 3, 4, 5 and 6 constitute a 160-bit circulating register.
  • CL is the master clock pulse which is supplied to the shift registers l, 3, 4, 5 and 6, and if necessary, to other circuits.
  • T T T and T represent clock pulses specifying the time of the output signals from the l44-bit shift register I and correspond to code I", code 2", code 4" and code 8" of the BCD codes, respectively.
  • T,,, T,,, T and T are clock pulses specifying the time of the output signals of the l44-bit shift register I and correspond to the contents of the first time-space register, the second timespace register, the third time-space register and the fourth time-space register, respectively.
  • T-l, T-2, T-l are clock pulses specifying the time of the output signals of the l44-bit shift register 1 and correspond to the first digit, the second digit, and so on, up to the 10th digit from the least significant digit.
  • the 160-bit circulating register has stored therein the contents of the first time-space register, the second time-space register, the third time-space register and the fourth time-space register which are arranged in series of bits, in time division series of time-space registers and in series of digits.
  • an instruction pulse generator 13 generates an instruction pulse having a pulse width equal to the time necessary for the 160- bit circulating register to perform one cycle. Consequently, the contents of the first time-spa g'egister are shifted to the right by one digit.
  • T-l and T INHIBIT gate 7 is closed and the AND gate 9 is open since the ORgate 10 becomes logically l due to the output from ANllg te 11, to which the instructive pulse and the clock pulses T-l and T, are fed.
  • the contents of the third time-space register are trolled by an output signal of an AND gate 12 at the time T-1 and T and are shifted to the right by one digit when an instruction pulse generator 14 generates an instruction pulse.
  • the right shifting operation requires that the number of four-bit shift registers 3, 4, and 6 be equal to the number of time-sapce registers in the circulating register.
  • the contents of the third time-space register are required to be transferred to the first time-space register in the action step (d) during the multiplication operation in accordance with the flow chart shown in FIG. 1, and therefore, a gate means and a control circuit are necessary for such requirement.
  • FIG. 3 A flow chart according to the present invention is shown in FIG. 3 and describes the same general operation as the flow chart shown in FIG. 1.
  • the flow chart of FIG. 3 differs from that of FIG. 1 in that the action steps (d), (h) and (k) of FIG. 1 are eliminated, and action steps (I) and (m) are added, while the other steps are the same as FIG. 1.
  • Each of the various action steps in FIG. 3 is dependent upon the state of a control circuit (not shown) and is governed by a program control circuit (not shown).
  • the following description will be of, for convenience, an electronic calculator having four time-space registers, each of which has a 10 digit capacity and holds numbers in BCD code.
  • the contents of these four time-space registers are stored in a circulating time-space register in series of bits, in time division series of registers, and in series of digits, that is, in Polish stack form.
  • the calculator is of fixed decimal point position type and the decimal point position of the calculator is predetermined.
  • the-first time-space register holds the multiplier
  • the second time-space register holds the multiplicand
  • the third time-space register holds the product
  • the fourth time-space register is used as a memory register which does not concern the multiplication operation.
  • the multiplicand is stored in the second timespace register and the multiplier is in the third time-space register before the arithmetic operation.
  • the contents of the first, the second, the third and the fourth register are represented by A, B, C and D, respectively.
  • the contents of the first and the second digits of each time-space register are represented by A--l, B-l, C-1, D-l, A-2, B-2, C-2 and D-2.
  • the rest of the contents of each time-space register are represented in the same way as above.
  • control circuit and/or the program control circuit test whether the contents of the 10th digit of the second time-space register, i.e., 8-10, are zero in an action step (a). When 8-10 is zero, the program control circuit selects actions steps (b) and (c) in order.
  • a counter K counts up by one.
  • the contents of the counter K are used to control the decimal point position of the product.
  • the action step (c) the contents of the second time-space register are shifted to the left by one digit.
  • the program control circuit again selects the action step (a) and the same operation as above is repeated.
  • the program control circuit selects an action step (I) as a next step. (I)
  • the contents of the third register are transferred to the first register and at the same time, the original contents of the first time-space register are transferred to the third time-space register while shifting to the right by one digit. Therefore, at the beginning of the multiplication, the contents of the third time-space register are transferred to the first time-space register and the third time-space register is cleared in the first action step (1) following the action step (a), as the first time-space register is cleared before the multiplication operation.
  • an action step (e) a test is made to determine whether the contents of the least significant digit of the first time-space register is zero. If they are not zero, the program control circuit selects an action step (f) as a next step, in which the contents of the least significant digit of the first time-space register are reduced by one.
  • an action step (g) the contents of the second time-space register are added to the contents of the third register. After the action step (g), the program control circuit again selects the action step (e).
  • the contents of the second time-space register are added repeatedly to the contents of the third time-space register for a number of times equal to the number of the least significant digit of the multiplier by looping the action steps n (g)- If the (l). of the least significant digit of the first time-space register is zero in the action step (e), the program control circuit selects actions steps (i), (j) and (m) in order and again selects the action step (I).
  • a test is made to determine whether the'contents of the counter K are zero. If they are zero, the program control circuit selects the end step of the arithmetic operation. If they are not zero, the counter K counts down by one in the action step (j).
  • the contents of the third time-space register are transferred to the first time-space register and at the same time, the original contents of the first time space register are transferred to the third time-space register while shifting to the right by one digit.
  • the multiplication operation is carried out while the program control circuit is repeating the above actions.
  • an output signal of a 152-bit shift register is fed to four-bit shift registers 3 and 4 which are connected to each other in tandem.
  • An output signal of the four-bit shift register 4 is fed to an input terminal of the 152-bit shift register 15 through an INHIBIT gate 7 and an OR gate 8.
  • a 160-bit circulating register is constituted by the shift registers 3, 4 and 15.
  • an instruction pulse generator 18 In the action step (I) or (m) shown in FIG. 3, an instruction pulse generator 18 generates an instruction pulse having a pulse width equal to the time necessary for the 160-bit circulating register to perform one cycle.
  • the instruction pulse causes the contents of the third time-space register to transfer to the first time-space register through an AND gate 9 at the time of Te.
  • the INHIBIT gate 7 is closed through an OR gate 10 as an AND gate 17 becomes logically l by being fed clock pulse T and the instruction pulse.
  • the contents of the first time-space register are also transferred to the third time-space register through the AND gate 9 as the gate 16 becomes logically l by being fed clock pulses T-l, T and the instructional pulse.
  • the time-space registers in the circulating register are arranged in an order of the first, the second, the third and the fourth time-space registers, the contents of each digit of the first time-space register are put into the third time-space register at digit positions lower by one digit than those of the first time-space register. Thus, the contents of the first timespace register are transferred to the third time-space register while being shifted to the right by one digit.
  • FIG. 6A shows the initial state of the time-space registers.
  • the state of the time-space registers changes to the state shown in .FIG. 68 after the first operating step.
  • the second operating step the same operation as in the first operating step, is executed.
  • FIG. 6C shows the final state of the timespace registers after the second operating step.
  • the contents of the first time-space register and the third time-space register are shifted to the right by one digit.
  • right shifting means of a simple construction for a digital data processor in accordance with the invention reduces the numbers of the four-bit shift registers necessary for the conventional right shifting means. Such reduction need not be limited to a case of the four-bit shift register.
  • the right shifting means in accordance with the present invention makes it unnecessary to employ additional means for transferring the contents of the third register to the first register in the multiplication operation. Therefore, the circuit construction for the multiplication operation becomes simple.
  • a right shifting system for a circulating register storing a plurality of time-space registers in serial of bits, in time division serial of time-space registers and in serial of digits comprising:
  • a second shift register means which receives output signals from said first shift register means
  • an input gate means having an output coupled to said first shift register means and which feeds input signals from said shift register means and for which two signal paths are provided, the first path receiving output signals from said first shift register means and the second path receiving output signals from said second shift register means which is delayed depending upon the length of said second shift register means compared with the signals in said first path;
  • a control circuit means which is coupled to said input gate means and which controls the flow of signals through said input gate means from said two signal paths selectively so that the right shifting operation of the contents of at least two time-space registers of said plurality of time-space registers is completed by repeating a couple of operations, the first of which is transferring the contents of the foremost time-space registers to the hindmost time-space register of said at least two time-space registers at a digit position lower by one digit than a normal digit position of said foremost time-space register, and the second of which is transferring the contents of said at least two time-space registers except the foremost time-space register ahead by one time-space register position in said at least two time-space registers by using said first path during each operation step until all the contents of said at least two time-space registers are shifted to the right by one digit.

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  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Computational Mathematics (AREA)
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US11385A 1969-02-26 1970-02-16 Right shifting system with data stored in polish stack form Expired - Lifetime US3674997A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP1519769A JPS5529454B1 (fr) 1969-02-26 1969-02-26
JP1519869 1969-02-26
FR7006784A FR2077935A1 (fr) 1969-02-26 1970-02-25

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FR (1) FR2077935A1 (fr)
GB (1) GB1306256A (fr)
NL (1) NL153691B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3889110A (en) * 1972-03-03 1975-06-10 Casio Computer Co Ltd Data storing system having single storage device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3405392A (en) * 1965-04-30 1968-10-08 Sperry Rand Corp Electronic calculators
US3526760A (en) * 1966-04-01 1970-09-01 Singer Co Square root calculator employing a modified sum of the odd integers method
US3531632A (en) * 1967-06-30 1970-09-29 Singer Co Arithmetic system utilizing recirculating delay lines with data stored in polish stack form

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3405392A (en) * 1965-04-30 1968-10-08 Sperry Rand Corp Electronic calculators
US3526760A (en) * 1966-04-01 1970-09-01 Singer Co Square root calculator employing a modified sum of the odd integers method
US3531632A (en) * 1967-06-30 1970-09-29 Singer Co Arithmetic system utilizing recirculating delay lines with data stored in polish stack form

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3889110A (en) * 1972-03-03 1975-06-10 Casio Computer Co Ltd Data storing system having single storage device

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GB1306256A (fr) 1973-02-07
DE2004754A1 (de) 1971-05-19
FR2077935A1 (fr) 1971-11-05
DE2004754B2 (de) 1976-07-29
NL7001061A (fr) 1970-08-28
NL153691B (nl) 1977-06-15

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