US3673431A - Low voltage pulser circuit for driving row-column conductor arrays of a gas discharge display capable of being made in integrated circuit form - Google Patents

Abstract

There is disclosed an interfacing system for driving row-column conductor arrays to the gas discharge display panel in a low cost integrated circuit assembly. Due to the requirement of opposite polarity or bidirectional signals being applied to the conductors in the arrays, although the integrated circuits are functionally identical in translating low level logic signals to high voltage pulse signals which are algebraically added to sustainer voltages, the circuits are modified so as to permit NPN PNP transistors to be formed on the same chip and thus simulate a power PNP transistor.

Description

United States Patent [151 3,673,43 1 OBrien 1 June 27, 1972 [54] LOW VOLTAGE PULSER CIRCUIT FOR 3,611,296 10 1971 Johnson ..31s/169 DRIVING ROW-COLUMN CONDUCT 3,356,898 12/1967 Dano ..3l5/169 ARRAYS OF A GAS DISCHARGE 3,522,450 8/1970 Muenter ....307/241 3,382,377 5/1968 Hufiman et al. ..307 241 DISPLAY CAPABLE OF BEING MADE IN INTEGRATED CIRCUIT FORM [72] Inventor: Thomas Edward OBrien, Philadelphia,

[73] Assignee: Owens-Illinois, Inc;

[22] Filed: May 28, 1971 [21 1 Appl. No.: 147,764

[52] US. Cl. ..307/24I, 315/169 R, 307/255 [51] Int. Cl. ..H05b 41/00 [58] Field ofSearch ..307/24l,255;315/169R [56] References Cited UNITED STATES PATENTS 3,499,167 3/1970 Baker et a1 ..313/220 ENABLE CP-l ' PC-IO COL DATA Primary Examiner-Donald D. Forrer Assistant Examiner-Harold A. Dixon Attorney-Beveridge & De Grandi ABSTRACT There is disclosed an interfacing system for driving row 3 Claims, 1 Drawing Figure LOW VOLTAGE PULSER CIRCUIT FOR DRIVING ROW- COLUMN CONDUCTOR ARRAYS OF A GAS DISCHARGE DISPLAY CAPABLE OF BEING MADE IN INTEGRATED CIRCUIT FORM The present invention relates to new and improved circuitry for supplying discharge condition manipulating pulse potentials to the row-column conductor matrices of gas discharge display-memory panels of the type disclosed in Baker et al. U.S. Pat. No. 3,499,167 and British Pat. Specification No. 1,161,832. It is an improvement on the circuits disclosed in Johnson U.S. Pat. application Ser. No. 888,743 now U.S. Pat. No. 3,611,296 and Johnson U.S. Pat. application Ser. No. 821,306 now U.S. Pat. No. 3,614,739. The gas compositions used in the panel shown in the Baker et al. patent have been greatly improved to now permit driving same by integrated circuits. In such gas discharge panels, the applied voltages are usually of two types, one typically denoted as the sustainer voltage is a periodic voltage which may be continuously or discontinuously applied but is typical of a sinusodial, square, triangular, etc. wave shape. This sustainer voltage must be applied commonly to all row and column conductors and, typically, one-half of the sustainer voltage is applied to one of the conductors of the array and the other half, 180 out of phase with respect to the former half, is applied to the other conductors of the array and, in a preferred arrangement as disclosed in the aforementioned Johnson patents, are applied via the pulsing circuits which supply the other potentials referenced above. This second potential is a unidirectional voltage pulse, one-half applied to the row conductors and one-half of which is applied to the column conductors but of opposite polarity. Hence, the circuitry for driving a row-column array in the panels must be constructed at relatively low cost and high reliability. At the same time, it is highly desirable to provide logic circuitry in the integrated circuit environment or structure so as to reduce the number of wires or conductors of the panel. In this connection, logic circuitry as well as the arrangement of the circuits on the panels per se are known. It will be apparent that the circuitry disclosed herein need not be directly mounted on the panel but may be mounted or printed circuit boards and connected to the panel by flexible cables, conductors and the like.

Referring now to the drawings which disclose a preferred embodiment of this invention, there is shown a gas discharge display/memory panel of the type disclosed in Baker et al. U.S. Pat. No. 3,499,167. The panel is composed of a pair of glass plates 10 and 11, plate 10 carrying row conductor array 12 and plate 11 carrying column conductor array 13, respectively. The odd numbered conductors R1, R3 R19 Rn in the row conductor array 12 being served from one side of the panel whereas the even numbered conductors may be served from the opposite side (not shown). ln a similar fashion, column conductors 13 are carried on plate 11 and odd numbered or alternate ones of the column conductors C1, C3, C C19 Cn, are served from the lower plate extension, whereas the even numbered column conductors are served from circuitry on an opposite edge extension of plate 11 (not shown). It will be appreciated that all conductors may be served from the same side or in various other orientations or groupings not here pertinent.

The conductors within the active area of the panel have a dielectric coating 15 and 16, respectively, and the plates are joined by a spacer sealant 17 to form a thin (under about mils) gas discharge chamber 18 containing a gaseous discharge medium. Preferably, the gas is of a type disclosed in Belgian Pat. No. 739,303 corresponding to Nolan application Ser. No. 764,577, filed Oct. 2, 1968.

Each of row conductors, R1 R3, R5 R19, is served by an individual pulser PR1, PR3, PR5 PR19, respectively, and each of the column conductors C1, C3, C5 C19, are served by an individual column PCl, PC3, PCS PC19, respectively. As shown, each pulser is associated with a gate circuit (to be described in greater detail hereinafter) each gate circuit requiring an enable pulse which is applied in common to the gate circuit in all pulsers in a sector on row enable bus 21 and a data input pulse as applied on data input terminals, row data 1, row data 3, row data 5 row data 19. Similarly, the column pulsers PCl, PC3 PC19 are each equipped with logic circuitry driven by a pair of input pulses, one of which is the column enable pulse on the column enable bus 22 and the column data terminals, column data terminal 1, column data terminal 3, column data terminal 5 column data 19. Thus, in order to activate any pulser circuit whether it be a column pulser or a row pulser requires two pulses, one specific to the pulser circuit per se as applied to the data terminals and one specific to a particular sector or area of the panel and designated as the enable pulse (row and/or column). The row pulsers and logic circuits are isolated electrically from the column pulsers and logic circuits by an isolation circuit, now shown. It will also be appreciated that more or less pulsers may be controlled by a single enable pulse to row or column pulsers, respectively.

All of the pulser circuits require a low voltage (no greater than approximately 12 volts) potential for operating the control or logic circuitry inputs and a relatively higher voltage (approximately 50 volts) for supplying high voltage pulses to be algebraically added to the sustainer voltages. This direct current voltage is bidirectional in the sense that there is a corresponding negative voltage (minus VHV) applied. Thus, in general there will be four direct current voltage supplied VHVl, VHV2, VLVl and VLV2 as shown. It will also be noted that as in the case of the above-referenced Johnson patent applications, the sustainer voltages (Vs/2) are applied in series with the high direct current voltages and passes substantially unattenuated through the pulser circuits to the row and columnconductors, respectively.

Although the function of the circuits for driving the row and column conductors are identical in converting or translating low level logic signals to high level voltages and at the same time passing, in unaltered form, the sustaining voltage, because of the differences in conductivity types and the inherent differences in materials for fabricating such structures, the circuits are difi'erent. It is with respect to the specific circuitry for permitting the relatively inexpensive manufacture of low voltage pulser circuits (approximately 50 volts) that the present invention finds its greatest utility. Moreover, it is with respect to the supplying of such potentials to a gas discharge display/memory panel of the type disclosed in the aforementioned Baker et al. patent as well as other gas discharge panels and cross matrix display systems that the invention finds specific usefulness. Obviously, the row and column pulser circuits may be interchanged so that row type pulsers drive column conductors and column type pulsers drive row conductors.

ROW PULSER CIRCUITS The row conductor pulser circuits will be described first and in this connection, reference is made to row pulser circuit PR-ll, which is shown in detail, it being understood that the remaining pulser circuits are all identical except for enabling input NPN transistor circuitry Q1 and Q3. It will be further understood that all of the pulser circuits PR1, PR3 PR19, including logic transistors Q1, Q2, Q3 and Q4, are made on a common circuit chip with the only external terminals being the low voltage terminal LV (12 volts) the higher voltage terminal I-lV (50 volts) enable input terminal RE, and data input terminals 1, 3, 5 l9. NPN transistor Q1 has its collector electrode connected to enable input tenninal and its collector electrode connected in common +VHV1 and +VLV1. The emitter of NPN transistor O1 is connected through an emitter resistor R10 to a pair of NPN transistors Q3 and Q4, transistor Q3 having an emitter resistor R1. Transistors Q3 and Q4 constitute a differential current splitter with transistor Q4 serving as a current source to the switching circuit. In common with O4 collector is a data" input transistor Q2 which is an NPN transistor having its base electrode connected to data" input temiinal. The common point A between the emitter of transistor Q2 and the collector of transistor O4 is connected to the common terminals of the cathodes of diodes CR1 and CR2. The anode of diode CR2 is connected through a resistor R5 to the circuit common terminal and the cathode of CR2 is connected through diode CR1 and resistor R3 to the high voltage supply VHV1 (50 volts). The intermediate point B between diode CR1 and resistor R3 is connected into the base electrodes of transistors Q5 and CR3. It will be noted that transistor CR3 is connected to serve as a diode. The intermediate point C between diode CR2 and resistor R5 is connected to the base electrode of switching transistor Q6. The emitter of transistor Q6 is connected to the circuit common whereas the collector is connected to the base electrode of transistor Q7 which is an amplifying transistor and through a collector resistor R4 to the collector of transistor CR3. The base of switching transistor Q5 is connected to the intermediate point between resistor R3 and diode CR1.

This circuit operates as follows: an enable voltage pulse (minus 12 volts to volts from conventional MOS logic, now shown) in conjunction with a data input signal voltage (0 to minus 12 volts from conventional MOS" logic source, not shown) on data input terminal l1 controls the switching amplifier which includes resistor R transistors Q6, Q7, Q5 and transistor CR3. Transistors Q3 and Q4 are used in a differential current splitter of the Widlar technique. Transistor O4 is used in this configuration to drive transistors Q6 and Q7 on through diode CR2. Transistors Q6 and Q7 are used in an NPN-PNP fashion to simultate a power PNP transistor. In this connection, it is important to note that a high voltage, high power PNP transistor is not possible using some integrated circuit fabrication techniques (e.g., diode isolation, for example) so this requires transistors Q6 and Q7 to be used in a complementary configuration to simultate a high power PNP transistor. The enable" input pulse drives all the circuits by steering the current out of transistor Q4, via O3 in a differential current splitter configuration. The data input drives transistor Q2 .to either allow the current from Q4 to pass into the switch or to shunt it away from the switch. Transistor Q2 operates in the off mode thus allowing the current out of transistor Q4 to go through diode CR2 and into transistor Q6 giving a pulse output. Due to the data input requirement to vary between 0 and minus 12 volts, transistor Q2 is designed to have an emitter base breakdown voltage of 7 -10.5 volts. In this connection it should be noted that generally the fabrication of most integrated circuits uses a base concentration of somewhere between 6 X to about 9 X 10. This concentration results in an emitter base breakdown anywhere between 6.5 to 8.5 volts. The base concentration that is used to achieve a higher emitter base diode is somewhere around I to 2 X 10. This low concentration diffusion is generally used for making resistors of a more comfortable length when a high value resistor is needed. Using a low concentration base for the purpose of a high base-emitter voltage in integrated circuits however is not commonly used.

COLUMN PULSER CIRCUITS Referring now to the column circuitry, it will be described in connection with column pulser PC-ll, it being understood that this circuitry is identical in all of the PC packages and the only difference being to the use of the common enable input transistor Q10. In this configuration, the emitter follower Q10 is simply a current switch for transistor Q1 1. Transistor Q1 1 is an emitter follower transistor which is driven on by the voltage across resistor R10. Resistor R12 determines the current to the output stage. Transistors Q12, Q13, Q14 and Q15 operate identical to the corresponding transistors Q2, Q6, CR3 and Q5 in the row pulser circuitry except for the use of the transistor pair Q6, Q7, made to look like or operate similar to an PNP transistor. That is, transistors Q6 and Q7 find their equivalency in transistor Q15 and operate, essentially, in the same fashion. It will be noted that in this circuit resistor R12 is used in place of a current source out of the emitter follower to avoid over drlvrng the output switch. In this manner, transistor Q11 is used in a similar fashion to simulate a constant current source by virtue of the high value of emitter resistor R12. As in the row pulser circuitry, transistor Q12 is driven by the data input and either allows the current through R12 to pass into the switch or shunt it away from the switch.

While a preferred embodiment of the invention has been shown and illustrated in the drawings, it is to be understood that the invention is not to be limited to the exact form there shown for many changes may be made, some of which have been suggested herein, within the scope of the following claims.

What is claimed is:

1. An integrated circuit system for supplying sustaining voltages and discharge manipulating pulse voltages to one group of row conductors and one group of column conductors in a gas discharge device in which transversely oriented row and column conductors effecting discharges in the gas have dielectric charge-storage means, for charges produced on discharge, interposed between said row and column conductors and the gas, comprising in combination, at least a pair of monolithic semiconductor bodies, each processed to include a plurality of individual transistor switching circuits connected by conductors in circuit configurations described, hereinafter including a plurality of contact areas to which connections to and from said circuit configurations are made, each said circuit configuration being functionally identical, wherein: each circuit configuration translates a low level input pulse signal voltage to a high level pulse signal voltage and feeding through a high level periodic signal voltage as said sustaining voltage, the output voltages from each circuit configuration being of opposite polarity, respectively, the improvements wherein:

each said circuit configuration on one of said bodies including as means for translating low level pulse signal voltage to a high level pulse signal voltage a pair of complementary configured transistors formed in NPN PNP fashion to simulate a power PNP transistor, and each said circuit configuration on the other of said bodies including as means for translating low level pulse signal voltages to a high level pulse signal voltage a power NPN transistor.

2. The invention defined in claim 1 wherein a plurality of the circuit configurations on a body are controlled by a common enabling pulse voltage, the further improvements wherein, with respect to the said circuits on said one of said bodies, said enabling pulse voltage is applied to said circuits through a differential current splitter circuit on said body.

3. The invention defined in claim 2 wherein the said current splitter circuit is constituted by a first transistor element and a plurality of second transistor elements, said plurality of second transistor elements being unique to each said circuit configuration and said first transistor circuit element being common to all said plurality of circuit configurations.

Claims (3)

1. An integrated circuit system for supplying sustaining voltages and discharge manipulating pulse voltages to one group of row conductors and one group of column conductors in a gas discharge device in which transversely oriented row and column conductors effecting discharges in the gas have dielectric charge-storage means, for charges produced on discharge, interposed between said row and column conductors and the gas, comprising in combination, at least a pair of monolithic semiconductor bodies, each processed to include a plurality of individual transistor switching circuits connected by conductors in circuit configurations described, hereinafter including a plurality of contact areas to which connections to and from said circuit configurations are made, each said circuit configuration being functionally identical, wherein: each circuit configuration translates a low level input pUlse signal voltage to a high level pulse signal voltage and feeding through a high level periodic signal voltage as said sustaining voltage, the output voltages from each circuit configuration being of opposite polarity, respectively, the improvements wherein: each said circuit configuration on one of said bodies including as means for translating low level pulse signal voltage to a high level pulse signal voltage a pair of complementary configured transistors formed in NPN PNP fashion to simulate a power PNP transistor, and each said circuit configuration on the other of said bodies including as means for translating low level pulse signal voltages to a high level pulse signal voltage a power NPN transistor.

2. The invention defined in claim 1 wherein a plurality of the circuit configurations on a body are controlled by a common enabling pulse voltage, the further improvements wherein, with respect to the said circuits on said one of said bodies, said enabling pulse voltage is applied to said circuits through a differential current splitter circuit on said body.

3. The invention defined in claim 2 wherein the said current splitter circuit is constituted by a first transistor element and a plurality of second transistor elements, said plurality of second transistor elements being unique to each said circuit configuration and said first transistor circuit element being common to all said plurality of circuit configurations.

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