US3754230A

US3754230A - Plasma display system

Info

Publication number: US3754230A
Application number: US00099798A
Authority: US
Inventors: E Auger
Original assignee: Raytheon Co
Current assignee: Raytheon Co
Priority date: 1970-12-21
Filing date: 1970-12-21
Publication date: 1973-08-21
Anticipated expiration: 1990-08-21
Also published as: JPS5329054B1; GB1370676A

Abstract

Visual display systems such as plasma displays in which a diode and resistor matrix provides writing, erasing and sustaining voltages to a plurality of elemental areas to produce visual indications without interference between the various supplied voltages, whether dc, ac or pulse for coupling control signals and logic to a large number of elements with a reduction in the required number of switches and circuit connections is described.

Description

United States Patent [191 1111 3,754,230 Auger 1 Aug. 21, 1973 PLASMA DISPLAY SYSTEM 3,573,542 4/1971 Mayer et a1 340/324 R 2,995,682 8/1961 Livingston 315/169 R [75] Invent Ernes Auger Blnenca, Mass- 3,609,746 9/1971 Trogdon 340/324 R [73] Assignee: Raytheon Company, Lexington,

M Primary ExaminerDavid L. Trafton Attorney-Milton D. Bartlett, Joseph D. Pannone, [22] Filed: 1970 Herbert W. Arnold and David M. Warren [21] Appl. No.: 99,798

[57] ABSTRACT 52 us. c1. 340/324 M, 315/169 R, 315/171, Visual p y systems such as plasma p y in which 340/1 EL a diode and resistor matrix provides writing, erasing [51] Int. Cl. G08b 5/36 and Sustaining voltages a plurality of elemental areas [58] Field of Search 340/324 R, 166 EL; to produce visual indications i h u int rferen e be 315/1 9 R 171 tween the various supplied voltages, whether dc, ac or pulse for coupling control signals and logic to a large 5 R f r Cited number of elements with a reduction in the required number of Switches and Circuit connections is de- 3,689,912 9/1972 Dick 340/324 R scnbed' 3,559,190 1/1971 Bitzer et a1. 340/173 18 Claims, 16 Drawing Figures WRITE ERASE RESET SUSTAIN 1 -//6 SUSTAINER lWRlTE/ERASE GENERATOR M0 DRIVER 5 1 NEGATIVE R EDGE *1 I S W l T C H 8311a,, i D L l L -I l an ----1 I i //30 //34 l 1 m4 m6 /0& //0 A ./B X AXIS PA N E L L! N E s 1 l //20 3%r/24 -/28 -52 T 1;; 1 A l f /46 F /48 1 1 M N 3 5 &1 .43 1 I00 SUSTAIN g E SWITCH 1 i e V/2A Shaw 25 PArEmEumm ms SHEET 1 (IF 7 l8 /0 I) I SWITCHING UTILIZATION CENTRAL MATRIX DEVICE COMPUTER SWITCHING UTILIZATION MATRIX DEVICE W, $WITCHING UTILIZATION MATRIX DEVICE WRITE ERASE RESET SUSTAIN I //4 WRlTE/ERASE G E I I E R A TDTQ M0 DRIVER I PAIENTEIIIIIIIm Ian 3,754,230

SHEU UT 7 /68 /76 TO FROM TO FROM IsOLATION susTAINER IsOLATION wRITE/ERAsE N ETWQRK GENERATOR NETWORK DRIVER FROM FROM LOGIc LOGIc MATRIX MATRIX [-76 /2 -92 LOGIC 76 84 susTAIN SWITCHES 88 WR'TEIERASE I susTAINER DR'VER GENERATOR I I6 l ,wRITE/ERAsE LINES SWITCHES l6 70 73 LINES l ISOLATION V LOGIC "94 NETWORK 25s 74 LINES g x CHANNEL GENTRAL PLASMA COMPUTER DISPLAY Y HANNEL 256 I0 96 LINEs i V LOGIc ISOLATION NETWORK a0 LIISES 86. v susTAI N I6 I SWITCHES LNES WRITE/ERASE SUSTAI NER DR'VER GENERATOP 90 WRITE/ERASE SWITCHES V LOGIC PATENTEUMJBZI ma SHEET 5 OF 7 WQY W w l I l 4 1 1 w fi l fiw u E PATENIEDAUSZI I975 SHEET 7 [IF 7 FROM Y 386 W/E SWITCH 350 380/ -FROM Y-SUSTAINER SWITCH JFROM w E SWITCH FROM Y-SUSTAINER SWITCH FROM X r SUSTAINER SWITCH FROM X W/E SWITCH FROM X SUSTAINER SWITCH FROM x W/E SWITCH PLASMA DISPLAY SYSTEM BACKGROUND AND SUMMARY OF THE INVENTION This invention relates to visual display systems having a switching and control matrix providing for the simplification of circuitry and the reduction of components for switching and control of a large quantity of input signals. More particularly, a visual display system is described embodying the present invention in which a display is provided by a matrix which is an improvement over prior art systems in that fewer components and circuit connections are required to couple data from a computer or other data input source to the display. Isolation of the power signals, required to provide the major portion of the visual indication energy and/or to sustain display data from data signals, required to write or erase data, is provided by circuitry which allows the data signals to be applied simultaneously with the power signals without loss of data. Prior art systems cannot apply these voltages simultaneously because such systems cannot provide for isolation, and, in systems of the prior art, loss of data and fading can occur when writing or erasing, thus, an improved display system requiring fewer components and circuit connections with a resultant savings in cost is provided.

The present invention provides a method of applying an alternating or varying dc voltage to a plurality of nodes of a matrix simultaneously, with the ability to increase the voltage or pulse on any single node simultaneously and without interference with the voltage on the other nodes. This technique is particularly applicable to those visual displays in which visual indications are controlled by lines individually connected to each of said nodes and using circuitry in which two or more control signals or nodes are required to switch or gate a large number of incoming data signals through a matrix to the display system.

Display systems of the prior art, in which control signals must be brought to the display elements require in addition to circuit connections in the X and Y plane for every element, a switching circuit for each element to provide for element selection. In a display of 256 by 256 elements, a minimum of 1,024 switches would be required. The present invention optimally requires a number of switches substantially equal to twice the square root of the number of lines in each channel or axis. Thus, for a 256 by 256 matrix, only 32 switches for the X axis and thirty-two switches for the Y axis, for a total of 64 switches are required to gate in all of the memory control signals.

If a writing signal were inadvertently superimposed upon a power or sustaining signal, the wrong element would light and an inaccurate and incoherent display would result. This is the reason that systems of the prior art required individual switches for individual elements to provide isolation.

The present invention provides a plurality of switches for the X and Y axis of the crossed grids of a capacitively coupled display in which the switches are used only when the displayed data is to be changed. The data that is not changed is displayed by the continued application of a sustaining voltage through the switches which are all open and consuming no power.

In voltage controlled displays such as a plasma display, a gas discharge may be maintained or sustained by a voltage less than that required to create the discharge, hence, the plasma display has an inherent memory in the sense that as long as a sustainer voltage is applied to the display, the displayed data, which is comprised of a plurality of glowing cells, will be maintained by the sustainer alone with no requirement that refresh signals be continuously supplied from a central data source such as a computer. Thus, computer interface time is greatly minimized in a plasma display system. An additional advantage of such a system is that the display and circuitry associated therewith is essentially flat, since no cathode ray tube is required, and because it is transparent, the plasma display may be used as an overlay over another display source such as a cathode ray tube display to give a composite display.

The circuitry of the present invention permits writing and erasing voltages to be applied to selected crossings of X and Y axis grid points by closing selected Write/E- rase switches and opening selected sustainer switches in accordance with predetermined logic. The closed switches brings the desired voltages to nodes through isolation diodes and resistors, and the open switches prevents the voltages from being shunted from the desired nodes to undesired nodes. All. of the closed switches shunt other nodes to the sustaining voltage source. Writing speed is increased in the present system because the sustainingvoltage does not have to be removed from any nodes when writing at other nodes as in the prior art, hence, simultaneous writing and sustaining is accomplished by the present invention. The present system gates the digital input signals to the switches which in turn gates the required control voltages to the display.

BRIEF DESCRIPTION OF THE DRAWINGS Other and further advantages of the invention will become apparent in connection with the accompanying drawings wherein:

FIG. 1 illustrates a block diagram of a system embodying the invention;

FIG. 2 illustrates a plasma display panel of the type with which the present invention may be utilized;

FIG. 3 illustrates a gas discharge characteristic curve;

FIGS. 4 through 7 illustrate functional equivalent circuits of the various operating modes of an embodiment of the present invention; I

FIG. 8 is a waveform employed in an" embodiment of the present invention;

FIG. 9 is a block diagram of an embodiment of the present invention;

FIG. 10 is a simplified equivalent circuit diagram of an embodiment of the present invention;

FIG. 11 is a circuit diagram of a sustainer switch of the present invention;

FIG. 12 is a circuit diagram of a write and erase switch of the present invention;

FIG. 13 is a circuit diagram of a sustainer generator for generating the waveform of FIG. 8 in accordance with the present invention;

FIG. 14 is a circuit diagram of a driver circuit in accordance with the present invention;

FIG. 15 is a circuit diagram of the X axis circuit connection to a 64 line plasma display; and

FIG. 16 is a circuit diagram of the X and Y axis circuit connection to a four line plasma display.

DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to FIG. 1, a switching matrix in accordance with the present invention is illustrated coupled to a central computer shown generally at 10. Positional data, radar presentations, weather data and other information is stored or received at computer for coupling to and display or storage at utilization devices such as 18, and 22 which may comprise visual displays or other signal utilization means. Switching matrix 12 couples data from the computer 10 to utilization device 18 without the need for refreshing signals from the computer, with minimal circuit connections, and with less demand on computer time than systems requiring a constant refresh, due to the inherent memory of a plasma display in conjunction with reduced data requirements and reduced circuitry. Other utilization devices, particularly displays of the plasma type, may be coupled to computer 10 by

additional switching matrixes

14 and 16, which serve to couple different signals which may be dc or ac voltages or pulses to the displays simultaneously and without mutual interference.

Referring now to FIG. 2, there is illustrated a plasma display panel of the capacitive discharge type with which the present invention is particularly advantageous. Essentially, the panel is a flat gas filled glass plate with orthogonal conductors which may be plated thereon on opposite sides of a glass plate.

Glass plates

30 and 32 form a backing on horizontal and vertical rows of conductors 34 and 36 respectively with thin layers of

glass

38 and 40 deposited between the conductors and the plasma 42 such that a point of light appears at the junction of a row and a column connector when an appropriate voltage is applied to any pair of lines. A constant ac voltage, the sustainer, must be applied to all of the lines to sustain the light after the initial discharge or writing, thus the panel has discreet threshholds for writing, erasing, and sustaining as will be explained.

The plasma display is a digital storage device with two stable states determined by the presence or absence of charge on the

glass plates

38 and 40. The individual cells of the display are excited by an alternating signal, the amplitude of which, when large enough, causes the gas in the cell to ionize when the voltage exceeds the firing potential of the plasma, which discharge develops into a glow and illuminates the

transparent glass walls

30 and 32. The plasma display accepts digital data directly with no analog circuit requirements, and stores the data by virtue of its inherent memory" resulting from the wall charge on the display walls. The capacitive coupling to the plasma cells provides natural isolation, and since no electrodes are present in the cell, higher density displays then are possible with conduction type plasma displays may be realized.

Referring now to FIG. 3, there is shown a graph illustrating the operation of a typical gas tube which generally corresponds to an individual elemental area of a plasma display. The term minimum breakdown distance" is defined as being the distance between two electrodes in a gaseous medium where the smallest voltage between the electrodes is required to create a discharge between the electrodes. It may be noted that this distance will vary in accordance with the pressure and type of gas surrounding the electrodes and electrode configuration. When the grid is positioned at the minimum breakdown distance from the cathode, the oscillations produced in a gas tube prior to breakdown of the tube will be less than those produced with other spacings of the electrodes since the oscillation generated between the grid and cathode in general vary directly as a function of the voltage applied between the grid and cathode. Thus, by positioning the grid at the minimum breakdown distance from the cathode, maximum stability of the device is achieved.

The voltage between the grid and the cathode of a typical gas tube is plotted along the abscissa of the graph and the current drawn from cathode to grid is plotted along the ordinate in amperes. When the current of the discharge is 10 Amperes or less as shown by the area labeled Townsend discharge, the voltage across the discharge varies directly as a function of the current such that when the voltage increases the current increases. When the voltage is increased to a point beyond that required to produce 10 Amperes as shown by point A, the current will then increase with a decrease in voltage thereby entering the region labeled normal glow. Point A is the tube firing point and upon firing of the tube the grid current will not pass beyond the normal glow region because the grid voltage would be lowered below that required for maintaining the discharge between grid and cathode. Thus, it may be seen that once a sufficient voltage is applied to increase the current along the curve to point A the current will then rapidly increase to form a glow discharge between the grid and cathode. Some electrons from the glow discharge will move through the grid section and be accelerated to the anode and will ionize the space therebetween to thereby establish cathode-to-anode conduction and fire the tube.

If the voltage between the electrodes is maintained below that required to produce the current at point A, this voltage being in this case by way of example, approximately l8O volts, the current will not increase to form an arc. Thus, for example, where the grid voltage is maintained at 178 volts above the cathode the current is on the order of i0 Amperes. A positive signal voltage of 2 volts applied to the grid would be sufficient to fire the tube thereby producing a circuit having extremely great sensitivity. The point where the current begins again increasing with an increase in voltage is the abnormal glow region shown at point B in which region greater voltages are required to produce greater conduction current. In a plasma display, the X and Y axis intersection. corresponds to theabove described electrode. I

The voltage requirement at point B is the minimum sustaining voltage required to maintain the discharge, and the memory margin, or inherent memory of the plasma display is proportional to the voltage difference between points A and B by the relationship:

M= V V /l/2 V,,, where M is the memory margin and V, V is the bistable range.

Referring now to F168. 4 through 8, functional equivalent circuits are illustrated which are representative of the various operating modes of the plasma dis play. These modes are the Erase mode, the Write mode, the positive half cycle emitting mode, the negative half cycle emitting mode and the erased mode, wherein:

C the capacitance of the plasma C, represents the capacitance of the glass dielectric on either side of the plasma.

C, represents stray capacitance across the conductor grid lines crossing over the cell.

V the external applied cell voltage.

In accordance with Kirchoffs laws, V, C,/C,, 2C V,,.

Thus, it may be seen that the firing voltage V, which is the externally applied voltage just sufficient to start a sequence of discharges must be greater than the actual voltage required to cause these discharges since all of this voltage does not occur across the plasma cell. The actual external applied voltage is V,, a sustaining voltage, when the information is displayed but not changed and is, of course, less than the firing voltage but sufficient to sustain the discharge sequence.

The recurrent voltage is the magnitude of the externally applied voltage at which each discharge of a sequence of discharges is initiated and in symmetrical waveforms the recurrent voltage is the same on both positive and negative half cycles.

The writing voltage V is the amplitude of the externally applied voltage when a cell is turned on, which voltage is higher than V,, while the erase voltage V, is the amplitude of an applied voltage when a cell is turned off and is less than the sustaining voltage.

The erased mode is illustrated by FIG. 5. The plasma cell is the electrical equivalent of capacitor 50. Capacitors S2 and 54 represent the capacitance between the plasma cell and the X and Y connector lines respectively with V, being the voltage applied on the X line and V,, the voltage applied on the Y line. This circuit is a simple ac voltage divider and the voltage which is developed from the ac sustaining voltages across

capacitors

52 and 54 is insufficient to ignite the cells, thus ionization does not occur. The total plate to plate voltage at any time is V, V V

In order to write, or to cause ionization across a plasma cell with the resultant glow discharge, an additional voltage must be superimposed on the sustaining voltage such that the increased net voltage will be large enough to ignite the cell as may be seen from the waveform of FIG. 8 and in equivalent circuit form in FIG. 6 in which the equivalent circuit for the emitting or writing mode during the positive half cycle of the sustaining cycle is illustrated, which cycle in the upper waveform of FIG. 8. The voltage source 60 in combination with diode 62 is representative of a threshold condition above which current is allowed to flow through the light source 64 and thus generate light. Of course, light source 64 is the ionized and glowing plasma. When this happens the impedance of the plasma cell 64 suddenly drops and the basic ac voltage divider as shown in FIG. 5 is altered since capacitor 50 can acquire no more voltage as the input voltage continues to rise, and as a result capacitances 52 and 54 acquire larger voltages than they do in the erased mode discussed with reference to FIG. 5 and the polarity of the charge on

capacitances

52 and 54 of FIG. 6 is such that they will add to the sustaining voltage in the subsequent negative half of the sustaining voltage cycle, thus it may be seen that the sustaining voltage alone is large enough to reignite a plasma cell in each subsequent half cycle due to the assistance of this additional charge on

capacitances

52 and 54.

When writing, the voltage across capacitor 50 ignites the gas on the positive sustaining cycle. From the curve of FIG. 3 it may be observed that once in the normal glow region, this voltage is approximately constant with increasing current, thus the voltage across

capacitors

52 and 54 increases, and V, is greater after a write pulse than after a normal sustaining pulse, the ratio of V to V, is changed and a closed circuit after ignition results. V, is regenerated with reversed polarity each cycle as may be seen from FIG. 7, in which the equivalent circuit for the emitting mode during the negative half of the sustaining cycle is illustrated. This charging is identical to the emitting mode during the positive half cycle except that all of the polarities are reversed.

Capacitors

52 and 54 are initially charged as in the positive half cycle, with polarity reversal at the sustainer frequency. v

To selectively erase, an erase pulse is applied to the appropriate X and Y lines, which pulse is smaller in amplitude than that which is used for writing as may be seen with reference to the waveform of FIG. 8. Additionally, the Erase pulse is applied between sustain pulses; hence, the erase pulse is basically a weak sustain pulse which is large enough to ignite the cell, which discharges the coupling capacitors in the cell without which reversal of polarity and charge memory is lost and the cell will not ignite in subsequent cycles unless it is again written into. The lost memory is of course, the lost wall charge. When erasing, the applied voltage falls below point B on the curve of FIG. 3, hence the gas is in the Townsend discharge region and an increase in applied voltage increases the voltage across the equivalent capacitance 50 without increasing V, across

capacitors

52 and 54..Thus, the absolute value of V, does not increase and the next sustain pulse is insufficient when added to V, to fire the cell; hence, memory is lost, or erased.

It has been found that a step pulse sequence of writing and sustaining voltage provides an improved display capability sincethe charge developed on the plasma cell-walls depends on the intensity of ionization and the duration of the discharge and a rapidly increasing applied voltage increases this intensity of ionization, and thereby the total created charge.

In the present embodiment, a steeply sloped writing pulse somewhat over 200 volts, a sustaining voltage of approximately I40 volts and an erase pulse of approximately volts are employed during periods T, and T of the applied waveform. These voltage requirements are obtainable because of the close proximity of the conductors to the glass surface of the plasma displays and the close spacing of opposing cell walls which is on the order of several mills. Additionally, the particular gas composition employed and the pressure of the gas in Torr has a direct result upon requiredionization voltages in accordance with the well-known Paschen curve for gases. Neon, Helium, Argon, Krypton, Xenon and Nitrogen, and mixtures of these gases maybe used to effect plasma discharge. For example, a Neon Nitrogen mixture with about 4 percent Nitrogen results in an adequate memory with sufficient visible light output. Of course, these voltages are applied negatively on the orthogonal grid with a resultant doubling of all applied voltages as is apparent from FIG. 8.

A composite equivalent circuit of the write, erase and erased modes of FIGS. 5 through 7 is illustrated by FIG. 4. V and V,,, are selectively applied with V, and Y, to the light source 64 at a polarity determined by

diodes

62 and 66 which in turn are biased by the charge on

capacitors

52 and 54. When the total applied voltage across light source 64 is sufficient to maintain glow discharge, visible light is emanated. Of course, the sustaining voltage applied via capacitors S2 and 54 will cause discharge only when the plasma is in the glow region of the discharge curve.

Referring now to FIG. 9, a block diagram of a plasma display system is disclosed which comprises a 256 by 256 element plasma panel which requires 2 N switches for each axis where N is the number of conductivity lines per axis. Control, timing, and selection signals are generated at the central computer which supplies the various switching matrixes, Write/Erase drivers, and sustainer generators with the appropriate command logical inputs.

The X and Y

axis isolation networks

70 and 72 described with reference to FIG. 10, couple the sustaining voltage and the write or erase voltages to the display 74 without interference with each other or with the voltages present on other modes. The isolating network comprises a matrix of diodes and resistors which may effectively be plated directly on the plasma panel as diode chips and film resistors with a resultant further reduction in circuit connection requirements.

Switchable connections in the X channel are controlled via 16 sustain switches 76 and sixteen write switches 78 and similar switchable connections in the Y channel are controlled via sixteen sustain

switches

80 and 16 write switches 82 respectively. Write and erase voltage generators 84 in the X channel and 86 in the Y channel supply the voltage pulses necessary for switching and erasing to the X and Y channels via switches 76 through 82, with timing and control coupled from the computer to

drivers

84 and 86 and to X and

Y sustainer generators

88 and 90 respectively which may be simultaneously applied to elemental areas of the display 74 through

switches

76 and 80 while isolated from writing voltages by the

isolation networks

70 and 72. Logic matrixes 92 and 94 in the X channel and 96 and 98 in the Y channel couple element selection coding data digitally directly from the computer to the switching networks, and comprise a matrix arrangement of the switches described with reference to FIGS. 11 and 12, the interface portion of which is standard transistortransistor logic modules interfacing computer 10.

Referring now to FIG. 10, a switching and control circuit in accordance with the present invention is shown generally at 100 which is particularly adaptable for use with the plasma display previously described. The illustrated circuit controls the X' axis of a simple four line plasma panel; however, any number of plasma lines may be controlled by additional connective circuitry. For a panel comprising N LINES 2 WV sustaining and writing per axis switches are required with an optimum number of panel elements. Thus, fora four line panel four switches are needed, but for a 256 X 256 line panel only 64 switches are required. These switches apply simultaneously with a control voltage and sustainer voltage without interference, one with the other, the control voltages ,being, of course, the write and erase voltages required by the glow areas.

Selection of the glow discharge points for writing or erasing is accomplished by steering voltage pulses generated in a Write/Erase driver 116 to which panel lines A, B, C and D which are illustrated as nodes 104 through 110, to which the X axis lines are coupled, the voltages on which, oppositively to the voltage counterparts on the Y axis (not shown) causes the plasma elements which are bistable devices, either on or off to glow or not glow. The write and erase signals are applied to the Write/Erase driver 116 in digital form directly from the computer.

Two types of switches are required, write switches and sustain switches. The function of the write switches 102A and 1023 is to apply a writing voltage to the panel lines 104 through which panel lines are also connected to separate sustaining switches 112A and 1 128. The function of the sustaining switches is to provide a path back to the sustaining voltage generator 1 14 for all but one of the panel lines in a group of panel lines such as 104 and 106 or 108 and 110. [n this way only one panel line will receive a writing voltage from driver 116, while all of the other lines can simultaneously be sustained. With a 50 KC pulse train, writing will occur every 20 p. sec. The writing and sustaining switches are the element switches such as transistor switches.

Each write switch couples the writing voltage to a different group of panel lines, switch 102 to

elements

104 and 106 and other switch 102 to

elements

108 and 1 10. The sustaining switches 112A and 112B couple out any panel lines from the write voltage to which writing volt ages is not intended. All other lines are coupled back to the sustainer voltage generator 114.

A diode resistor network comprising diode and resistor 122 associated with panel line 104, diode 124 and resistor 126 associated with panel line 106, diode 128 and resistor 130 associated with panel line 108 and diode 132 and resistor 134 associated with panel line 110 isolate the write voltage from the sustainer voltage such that writing and sustaining to different panel lines may occur simultaneously and glowing and sustained plasma areas will not dim while writing occurs at other panel points. Diode and resistive isolation network 120 through 134 may comprise diode chips and film resistors of well-known and conventional design, or may comprise switches such as two point diode switches.

Before writing, the write switches are open. When writing, the write switch associated with the selected panel line is closed, and a write pulse is applied to that line. For example, if it is desired to write into line 104, switch 102A is closed. The sustain switches are normally closed; however, when writing, a switch is opened. For the case described above, switch 112A is opened and the voltage applied to line 106 is conducted through closed switch 1 128 on the positive half cycle back to the sustainer generator 114. 7

During the negative portion of the sustainer waveform, the negative edge switch connects point T to point R thereby providing an unblocked path for the negative half cycle of the sustainer. Negative edge switch 140 senses when the sustainer is going negative as described with reference to FIG. 13. This is necessary because writing occurs only on the positive half cycle; hence, the separate and noninterfering negative sustaining path. During the negative half cycle,

diodes

142 and 144 block the sustainer from the panel lines, and the alternate path provided at T allows the sustainer to reach these points, and

diodes

146 and 148 block on the positive half cycle with current flow through

diodes

142 and 144. When writing, the voltage at points M and N is more positive than the sustainer voltage, and the polarity of

diodes

146 and 148 will not block this voltage, since their function is only to gate the negative sustainer to nodes A and B; hence, the alternate path.

The quantity of circuits is minimized by the matrix arrangement employed in the present invention. The base emitter of each transistor switch is connected to each other transistor switch in a diode matrix form. Both the base and emitter lines of the simple transistor current switches employed in switches 102 and 112 share a common physical location, thus common mode rejection of ground noise between the low level logic and the high level drive electronics without the need for expensive line receivers and line drivers is provided.

Referring now to FIG. 11, a sustainer switch circuit is shown generally at 160. The base emitter portion of driver transistor 162 is connected in matrix arrangement to conventional transistor transistor logic modules, thus conserving components and serving the address decoding functions. Input current is coupled through

resistors

164 and 166 to switching transistor 168 which opens and closes to provide a sustainer current path in accordance with the input control from the central computer.

Referring now to FIG. 12, a Write/Erase switch circuit is shown generally at 170. The base emitter portion of transistor 172 is connected in matrix arrangement to conventional transistor transistor logic modules in a similar manner to the matrix arrangement of the sustainer switches described with reference to FIG. 11. Input current is coupled through resistor 174 to transistor switch 176 which acts to couple the Write/Erase driver output through the switch to the isolation network in accordance with the input control from the central computer via the logic matrix. Both writing and erasing pulses are selectively coupled through transis tor 176, as these are merely time displaced voltage pulses of different magnitudes.

Referring now to FIG. 13, a circuit diagram of the sustainer generator and negative edge switch is illustrated generally at 200. The output level control circuit 202 comprises three transistor switches, 204, 206 and 208, which generate the voltages necessary to form the sustainer waveform shown in FIG. 9. A clock pulse of 50 KC is supplied to the base of transistor switch 204 which short circuits the applied voltage to ground during the zero voltage portion of the sustainer waveform.

As described with reference to FIG. 8, the erase pulse of 125 volts provides a selective erase of the display; that is, one spot at a time is erased every microseconds at 50 KC when erasure of selected areas is desired; however, a reset, or simultaneous erasure capability of all of the plasma cells, is provided by switch 206, which when actuated by the reset pulse provides a voltage drop across zener diode 210 sufficient to couple the erase voltage of 125 volts onto the sustainer line. This voltage will not cause the capacitance (from plasma to glass) to charge on the next occurring cycle, hence, erasure occurs in 20 microseconds. The sustainer switches are not reset, and the sustainer level is reduced to the erase level of 125 volts during the sustaining portion of the cycle, T

Switch 208 is supplied via the logic matrix from the central computer with a dc pulse to couple 70 volts to the sustainer line during the T portion of the cycle and a drop across zener diode 212 sufficient to result in a 70-volt output is effected.

The varying output of the level control circuit 202 is supplied to the output drive circuit 220 which comprises two complimentary Darlington

current amplifers

222 and 224 the former comprising NPN transistors and the latter comprising PNP transistors, with amplifier 222 driving the load in the positive direction and amplifier 224 driving the load in the negative direction. Biasing potentials of 140 and 200 volts are provided from external power supplies. Thus, current multiplication is provided for driving a low impedance output from a high impedance input with current gain, but no voltage gain. Diode 226 provides a conduction path from the isolation resistors for increased stability. The output on line 228 is the sustainer voltage.

The negative edge switch 230 transfers the negative portion of the sustaining voltage from line 228 to line 232 during that portion of the waveform when it is changing in the negative direction. When point R goes negative, capacitor 234 charges through the baseemitter junction of switching

transistors

236 and 238 thereby turning

transistors

236 and 238 ON which closes the switch. Suitable emitter-to-base biasing is provided by

resistors

240 and 242 for

transistors

236 and 238 respectively.

Referring now to FIG. 14, the Write/Erase driver circuit is shown generally at 250. The generated writing pulse of 200 volts is derived from an external supply, not shown, and is coupled to the write switches during a portion of the T, positive half cycle of the sustainer by a transistor switch 252 which is driven by a driver transistor 254. A suitable control pulse is applied to the base of transistor 254 from the central computer via coupling capacitor 256.

Resistors

258, 260 and 262 provide suitable biasing for

transistors

252 and 254, respectively.

The generated erase pulse of volts is similarly derived from an external supply, not shown, and is coupled to the Write/Erase switches during a portion of the T sustainer cycle by a transistor switch 264 which is driven by a driver transistor 266. While T, is approximately 5 to 8 microseconds and the time between pulses T is also from 5 to 8 microseconds, other timing sequences and voltage levels may be employed depending upon the particular characteristics of the plasma drive used. The erase pulse is advantageously of approximately 23 microseconds duration. A suitable control pulse is applied to the base of transistor 266 from the central computer via coupling capacitor 268.

Resistors

268, 270 and 272 provide biasing for

transistors

264 and 266, respectively.

Referring now to FIG. 15, the X channel connections for a 64 line plasma display are illustrated. The glass plasma panel shown generally at 302 has plated thereon a plurality of integrated circuit chips 304 through 3l8which comprise the resistor-diode insulation circuitry described with reference to FIG. 10 for a four line system. FIG. 15 illustrates the reduction in external connections to the plasma panel required by the present system, with all writing, sustaining and erasing voltages being received by 16 lines rather than by 128 lines as in the prior art. The alternating I40 volt sustainer voltage is applied to lines X1 through X64 via eight sustainer switches S through S each of which switches couples the sustainer voltage to eight lines.

As described with respect to FIG. 10, when no writing or erasing voltages are applied, lines 320 through 334 couple the volt sustainer to the isolation circuits 304 through 318, respectively. When writing pulses are selectively applied. via the Write/Erase switches W through W to lines 320 through 334, respectively, writing or erasing is accomplished. For example, to write on line X,, a writing pulse is applied through switch W, via line 320 to the isolation network 304. With a writing pulse of 200 volts, this voltage is coupled via resistor 336 to line X which is connected between resistor 336 and diode 338 to provide a direct path for the writing voltage to line X Sustainer switch S is open while switches S through S are closed, thereby shorting lines X through X back to the sustainer generator at l40 volts, leaving 200 volts on line X. only. The back biasing of diode 338 provides isolation of the 140 volts sustainer from the 200 volt writing pulse. A similar 200 volt writing pulse is, of course, applied to the corresponding Y line (not shown) when writing is effected, the connections for Y through Y being identical to those for X through X with a waveform correspondence as illustrated by FIG. 8.

Referring now to FIG. 16, the X and Y grid matrix for a four line plasma panel, the X axis of which is described with reference to FIG. 10, is shown generally at 350. Lines 1 through 4 of the X matrix are plated on a glass substrate 30, and the corresponding Y axis lines 1 through 4 are plated on a glass substrate 32 which is isometrically illustrated in FIG. 2. The X and

Y isolation networks

352 and 354 are also plated on

glass substrates

30 and 32, respectively, and all the circuit connections required to the panel, 2 VIV, where N is the number of panel lines per axis, are shown as

points

356, 358, 360 and 362 for the X axis grid and 364, 366, 368 and 370 for the Y axis grid. It may be observed that the X and Y axis circuitry is identical and that whatever voltage is applied positively on the X axis grid is also applied negatively on the Y axis grid, thereby producing a composite absolute voltage between the X and Y axis grids of twice any individually applied voltage to any one line in either the X or Y axis grids as may be observed with reference to FIG. 8, in which the absolute values of the write and erase pulsesare 400 volts and 250 volts, respectively, with an absolute sustainer voltage of 280 volts.

As described with reference to FIG. 10, writing and erasing voltages are coupled from the Write/Erase switches to the isolation network 352 for the X axis via

lines

372 and 374, and the sustainer voltage is coupled to the isolation network 352 from the X axis sustainer switches via

lines

376 and 378. In a similar manner, the writing and erasing voltages are coupled to the Y axis isolation network 354 from the Y Write/Erase switches via

lines

380 and 382, and the Y axis sustainer voltage is coupled to isolation network 354 from the Y axis sustainer switches via

lines

384 and 386.

The plasma between

glass plates

30 and 32 is ionized by the voltage developed between the X and Y axis grid spaced intersection points by virtue of the voltage capacitively built up therebetween and the resultant dis charge through the plasma as previously described. Of course, this simplified plasma panel of four lines by four lines is illustrative only and in practice, a 256 by 256 line matrix is preferably employed.

While particular embodiments of the invention have been shown and described, various modifications thereof will be apparent to those skilled in the art. For example, the circuitry of the present invention may be effectively employed in displays of the electroluminescent type, the light emitting diode matrix type and in displays in which the reflectivity of a surface is controlled. Therefore, it is not intended that the invention be limited to the disclosed embodiments or details thereof and departures may be made therefrom within the spirit and scope of the invention as defined in the appended claims.

What is claimed is:

l. A visual display system in which a plurality of illuminated areas are created by the crossing of wire grids comprising:

switching means for controlling the generated dissustaining means for maintaining the display once generated;

means for isolating said sustaining means from said switching means such that sustaining occurs independently of signals switched by said switching means;

writing means for generating a voltage sufficient to cause illumination of selected areas of said display, said writing voltage being greater than said sustaining voltage; and

means included in said switching means for enabling the simultaneous application of said writing voltage sequentially to selected crossings of said wire grid while sustaining voltage is applied to other crossings of said wire grid;

said sustaining voltage and said writing voltage being isolated one from the other.

2. A visual display system in accordance with claim 1 wherein each of said switching means is coupled to a plurality of wires of said grid and wherein the number of said switching means is less than the number of intersections of said wire grids.

3. A visual display system in accordance with claim 2 wherein said wire grids intersect at N points and wherein the number of control swit ches required for said N points is substantially 4 Vfi.

4. A visual display system in accordance with claim 3 wherein said sustaining voltage and said writing voltage are alternating voltages.

5. A visual display system in accordance with claim 3 wherein said sustaining voltage and said writing voltage are pulsed dc voltages.

6. A visual display system in accordance with claim 3 wherein said display is of the capacitively coupled type wherein said wire grids are on opposite sides of an illuminatable substance and cause a capacitive discharge at selective locations through said illuminat'able substance.

7. A visual display system in accordance with claim 6 further comprising;

means for generating an erasing voltage for selectively erasing portions of said visual display wherein said erasing voltage is applied through the same switches through which said writing voltage is applied to said display.

8. A visual display system in accordance with claim 7 wherein the magnitude of said erasing voltage is less than the magnitude of said writing voltage and more than the magnitude of said sustaining voltage.

9. A capacitively coupled plasma display system of the type in which two wire grids are plated on the surfaces of two dielectrics and are separated from each other by a fixed distance with an ionizable gas therebetween comprising:

writing means for generating a voltage sufiiciently high to cause ionization with resultant glow discharge of said ionizable gas;

sustaining means for generating a voltage sufficiently high to maintain said glow discharge once initiated by said writing voltage;

means for noninductively coupling said writing voltage and said sustaining voltage to selected areas of said plasma display in accordance with matrix selection data from said first mentioned means in both an X channel and a Y channel;

said X channel corresponding to one of said conductive grids and said Y channel corresponding to the other of said conductive grids;

said X grid and said Y grid crossing in matrix form;

means coupled to said switching means for isolating said writing voltage and said sustaining voltage one from the other prior to coupling to said conductive grid networks;

the source of said matrix selection data comprising a digital computer; and

said isolation network comprising a plurality of diode and resistive networks for cyclically coupling said writing and sustaining voltages to certain of said plasma areas while simultaneously blocking said writing voltage from other of said plasma areas.

10. The combination of claim 9 further comprising:

means for noninductively controlling said writing voltage with said sustaining voltage such that said writing voltage is selectively applied to areas of said visual display to produce visual indication at said areas without loss of said sustaining voltage at areas of said visual display at which said writing voltage is not applied.

11. A visual display system in accordance with claim 10 wherein said means for controlling includes;

means for isolating said sustaining voltage from said writing voltage.

12. A visual display system in accordance with claim 11 wherein said writing voltage are alternating signals.

13. In combination:

first and second sets of conductors;

means for producing light at a plurality of locations, said locations being situated at intersections of conductors of said first set of conductors with conductors of said second set of conductors;

a first set of diodes, said first set of diodes being coupled to said conductors of said first and second sets of conductors;

a plurality of switch means coupled to said first set of diodes for controlling which of said light producing means produce light;

means for generating a sustaining voltage; and

a second set of diodes, said second set of diodes being coupled to said sustaining voltage generating means and to said first and second sets of conductors.

14. The combination of claim 13 wherein said switch means are less in number than the total number of conductors of said first and second sets of conductors.

15. The combination of claim 14 wherein the number of said switch means per set of conductors is substantially two times the square root of the number of conductors in said set of conductors.

16. A computer controlled display device comprising in combination:

an array of crosspoint cells defined by respective row and column conductors;

a source of alternating polarity sustaining signals;

a plurality of diodes, said diodes having first and second terminals, said first terminals of each of said diodes being coupled to separate ones of said row and column conductors;

a plurality of first switch means, said first switch means being coupled to said second terminals of said diodes, said switch means conducting when data displayed on said display device is being sustained;

a source of writing signals, said writing signals causing selected ones of said crosspoint cells to emit light when said writing signals are coupled to selected ones of said row and'column conductors;

a plurality of second switch means, said second switch means coupling said writing signals to selected ones of said row and column conductors when said second switch means are conducting; and

means for operating said first and second switch means in response to signals from said computer.

17. The combination of claim 16 wherein said array of crosspoint cells comprises a plasma display panel.

18. The combination of claim 17 further comprising a plurality of resistors, one of said resistors being connected between each of said second terminals of said diodes and said first switch means.

Claims

2. A visual display system in accordance with claim 1 wherein each of said switching means is coupled to a plurality of wires of said grid and wherein the number of said switching means is less than the number of intersections of said wire grids.
3. A visual display system in accordance with claim 2 wherein said wire grids intersect at N2 points and wherein the number of control switches required for said N2 points is substantially 4 Square Root N.
4. A visual display system in accordance with claim 3 wherein said sustaining voltage and said writing voltage are alternating voltages.
5. A visual display system in accordance with claim 3 wherein said sustaining voltage and said writing voltage are pulsed dc voltages.
6. A visual display system in accordance with claim 3 wherein said display is of the capacitively coupled type wherein said wire grids are on opposite sides of an illuminatable substance and cause a capacitive discharge at selective locations through said illuminatable substance.
7. A visual display system in accordance with claim 6 further comprising; means for generating an erasing voltage for selectively erasing portions of said visual display wherein said erasing voltage is applied through the same switches through which said writing voltage is applied to said display.
8. A visual display system in accordance with claim 7 wherein the magnitude of said erasing voltage is less than the magnitude of said writing voltage and more than the magnitude of said sustaining voltage.
9. A capacitively coupled plasma display system of the type in which two wire grids are plated on the surfaces of two dielectrics and are separated from each other by a fixed distance with an ionizable gas therebetween comprising: writing means for generating a voltage sufficiently high to cause ionization with resultant glow discharge of said ionizable gas; sustaining means for generating a voltage sufficiently high to maintain said glow discharge once initiated by said writing voltage; means for noninductively coupling said writing voltage and said sustaining voltage to selected areas of said plasma display in accordance with matrix selection data from said first mentioned means in both an X channel and a Y channel; said X channel corresponding to one of said conductive grids and said Y channel corresponding to the other of said conductive grids; said X grid and said Y grid crossing in matrix form; means coupled to said switching means for isolating said writing voltage and said sustaining voltage one from the other prior to coupling to said conductive grid networks; the source of said matrix selection data comprising a digital computer; and said isolation network comprising a plurality of diode and resistive networks for cyclically coupling said writing and sustaining voltages to certain of said plasma areas while simultaneously blocking said writing voltage from other of said plasma areas.
10. The combination of claim 9 further comprising: means for noninductively controlling said writing voltage with said sustaining voltage such that said writing voltage is selectively applied to areas of said visual display to produce visual indication at said areas without loss of said sustaining voltage at areas of said visual display at which said writing voltage is not applied.
11. A visual display system in accordance with claim 10 wherein said means for controlling includes; means for isolating said sustaining voltage from said writing voltage.
12. A visual display system in accordance with claim 11 wherein said writing voltage are alternating signals.
13. In combination: first and second sets of conductors; means for producing light at a plurality of locations, said locations being situated at intersections of conductors of said first set of conductors with conductors of said second set of conductors; a first set of diodes, said first set of diodes being coupled to said conductors of said first and second sets of conductors; a plurality of switch means coupled to said first set of diodes for controlling which of said light producing means produce light; means for generating a sustaining voltage; and a second set of diodes, said second set of diodes being coupled to said sustaining voltage generating means and to said first and second sets of conductors.
14. The combination of claim 13 wherein said switch means are less in number than the total number of conductors of said first and second sets of conductors.
15. The combination of claim 14 wherein the number of said switch means per set of conductors is substantially two times the square root of the number of conductors in said set of conductors.
16. A computer controlled display device comprising in combination: an array of crosspoint cells defined by respective row and column conductors; a source of alternating polarity sustaining signals; a plurality of diodes, said diodes having first and second terminals, said first terminals of each of said diodes being coupled to separate ones of said row and column conductors; a plurality of first switch means, said first switch means being coupled to said second terminals of said diodes, said switch means conducting when data displayed on said display device is being sustained; a source of writing signals, said writing signals causing selected ones of said crosspoint cells to emit light when said writing signals are coupled to selected ones of said row and column conductors; a plurality of second switch means, said second switch means coupling said writing signals to selected ones of said row and column conductors when said second switch means are conducting; and means for operating said first and second switch means in response to signals from said computer.
17. The combination of claim 16 wherein said array of crosspoint cells comprises a plasma display panel.
18. The combination of claim 17 further comprising a plurality of resistors, one of said resistors being connected between each of said second terminals of said diodes and said first switch means.