US3657477A - Arrangement for encoding intelligence - Google Patents

Arrangement for encoding intelligence Download PDF

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Publication number
US3657477A
US3657477A US227344A US3657477DA US3657477A US 3657477 A US3657477 A US 3657477A US 227344 A US227344 A US 227344A US 3657477D A US3657477D A US 3657477DA US 3657477 A US3657477 A US 3657477A
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Prior art keywords
counting
elements
output
chain
pulse
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Expired - Lifetime
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US227344A
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Inventor
Kurt Ehrat
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OMNISEC AG TROCKENLOOSTRASSE 91 CH-8105 REGENSDORF SWITZERLAND A Co OF SWITZERLAND
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GERTAG AG
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Assigned to OMNISEC AG, TROCKENLOOSTRASSE 91, CH-8105 REGENSDORF, SWITZERLAND, A CO. OF SWITZERLAND reassignment OMNISEC AG, TROCKENLOOSTRASSE 91, CH-8105 REGENSDORF, SWITZERLAND, A CO. OF SWITZERLAND ASSIGNMENT OF ASSIGNORS INTEREST. Assignors: GRETAG AKTIENGESELLSCHAFT
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
    • H04L9/065—Encryption by serially and continuously modifying data stream elements, e.g. stream cipher systems, RC4, SEAL or A5/3
    • H04L9/0656—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher
    • H04L9/0662—Pseudorandom key sequence combined element-for-element with data sequence, e.g. one-time-pad [OTP] or Vernam's cipher with particular pseudorandom sequence generator

Definitions

  • a code pulse generator comprising a counting pulse supply, a plurality of binary elements constituting at least one counting chain, an output to each of said binary elements, at least one mixing circuit arrangement, an output to the mixing circuit arrangement, and a plurality of inputs to said mixing circuit arrangement, the number of said inputs being substantially equal to the number of elements in the counting chain and each such input being controllable by a respective output of said binary elements
  • the mixing circuit including means for converting the state of all its inputs into a predetermined code program appearing at its output, the input of the individual consecutive elements of the counting chain being connected with said counting pulse supply so as to alter its state from counting pulse to counting pulse, and the input of the individual consecutive elements of the counting chain being connected further with the output of every previous element by logic gates which serve to interrupt the changing of the state of any particular stage only when by arriving of a counting pulse the state of all previous elements is 1", and the mode of action of the counting chain being such as to alter from counting step to counting step more than the half of all the elements
  • the various pulses or combinations thereof are first mixed at the transmitter with a highly random sequence of corresponding pulses or combinations thereof knownas the code pulses or code pulse combinations, the intelligence then being transmitted in the form of the new pulses produced by the mixing.
  • the original intelligence is restored by means of a second identical sequence of code pulses.
  • code pulse sequences must be produced in identical form at transmitter and receiver, and identical code pulse generators are accordingly used at the transmitter and at the receiver.
  • the code pulse sequences must meet special requirements to ensure that there is no chance of the intelligence being tapped by unauthorised persons.
  • the period length of the code pulse sequence i.e., the time during which there is no repetition of the code pulse sequence must be large enough to ensure that there is no chance of the complete code pulse program period being performed completely in a useful time, even using very high-speed electronic means.
  • the distribution of the pulses within the code pulse sequence must as far as possible be random (statistically distributed).
  • the usual way to ensure a long code pulse period is to use arrangements like counters i.e., serial arrangements comprising elements, such as disc cams; the various elements are so stepped on in dependence upon one another that the arrangement passes through all the possible position combinations of the various elements before retuming to its initial state.
  • This can be achieved, for instance, in the case of mechanical arrangements, by a number of gears which engage with one another and which have prime numbers of teeth.
  • the condition can be met by a decade counter.
  • the decade counter although of very simple construction, has the disadvantage that the higher-order stages (elements) change their position only relatively seldom.
  • a conventional counter therefore does not meet the second requirement just outlined i.e., that the state i.e., the position of the various stages of the counter should vary as much as possible from counting step to counting step.
  • a code pulse generator comprising a plurality of binary elements constituting at least one counting chain, an output to each of said binary elements, at least one mixing circuit arrangement, an output to the mixing circuit arrangement, and a plurality of inputs to said mixing circuit arrangement, the number of said inputs being substantially equal to the number of elements in the counting chain and each such input being controllable by a respective output ofsaid binary elements, the mixing circuit arrangement being arranged to deliver at its output a reproducible code pulse programme dependent upon the state of all the inputs of the mixing circuit, and the individual consecutive elements of the counting chain being. arranged so to interact that, from counting step to counting step, the state of, on the average, one half of all the elements of the counting chain alters and the counting chain passes through all the possible position combinations before returning to its initial position.
  • an arrangement for encoding intelligence in pulse form comprising a transmitting station and a receiving station, and, at each such station the code pulse generator just indicated.
  • FIG. 1 is a block diagram illustrating the basic arrangement of an intelligence transmission system comprising provision for encoding
  • FIGS.- 2, 3 and 4 are block diagrams illustrating three respective embodiments of counter-like circuit arrangements according to this invention.
  • FIG. I which is in block schematic form, illustrates two stations which co-operate as transmitter and receiver and via which encoded intelligence is transmitted.
  • a transmitter 10 or a receiver 12 for instance, a teleprinter of known kind, for transmitting and receiving intelligence in the form of uncoded pulses.
  • the output of the transmitting teleprinter It) delivers to a mixer 14, the output of which is connected to a transmission channel symbolized by an arrow 16.
  • the transmission channel can be, for instance, a wire circuit or a cable circuit or a radio circuit.
  • the transmission channel delivers to a mixer 18, the output of which supplies the receiver teleprinter 12.
  • themixers 14 and 18 are supplied by code pulse generators 20' and 22.
  • the intelligence pulse trains produced by the transmitting teleprinter 10 are mixed in the transmitter mixer 14 with the code pulse sequence produced by the generator 20.
  • the resulting encoded pulse sequence is transmitted over the channel 16, then mixed in the receiving mixer 18 with an identical pulse train sequence produced by the generator 22 to restore the intelligence pulses which operate the receiver teleprinter 12.
  • the code pulse generators 20, 22 comprise a mixing and computing circuit 24 (at the. transmitter) and 26 (at the receiver) and a counting chain 28 (at the transmitter) and 30 (at the receiver).
  • Each counting chain comprises a relatively large number (n) of discrete counter stages 32, the output of each such stage being connected to an input of the mixing and computing circuit.
  • the number of mixing circuit inputs is the same as the number of counter stages and is, with advantage, greater than 20.
  • the counting period is 2 E 10.
  • the interaction between consecutive members of the counting chain is preferably such that the variation of the states arising out of the condition of the outputs of the various members is as large as possible from counting step to counting step i.e., the state of each output changes as often as possible between the O and the 1 states.
  • the variation of the state of the various outputs is so distributed that, even after a relatively reduced number of counting steps, the rate of occurrence of the 0" and 1 states appearing consecutively at each output is, on the average, equal.
  • the counting steps are triggered by counting pulses supplied through connections 34 and 36.
  • FIG. 2 illustrates an embodiment of a counting chain according to this invention.
  • the counting chain comprises flipflop triggers (0,1,2,3,4, n); in order not to overload FIG. 2, only the first five counting stages 100, 102, 104, 106 and 108 are shown.
  • Control is by means of a counting pulse supplied through a connection 110.
  • the counting pulse triggers the counting chain element into the opposite position and is supplied to the element directly and to the elements 102- 108 via other logical circuit elements 126, 128, 130, 132, 134, 136 and 138.
  • Outputs 112, 114, 116, 118, of the elements 100-108 extend to a mixing and computing circuit arrangement (not shown) of the kind shown in FIG. 1.
  • each counting chain element acts, by way of one delay device 124 per element, upon the immediately following higher counting chain element.
  • the delay circuit arrangements 124 ensure that the counting pulse has completely decayed before the new state of the previous element reaches the immediately higher element.
  • the counting chain operates as follows:
  • the output of any given counting stage, for instance, of the stage 104, is supplied, together with the counting pulse and via AND-gates 130 and 136, to the input of the immediately following counting element 106.
  • the counting pulse delivered by the connection 110 acts on one input of the AND-gate 130.
  • the second and inverting input of the AND-gate 130 is supplied from the output of a preceding second AND-gate 136.
  • One input thereof is connected by way of a delay circuit arrangement 124 to the output of the immediately previous stage 104 of the counting chain.
  • the second input of the AND-gate 136 is connected to the output of the AND-gate 134 associated with the immediately lower stage.
  • the counter 106 is triggered by every counting pulse until inversion at the second input of the AND-gate 130 produces a pulse.
  • the various counting stages 100-108 are continuously triggered by the counting pulse between and 1", and this continuous triggering of any stage is interrupted only at the time when all the preceding stages are in a given state the 1 state in FIG. 2.
  • This is also the state in which there would be a carry-over at all the preceding places in a conventional binary counter; for instance, if the counting stages 100, 102, 104 and 106 are at 1, a pulse (1 state) is produced at the output of the AND-gate 138 and, because of the inversion of the corresponding input of the AND-gate 132, prevents the counting pulse from reaching the counting element 108. Therefore, the output states of the counting elements are varied as follows:
  • FIG. 3 illustrates another embodiment of a counting chain in which the various flip-flop triggers (0,1,2,3,4 n) are in series with one another and the number of outputs is equal to the number of chain elements.
  • the various flip-flop triggers (0,1,2,3,4 n) are in series with one another and the number of outputs is equal to the number of chain elements.
  • the first five counting stages 210, 212, 214, 216 and 218 are shown. Any higher stage, for instance, the nth stage, changes over in dependence upon the state of the two preceding stages i.e., of the (n-l) th and (rt-2) th stage in the expulse passes seriatim through all the elements of the chain, and so the various chain elements are triggered consecutively in time, whereas in the arrangement illustrated in FIG. 2 all the elements of the chain are triggered simultaneously.
  • the counting pulse sequence frequency provided by an arrangement of the kind shown in FIG. 3 is therefore much lower than that provided by an arrangement of the kind shown in FIG. 2.
  • Each counting element has a left-hand output and a right-hand output, the states of which are always complementary to one another i.e., when the left-hand output is at, for instance, 0", the right-hand output is at l,” and so on. It will be assumed that any counting element is in the 1" state when its right-hand output is in the 1" state. Also, matters are so arranged that the state of any counting element changes whenever the state at the input changes from 0 to 1".
  • the righthand outputs of the elements 210, 212, 214, 216, 218 are connected to the outputs 220, 222, 224, 226 and 228 of the chain.
  • the 0th element 210 is actuated directly by the counting pulse arriving via the connection 230.
  • a pulse acts via a connection 232 on the input of the element 212.
  • the output thereof is connected via an OR-gate 234 to the input of the immediately following element 214.
  • the second input of the OR- gate 234 is connected to the right-hand output of the element 210. Consequently, the element 214 is triggered either when the element 212 changes from 0" to 1 or when the element 210 changes from 1 to 0.
  • the element 214 is therefore not triggered only in the case in which the previous element 212 changes from 1 to 0" and the element 210 changes from 0" to 1".
  • the program of the states of a five-element counting chain of the kind illustrated in FIG. 3 is therefore as follows:
  • the two complementary outputs of the various elements of the counter are not connected directly to the counting chain outputs 320, 322, 324, 326 and 328; instead, AND-gate pairs 330, 332; 334, 336; 338, 340; 342, 344 and 346, 348 are connected to the last-mentioned outputs.
  • the second inputs of these AND-gates are controlled by a flip-flop trigger 350, the input of which is controlled, by way of an AND-gate 352, by the counting pulse supplied through a connection 354 and also by the output pulse of a single-state multi-vibrator 356, which is controlled, by way of an OR-gate 358, by the two complementary outputs of the last element (not shown) of the counting chain.
  • the trigger 350 is changed over continuously by the counting pulse by way of the AND-gate 352. Consequently, a pulse from the trigger 350 is present alternately at each counting pulse at the corresponding inputs either of the ANDgates 330, 334, 338, 342 and 346 or of the AND-gates 332, 336, 340, 344, and 348. Consequently, the left-hand and right-hand of the two complementary outputs of the elements 310-318 are connected alternately to the outputs 320-328. In other ample. Since the arrangement is a series one, the counting words, the outputs of the counter elements are inverted at each consecutive counting step. The multi-vibrator 356 ensures that this inversion process is interrupted for one counting step when the highest element of the counter changes from to 1", or from 1 to 0. In an arrangement of this kind, the pulse program at the outputs is as follows:
  • a code pulse generator comprising a counting pulse supply, a plurality of binary elements constituting at least one counting chain, an output to each of said binary elements, at least one mixing circuit arrangement, an output to the mixing circuit arrangement, and a plurality of inputs to said mixing circuit arrangement, the number of said inputs being substantially equal to the number of elements in the counting chain and each such input being controllable by a respective output of said binary elements
  • the mixing circuit including means for converting the state of all its inputs into a predetermined code program appearing at its output, the input of the individual consecutive elements of the counting chain being connected with said counting pulse supply so as to alter its state from counting pulse to counting pulse, and the input of the individual consecutive elements of the counting chain being connected further with the output of every previous element by logic gates which serve to interrupt the changing of the state of any particular stage only when by arriving of a counting pulse the state of all previous elements is 1 and the mode of action of the counting chain being such as to alter from counting step to counting step more than the half of all the elements
  • a code pulse generator comprising a counting pulse supply, a plurality of binary elements constituting at least one counting chain, an output to each of said binary elements, at least one mixing circuit arrangement, an output to the mixing circuit arrangement, and a plurality of inputs to said mixing circuit arrangement, the number of said inputs being substantially equal to the number of elements in the counting chain and each such input being controllable by a respective output of said binary elements, the mixing circuit including means for converting the state of all its inputs into a predetermined code program appearing at its output, the input of the individual consecutive e ements of the counting chain being connected over an OR- gate with the output of the previous element and with the complementary output of the element before said previous element, and the first element of the counting chain being connected with said counting pulse supply, the individual elements changing its state with every counting pulse excepted when the previous element changes over from the state 1 to the 0" state, and the mode of action of the counting chain being such as to alter from counting step to counting step more than the half of all the
  • a code pulse generator comprising a counting pulse supply, a plurality of binary elements constituting at least one counting chain, an output to each of said binary elements, at least one mixing circuit arrangement, an output to the mining circuit arrangement, and a plurality of inputs to said mixing circuit arrangement, the number of said inputs being substantially equal to the number of elements in the counting chain and each such input being controllable by a respective output of said binary elements
  • the mixing circuit including means for converting the state of all its inputs into a predetermined code program appearing at its output, the first element of the counting chain being connected to said counting pulse supply and the input of the consecutive elements being connected to the output of the previous element so as to form an ordinary binary counter, and means for inverting the outputs of said elements from counting step to counting step and for suppressing such inversion when the highest element changes its state, the mode of action of the counting chain being such as to alter from counting step to counting step more than the half of all the elements of the counting chain and to pass the counting chain through all the possible position

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
  • Transmission And Conversion Of Sensor Element Output (AREA)
  • Radar Systems Or Details Thereof (AREA)
US227344A 1961-10-02 1962-10-01 Arrangement for encoding intelligence Expired - Lifetime US3657477A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CH1140961A CH392617A (de) 1961-10-02 1961-10-02 Anordnung zur Verschlüsselung von in Impulsform übertragenen Nachrichten

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US3657477A true US3657477A (en) 1972-04-18

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US (1) US3657477A (de)
BE (1) BE623086A (de)
CH (1) CH392617A (de)
DE (1) DE1234790B (de)
GB (1) GB973536A (de)
NL (1) NL283787A (de)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4114138A (en) * 1976-08-23 1978-09-12 Bell Telephone Laboratories, Incorporated Selective calling circuit
US4991209A (en) * 1988-10-17 1991-02-05 Grumman Aerospace Corporation Random local message encryption

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL225293A (de) * 1957-02-26
NL244086A (de) * 1958-12-10

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
R. K. Richards, Arithmetic Operations in Digital Computers, pp. 193 208 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4114138A (en) * 1976-08-23 1978-09-12 Bell Telephone Laboratories, Incorporated Selective calling circuit
US4991209A (en) * 1988-10-17 1991-02-05 Grumman Aerospace Corporation Random local message encryption

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BE623086A (de)
GB973536A (en) 1964-10-28
CH392617A (de) 1965-05-31
DE1234790B (de) 1967-02-23
NL283787A (de)

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Owner name: OMNISEC AG, TROCKENLOOSTRASSE 91, CH-8105 REGENSDO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:GRETAG AKTIENGESELLSCHAFT;REEL/FRAME:004842/0008

Effective date: 19871008