US3648262A - Memory arrangement - Google Patents

Memory arrangement Download PDF

Info

Publication number
US3648262A
US3648262A US836496A US3648262DA US3648262A US 3648262 A US3648262 A US 3648262A US 836496 A US836496 A US 836496A US 3648262D A US3648262D A US 3648262DA US 3648262 A US3648262 A US 3648262A
Authority
US
United States
Prior art keywords
lines
memory system
interconnected
line
control lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US836496A
Other languages
English (en)
Inventor
Hermann Kadow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Corp filed Critical Siemens Corp
Application granted granted Critical
Publication of US3648262A publication Critical patent/US3648262A/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/017545—Coupling arrangements; Impedance matching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/06—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
    • G11C11/06007—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element using a single aperture or single magnetic closed circuit
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits

Definitions

  • ABSTRACT A memory system having a plurality of control lines, to individual lines of which impulses from a source of constant current may be selectively applied, each line being provided with inductive feed, and having a temiination at the feed end thereof at least corresponding approximately with its wave resistance, the other ends of the parallel control lines being interconnected at least in groups with return flow being effected over other of associated lines whereby such connecting points are not led to a ground or other specific return line to improve the characteristics of the control lines as wave conductors and shorten the buildup processes associated with the return current, and thereby achieve an increase in operating speeds.
  • Maximum operating speeds achievable by memory arrangements or systems depend not only on the switching time of the memory elements but to a very important extent also upon the conduction characteristics of the control lines.
  • a predetermined wave resistance will be associated with each of such lines and by tenninating the lines with a resistance corresponding to the wave resistance, instead of a direct connection to a common ground return line or the like, a considerable reduction of the overswing of the control impulses can be achieved.
  • the invention is directed to the problem of effecting measures to shorten the buildup process and improve the wave conduction behavior of the control lines of a memory system and thereby effect an increase in the operating speed thereof.
  • the invention thus is directed to a memory system utilizing a plurality of control lines selectively and individually subjected to impulses from a source of constant current, with each of the lines being provided with inductive feed and having a termination at the feed or supply end thereof at least corresponding approximately to its wave resistance, the other ends of the parallel control lines being interconnected at least in groups, with return flow being effected over other of the associated lines whereby the connecting points of a group are not connected directly to a ground or other specific return line.
  • FIG. I schematically presents a circuit diagram of only that portion of a memory arrangement necessary for an understanding of the invention
  • FIG. 2 is a similar circuit diagram illustrating a modification of the circuit of FIG. 1;
  • FIG. 3 is a similar circuit diagram illustrating another modification of the circuit of FIG. 1.
  • reference numerals L1-L7 designate respective control lines of a memory system as for example, row lines extending in parallel relation and associated with a plurality of storage elements, for example magnetic ring cores having an approximately rectangular hysteresis loop with the lines Ll-L7 thus forming control lines in one coordinate of the matrix memory.
  • control lines as viewed in FIG. I, are illustrated as being interconnected while the ends at the left side of the Figure are connected at the terminals Kl-K7 to individually grounded resistances Rl-R7, the resistance values of which correspond as close as possible to the wave resistance of the respective associated control circuits formed thereby.
  • the terminals Kl-K7 are also connected over a selector system A, for effecting selection of a particular control circuit and connection thereof to an impulse generator G having constant current characteristics.
  • selector installations for the connection of unipolar or bipolar impulses are known, as are the corresponding impulse generators, in view of which it is believed unnecessary to present additional details with respect thereto.
  • the transformer U and switch S is representative of similar connections with the other control lines and it shall be assumed that the closed switch S indicates that the control circuit L4 has been selected for connection with the impulse generator G.
  • the partial currents flow in return direction on the adjacent lines, namely a current a.l in the two immediately adjacent lines, a current b.l next two successive lines in outward direction, etc.
  • the partial currents depend only on the resistances of the control circuit and the secondary winding of the transformer U, and thus they are at least approximately equal to one another. It will also be kept in mind that memory systems, for example, matrix memories generally contain a considerably greater number of parallel control lines than that illustrated in the Figure.
  • the current division takes place in relation to the partial wave resistances, dependent substantially on the conductor lengths or distances.
  • the wave resistance with respect to the two nearest neighboring lines thus is the lowest and increases for the lines further away.
  • Each of such wave lines is terminated with a resistance RJZR/Z, but as the wave resistance of the waveline consisting of the control circuit involved in its two neighboring lines is only slightly larger than R a considerably faulty termination exists which results in the return current in the nearest lines exhibiting a strong overswing, which in turn is transferred to the read line and possibly may cause disturbances of the read signal.
  • the wave conduction characteristics of the control circuits parallel to one another can be further improved by disposing the lines in two or more groups which are separated from one another, instead of providing a common connection of all ends of the control circuits remote from the feed.
  • grouping can be made, for example as illustrated in FIG. 2, in such a manner that a first group contains all lines with even numbers and a second group contains all lines with odd numbers.
  • Another possibility for example, resides in the consolidation of every fourth line, etc., as illustrated in FIG. 3.
  • a memory system comprising a plurality of control lines, to individual lines of which impulses from a source of constant current may be selectively applied, with each line being provided with an inductive feed and having a tennination at the feed end thereof at least corresponding approximately with its wave resistance, the other ends of the parallel control lines being interconnected, at least in groups, with return flow being effected over other of said lines of the group involved whereby such connecting points are not connected to a specific ground or other return line.
  • a memory system wherein every fourth line, i.e., the first, fifth, ninth, etc. are interconnected, and the second, sixth, 10th, etc. are interconnected, etc.
  • a memory system wherein additional parallel lines are provided adjacent the outermost lines of the associated group, and connected therewith to compensate for the fact that such outermost lines are not sequentially disposed with respect to the other lines of such group.
  • parallel control lines comprise line and/or column lines of a memory matrix.
  • a memory system according to claim 5, wherein said memory elements comprise magnetic cores having an approximately rectangular hysteresis loop.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Sewage (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Insulated Conductors (AREA)
US836496A 1968-07-03 1969-06-25 Memory arrangement Expired - Lifetime US3648262A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19681774500 DE1774500B1 (de) 1968-07-03 1968-07-03 Speicheranordnung

Publications (1)

Publication Number Publication Date
US3648262A true US3648262A (en) 1972-03-07

Family

ID=5702164

Family Applications (1)

Application Number Title Priority Date Filing Date
US836496A Expired - Lifetime US3648262A (en) 1968-07-03 1969-06-25 Memory arrangement

Country Status (7)

Country Link
US (1) US3648262A (OSRAM)
BE (1) BE735607A (OSRAM)
DE (1) DE1774500B1 (OSRAM)
FR (1) FR2014492A1 (OSRAM)
GB (1) GB1264530A (OSRAM)
LU (1) LU59001A1 (OSRAM)
NL (1) NL6909593A (OSRAM)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1049099A3 (de) * 1999-03-31 2001-09-12 Siemens Aktiengesellschaft Elektronisches Gerät, insbesondere Feldgerät

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3110888A (en) * 1959-09-01 1963-11-12 Texas Instruments Inc Magnetic switching core matrices
US3436750A (en) * 1965-04-06 1969-04-01 Hollandse Signaalapparaten Bv Write and read circuit arrangement for a magnetic storage with magnetizable cores
US3439352A (en) * 1966-03-30 1969-04-15 Bell Telephone Labor Inc Magnetic wall domain shift register
US3492664A (en) * 1965-09-17 1970-01-27 Telefunken Patent Magnetic core memory
US3579209A (en) * 1968-09-06 1971-05-18 Electronic Memories Inc High speed core memory system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1264853A (fr) * 1959-08-17 1961-06-23 Sperry Rand Corp Mémoire à noyaux magnétiques

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3110888A (en) * 1959-09-01 1963-11-12 Texas Instruments Inc Magnetic switching core matrices
US3436750A (en) * 1965-04-06 1969-04-01 Hollandse Signaalapparaten Bv Write and read circuit arrangement for a magnetic storage with magnetizable cores
US3492664A (en) * 1965-09-17 1970-01-27 Telefunken Patent Magnetic core memory
US3439352A (en) * 1966-03-30 1969-04-15 Bell Telephone Labor Inc Magnetic wall domain shift register
US3579209A (en) * 1968-09-06 1971-05-18 Electronic Memories Inc High speed core memory system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1049099A3 (de) * 1999-03-31 2001-09-12 Siemens Aktiengesellschaft Elektronisches Gerät, insbesondere Feldgerät

Also Published As

Publication number Publication date
DE1774500B1 (de) 1972-01-20
GB1264530A (OSRAM) 1972-02-23
LU59001A1 (OSRAM) 1969-11-14
BE735607A (OSRAM) 1970-01-05
NL6909593A (OSRAM) 1970-01-06
FR2014492A1 (OSRAM) 1970-04-17

Similar Documents

Publication Publication Date Title
US3671948A (en) Read-only memory
US2996666A (en) Automatic test apparatus
US3648262A (en) Memory arrangement
US3110017A (en) Magnetic core memory
US3343147A (en) Magnetic core switching and selecting circuits
US3209171A (en) Pulse generator employing minority carrier storage diodes for pulse shaping
US3555511A (en) Selection matrix for fixed storage systems
US3596145A (en) Drive circuit for ferrite phase shifters
US3540015A (en) Selection circuit for core memory
GB1270211A (en) Tap changer for regulating transformers with controllable semi-conductor rectifiers
GB816345A (en) Improvements in or relating to magnetic core memory device
US3651497A (en) Dynamically terminated memory line selection scheme
US3278909A (en) Reading and writing device for use in magnetic core storages
US3415955A (en) Control arrangement for a communication switching network
US3109161A (en) Electrical selection circuits
US3435437A (en) Pulse delay control circuit
US3483536A (en) Coincident memory device with no separate inhibit or sensing line
US3546672A (en) Pulse-supplying arrangements
SU418899A1 (OSRAM)
US3558918A (en) Pulse delay control circuit using code controlled ramp voltage slope to fix delay
US3470549A (en) Common mode choke for two-dimensional memory array
US3593321A (en) Matrix storage
US3085162A (en) Electrical selector circuit arrangements
US3293639A (en) Translation circuits
GB921749A (en) Improvements in or relating to electrical circuit arrangements for translating code groups