US3540015A - Selection circuit for core memory - Google Patents

Description

N. NISSEN SELECTION CIRCUIT FOR CORE MEMORY Filed June 5, 1967 Nov. 10, 1970 -INVENTOR. NICO NISSEN BY W AGENT FIG.2

United States Patent Ofice 3,540,015 Patented Nov. 10, 1970 3,540,015 SELECTION CIRCUIT FOR CORE MEMORY Nico Nissen, Hamburg, Germany, assignor, by mesue assignments, to US. Philips Corporation, New York, N.Y., a corporation of Delaware Filed June 5, 1967, Ser. No. 643,553 Claims priority, appliclatiggn Germany, June 30, 1966,

Int. Cl. G llc 7/00 US. Cl. 340-174 2 Claims ABSTRACT OF THE DISCLOSURE The invention relates to a group selection circuit for core memories with current switches. These current switches which may be arranged in the reading and writing pulse lines can control the reading and writing current pulses which are applied to the core memory through diodes.

Each time it is desired to derive or vary the information of a memory place in a core memory, one of a plurality of wires of a coordinate in the memory core matrix is selected. A current pulse is conveyed through said wire in one direction (reading) and then in the opposite direction (writing). Thus it must be possible for a current to flow through the selection circuit in both directions. This requirement could be avoided only if two wires were used for the matrix which, however, makes the matrix more expensive and more bulky.

It is known to use transistors in selection circuits as prepared current switches, that is to say, they are already in the condition of saturation when the current pulse appears from the current pulse generator which is common for all the wires of a coordinate.

In order to reduce the number of required components, a group selection process is usually used. In this method, current switches are provided at both ends of the matrix wire. Several matrix wires are combined to form one group. These wires are decoupled from one another by diodes. Only one current switch is switched each time on on each side. Two current switches, each time one on both sides, are involved in the selection of a matrix wire.

A current pulse supplied by the current pulse source which is common for all the wires of a coordinate, produces in the matrix wire a voltage drop which is variable with time. So at least one of the two involved selection circuits must be without a fixed reference potential for which purpose a potential-free current switch is required. The potential-free switches could be avoided by replacing them by current pulse sources and avoiding a current pulse source which is common for all the wires of a coordinate. Essential drawbacks of such an arrangement are that a central adjustment of the desired current pulse amplitude is no longer possible and every current pulse source produces a considerable loss of power.

This drawback is avoided according to the invention in that the groups are coupled to a common current pulse source by transformers and for the selection of one of several transformers and consequently of the control of the current pulses supplied by the common current pulse source, transistor current switches are provided in the primary circuits of said transformers.

The invention provides a selection circuit in which the potential-free switch is replaced by a current pulse source, while a central adjustment of the desired current pulse amplitude is possible.

The invention will be described in greater detail with reference to the drawings, in which FIG. 1 shows a general selection circuit,

FIG. 2 shows an example of a core memory matrix.

In the selection circuit shown in FIG. 1, a current pulse generator ZG is provided which is common for all the wires of a coordinate. This current pulse generator is connected, through parallel-arranged transformers Tr Tr to the individual groups, for example, G of the selection circuit. Where otherwise a potential-free switch is used, now the secondary or output winding of such a transformer is provided which, because on the primary side a control by a current pulse generator occurs, becomes effective as a current pulse source for the corresponding groups G of the selection circuit. By current switches T, for example, through base-controllable transistors, in the primary circuits of the transformers Tr -Tr it is determined which of several transformers is to transmit the current pulse which is supplied by the common current pulse generator. In addition, in the secondary circuit of the transformer a diode D in series with the output winding of the transformer is essential, firstly to make the remagnetisation process in the transformer independent of the load conditions in the output circuit and, in addition, to prevent that the current pulse supplied by another transformer does not flow away partly through the output windings of the transformers which are not involved.

Together with further current switches in connection with the groups G which, however, need not be constructed so as to be potential-free when using an arrangernent according to the invention several selection circuits may be realized.

FIG. 2 shows an example of a core memory matrix:

For the reading cycle the transistor T is conductive while the transistor T is cut 011?. Then also the transistors and T are conductive while T' and T remain cut off since their emitter potential is more positive than that of the transistors T and T (T cut off). A current pulse i which flows through the transformer Tr and the transistor T is supplied by a current pulse generator I which is common for all the wires of a matrix coordinate, through a transformer TRL. The current pulse transmited to the second circuit of the transformer Tr flows through the diode -D, a matrix wire, the diode D the transistor T and the transistor T to ground, or a suitable reference point as shown in the drawing. Subsequently the transistor T is cut off and T is made conductive for the writing cycle. A writing current pulse i which flows through the transformer Tr and the transistor T is supplied by the current pulse generator I which is common for all the wires of a matrix coordinate, through the transformer TRS. The current pulse transmitted to the secondary circuit of the transformer TR flows through the diode D in the reverse direction through a matrix wire, through the transistor '1 and the transistor T to ground, or a suitable reference point as shown in the drawing.

It is reached by the transistors T and T respectively in the emitter circuit of the current switches T' T and T',,, T respectively that for each time two current switches T' T and T' T respectively a common control stage may be provided.

The diodes D prevent, during the remagnetisation of a transformer, other switches which are not involved are operated inversely.

The function of the diode D is taken over on the other side of the matrix by the diode D which is present all the same.

The maximum permissible voltage drop in the matrix wire is determined only by the maximum permissible collector-emitter voltage of the current switch transistors.

What is claimed is:

1. A coordinate selection circuit for a memory matrix having a coordinate array of groups of storage elements arrayed in rows and columns, a first current source, a second current source, a first and second plurality of transformers each having primary and secondary windings, a first plurality of transistors each completing a circuit between each primary winding of said first plurality of transformers and said first current source, a second plurality of transistors each completing a circuit between each primary winding of said second plurality of transformers and said second current source, means coupling each secondary of said first plurality of transformers to a row of said matrix, means coupling each secondary of said second plurality of transformers to a column of said matrix, the intersection of a row and column including one of said groups of storage elements, a third plurality of transistors coupling each of said rows to a reference point, a fourth plurality of transistors coupling each of said columns to a reference point, means applying a group selection signal to said first and fourth plurality of transistors for passing current through the selected group in a first direction, and means applying a group selection signal to said second and third plurality of transistors for passing current through the selected group in a second direction.

2. A coordinate selection circuit for a memory matrix having a coordinate array of groups of storage elements arrayed in rows and columns, a first current source, a second current source, a first and second pluality of transformers each having primary and secondary windings, a

first plurality of transistors each completing a circuit between each primary winding of said first plurality of transformers, said first current source and a first common point, a second plurality of transistors each completing a circuit between each primary winding of said second plurality of transformers, said second current source and a second common point, means coupling each secondary of said first plurality of transformers to a row of said matrix, means coupling each secondary of said second plurality of transformer to a column of said matrix, the intersection of a row and column including one of said groups of storage elements, a third plurality of transistors coupling each of said rows to said second common point, a fourth plurality of transistors coupling each of said columns to said first common point, means applying a group selection signal to said first and fourth plurality of transistors for passing current through the selected group in a first direction, means applying a group selection signal to said second and third plurality of transistors for passing current through the selected group in a second direction, said last named means including a first selection transistor coupled between said first common point and a reference point for selecting said first and fourth plurality of transistors, and a second selection transistor coupled between said second common point and said reference point for selecting said second and third plurality of transistors.

References Cited UNITED STATES PATENTS 2,988,732 6/1961 Vinal 340174 3,231,753 1/1966 BroWn 307885 3,275,840 9/1966 Harding 30788 STANLEY M. URYNOWICZ, JR., Primary Examiner 3 3 2 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No. 3, 540,015 Dat d November 10, 1970 Inventofls) NICCO NISSEN It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below:

Col. 2, line 45, cancel "J and insert --I line 47, cancel "transmited' and insert --trans mitted--; line 67, cancel "are"' and insert -fr0m-.

Signed and sealed this 25th day of May 1971.

(SEAL) Attest:

EDWARD M.FLETCHER,JR. WILLIAM E. SCHUYLER, J1 Attesting Officer Commissioner of Patent:

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