US3638301A - Method for manufacturing a variable capacitance diode - Google Patents

Method for manufacturing a variable capacitance diode Download PDF

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Publication number
US3638301A
US3638301A US50810A US3638301DA US3638301A US 3638301 A US3638301 A US 3638301A US 50810 A US50810 A US 50810A US 3638301D A US3638301D A US 3638301DA US 3638301 A US3638301 A US 3638301A
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layer
type
type layer
impurity concentration
substrate
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US50810A
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Shigeo Matsuura
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Hitachi Ltd
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Hitachi Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/92—Capacitors with potential-jump barrier or surface barrier
    • H01L29/93—Variable capacitance diodes, e.g. varactors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/007—Autodoping
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/037—Diffusion-deposition
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/098—Layer conversion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/145—Shaped junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/916—Autodoping control or utilization

Definitions

  • This invention relates to a method for manufacturing a variable capacitance diode, especially, to a method for manufacturing a diode having a super stepped junction.
  • a variable capacitance diode where the junction capacitance of the semiconductor PN-junction is changed by an impressed voltage of reversed direction, an abrupt change in the distribution of the impurity concentration is needed in order to obtain a large capacitance variation.
  • the types of junctions in the impurity concentration distribution are as follows; graded type, stepped type and so-called super stepped type having a high variation rate thereof and formed so as to decrease the impurity concentration away from the major junction surface.
  • the semiconductor region having low-impurity concentration formed so as to decrease the impurity concentration away from the major junction surface is not directly connected with an electrode of a super stepped junction diode, but usually, for elevating the selectivity Q of said diode, is formed to have a required thickness for the capacitance variation and connected with a semiconductor region of the same conductivity type of low resistance (high-impurity concentration).
  • an N epitaxial layer of low-impurity concentration is formed on an N type semiconductor substrate of high-impurity concentration, and a high concentration N layer is diffused or an N epitaxial layer is grown on the N epitaxial layer, and an opposite conductivity tube P layer is diffused.
  • autodoping from the N type semiconductor substrate is caused in the coming heat treatment and the N type impurity concentration of the N epitaxial layer becomes too high, the abrupt change in the impurity concentration distribution and the quantity thereof are restricted, and the capacitance variation and quantity thereof is, therefore, unable to be enlarged more than a certain degree.
  • An object of this invention is to provide an improved variable capacitance diode.
  • Another object of this invention is to obtain a super stepped junction which is able to decrease the effect of autodoping by improving above-mentioned points.
  • a feature of this invention involves initially forming a lowimpurity concentration layer of an opposite conductivity type to the desired conductivity type for a super stepped junction and then heating the layer of said reversed conductivity type to cause autodoping from said layer and a high-impurity concentration layer adjoining to said layer of said reversed conductivity type, whereby the layer of the reversed conductivity type is converted to that of the desired conductivity type.
  • FIGS. la through 1d are cross-sectional views of the essential part of a semiconductor body in each manufacturing step for explaining a manufacturing process for a variable capacitance diode according to this invention
  • FIGS. 2a through 2d are charts for showing the distribution of the impurity concentration in the semiconductor body in each step corresponding to FIGS. la through 1d;
  • FIG. 3 shows a cross-sectional view of a variable capacitance diode manufactured by the method explained in FIGS. la through 1d;
  • FIGS. 4a through 4d are cross-sectional views of a semiconductor body in each manufacturing step for explaining another method for manufacturing a variable capacitance diode according to this invention.
  • EXAMPLE I A method for manufacturing a variable capacitance diode according to this invention is described in conjunction with FIGS. Ia through ld, FIGS. 2a through 2d and FIG. 3.
  • Said P type layer 2 is formed by a conventional epitaxial growing technique by thermal decomposition of inorganic or organic silane.
  • the distribution of impurity concentration in the silicon body thus produced is shown in FIG. 2a wherein the axis of abscissas illustrates the impurity concentration N- and P-type impurities and the axis of coordinates illustrates the distance from the surface of the body.
  • the N type substrate has a specific resistance of not more than about 0.02fl-cm., in other words, an impurity concentration of not less than 2X10 atoms/cmf and the P epitaxial layer has a specific resistance of 0.5 to 3.00 -cm, in other words, an impurity concentration of about 3X10 to 4X10 atoms/cm. and thickness of 1.0 to 5.0a.
  • an antimony doped silicon substrate having the specific resistance of 0.005(I-cm. was used and a boron doped epitaxial silicon layer of about 3 thickness and with specific resistance of about lO-cm. was formed on the substrate by thermally decomposing silicon tetrachloride at about 1,200 C. for 2 to 3 minutes.
  • said P type layer 2 is the layer which is to be compensated by auto-doping N-type impurities from the N substrate 1 and an N type silicon layer of low resistance (high-impurity concentration) formed in the following step B and to be converted to N type layer when a super stepped junction in this example is obtained.
  • an N-type layer 3 of low resistance (or high-impurity concentration) 3 is formed at the surface of said P type layer 2 by conventional impurity diffusing techniques, or epitaxially growing techniques as shown in FIG. lb.
  • the N type layer has a specific resistance of 0.6 to 0.001 O-cm, or an impurity concentration of about 10 to 6X10 atoms/cm.
  • a phosphorus doped silicon layer was epitaxially deposited on the P silicon layer 2 with a thickness of 1 to 3 4. by thermally decomposing silicon tetrachloride at about l,200 C. for 2 to 3 minutes. Antimony may be doped into the silicon layer 3 instead of phosphorus.
  • Step C The body next receives a heat treatment by heating the body to a high temperature for a sufficient time to convert the conductivity type of the P type layer 2 to N type as shown in FIG.
  • the newly formed N type layer 2' has a specific resistance of about 2 to SKI-cm.
  • the body was heated to about 1,200 C. for 20 to 30 minutes to obtain such a converted layer 2. If antimony is used to form the N type layer 3 in the step B, the body should be heated to about l,200 C. for 4 to 5 hours.
  • Step D a I type layer 4 of high-impurity concentration is formed at the surface of said N type layer 3 as shown in FIG. 1d by conventional diffusing techniques or epitaxially growing techniques, or is partially formed by using selectively treating techniques if needed.
  • boron was deposited on the N* layer 3 heated at a temperature of about l,030 C. for 1 hour in a nitrogen atmosphere and then the body thus formed, was heated to about l,000 C. for 2 to 3 hours in oxygen atmosphere to diffuse the deposited boron into the N layer, whereby a I type layer 4 was formed therein.
  • a silicon oxide film (not shown) of 5,000 to l0,000A thickness was formed at the surface of the P type layer 4.
  • a F type silicon layer in which boron is doped may be epitaxially deposited on the N type layer to a thickness of about 2p. by thermally decomposing silicon tetrachloride at about l,200 C. for 2 minutes.
  • a spectacular concentration distribution of impurities is obtained in the body thus produced through steps A to D.
  • a stepped PN-junction is obtained between the P layer 4 and the N layer 3, and a special region having a distribution in impurity concentration decreasing as leaving from the stepped junction is obtained in the N layer 3 and N layer 2'.
  • FIG. 3 shows a cross-sectional view of an improved variable capacitance diode according to this invention.
  • a diode is fabricated by selectively removing the body shown in FIG. 1d to make a moat extending to the substrate by means of conventional selective etching techniques, forming an insulating film such as silicon oxide, silicon oxide and silicon nitride, or lead-silicate glass on the surface of the body, forming a hole in the film to expose the surface of the P type layer 4, depositing metallic material such as gold or gold-gallium alloy to form an ohmic contact layer 6, further depositing silver on the contact layer 6 to form a second metal layer 7, and plating silver thick on the second metal layer 7 to form a bump 8 thereon, On the other side of the body, gold-antimony layer 9 is deposited on the surface of the N type substrate by vacuum evaporation method and silver layer 10 is deposited on the gold-antimony layer 9.
  • the above electrode structure and metallic material are desirable in the variable capacitance diode according to
  • step C was done independently or separately from step B and step D, it should be understood that the heat treatment in step C may be done simultaneously in step B and/or step D.
  • a semiconductor body having such a structure as shown in FIG. 1c may be obtained by a method described in the following example 2.
  • EXAMPLE 2 Another method for manufacturing a variable capacitance diode according to this invention will be example herein through FIGS. 1a, Icand 1d.
  • a P type boron doped silicon layer 2 of about 5p. thickness having a specific resistance of about 3Q-cm. is deposited on the surface of an N type silicon substrate 1 having a specific resistance of about 0.000lp.-cm. as shown in FIG. la by conventional epitaxial growing techniques.
  • the body thus produced is heated up to about l,200 C. in an antimony atmosphere for 5 hours and antimony is diffused into the P type layer 2, whereby an N+ type layer 3 of about 3 1. thickness is formed therein and the P type layer 2 is Converted to an N" type layer 2 as shown in FIG. 1c since N- type impurities contained in the N type substrate 1 and the N type layer 3 are diffused into the P type layer 2 due to the heat treatment in such high temperature.
  • a P type silicon layer of about 2 thickness is deposited on the surface of the N type layer 3 by a conventional epitaxially growing method as explained in the example 1.
  • a P type layer 12 of about 4p. thickness having a specific resistance of about lfl cm is epitaxially deposited on a N type silicon substrate 11 of about 0.002Q-cm, a silicon oxide film 21 is formed on the P type layer 12 by conventional oxidizing method, an N type region 13 is formed in the P type layer 12 by selectively diffusing an N-type impurity such as phosphorus, antimony or arsenide through a hole formed in the film 21, and a silicon oxide film 22 are formed on the diffused region 13.
  • the body thus produced is heated to a temperature not less than about l,l00 C. for a sufficient time to cause the N-type impurities contained in the N layer 13 and the N substrate 1 1 to be diffused into the P type layer 12 in order to convert the P type layer 12 to an N type layer 12' as shown in FIG. 4b, for example, for about 2 hours at l,l50 C. It is noted that in this step some parts of the P type layer 12 may remain therein without being converted into the conductivity type as shown in FIG. 4b.
  • a hole is formed in the silicon oxide film 22 and a P" type layer 14 is formed by selectively diffusing an N-type impurity such as phosphorus, antimony or arsenide into the N type layer 13 through the hole.
  • an N-type impurity such as phosphorus, antimony or arsenide
  • metal electrodes 16 to 20 are provided on the surface of the P type layer 14 and the substrate 11 by means as described in the example I.
  • the effect of autodoping is removed or extremely lessened by forming a layer of an opposite conductivity type, namely P type layer 2 or 12, on the substrate of highimpurity concentration, and a variable capacitance diode having an abrupt change in the distribution of impurity concentration at the super stepped junction and large capacitance variation is obtained.
  • a method for manufacturing a semiconductor diode comprising the steps of:
  • contacting metal electrodes contacts to the surface of said third semiconductor layer and said substrate.
  • said substrate has a specific resistance not more than 0.02 ohm-cm
  • said first semiconductor layer has a specific resistance of 0.5 to 3.0 ohm-cm. and a thickness of 1.0 to 5.0 microns
  • said second semiconductor layer has a specific resistance of 0.6 to 0.001 ohm-cm.
  • said second semiconductor layer is formed by epitaxially depositing said second semiconductor layer on the surface of said first semiconductor layer.
US50810A 1969-06-27 1970-06-29 Method for manufacturing a variable capacitance diode Expired - Lifetime US3638301A (en)

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Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3964089A (en) * 1972-09-21 1976-06-15 Bell Telephone Laboratories, Incorporated Junction transistor with linearly graded impurity concentration in the high resistivity portion of its collector zone
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
US4902633A (en) * 1988-05-09 1990-02-20 Motorola, Inc. Process for making a bipolar integrated circuit
US4980315A (en) * 1988-07-18 1990-12-25 General Instrument Corporation Method of making a passivated P-N junction in mesa semiconductor structure
US5166769A (en) * 1988-07-18 1992-11-24 General Instrument Corporation Passitvated mesa semiconductor and method for making same
US5182223A (en) * 1990-12-19 1993-01-26 Texas Instruments Incorporated Method of making an integrated circuit with capacitor
WO1997023900A1 (en) * 1995-12-21 1997-07-03 Philips Electronics N.V. Method of manufacturing a semiconductor device with a pn junction provided through epitaxy
US5686319A (en) * 1994-12-10 1997-11-11 Robert Bosch Gmbh Method for producing a diode
US5688714A (en) * 1990-04-24 1997-11-18 U.S. Philips Corporation Method of fabricating a semiconductor device having a top layer and base layer joined by wafer bonding
EP1139434A2 (de) 2000-03-29 2001-10-04 Tyco Electronics Corporation Variable Kapazitätsdiode mit hyperabruptem Übergangsprofil
EP1229584A2 (de) * 2001-02-05 2002-08-07 Matsushita Electric Industrial Co., Ltd. Halbleiterbauelement und zugehöriges Herstellungsverfahren

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3473977A (en) * 1967-02-02 1969-10-21 Westinghouse Electric Corp Semiconductor fabrication technique permitting examination of epitaxially grown layers
US3512056A (en) * 1967-04-25 1970-05-12 Westinghouse Electric Corp Double epitaxial layer high power,high speed transistor
US3544863A (en) * 1968-10-29 1970-12-01 Motorola Inc Monolithic integrated circuit substructure with epitaxial decoupling capacitance
US3560809A (en) * 1968-03-04 1971-02-02 Hitachi Ltd Variable capacitance rectifying junction diode

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3473977A (en) * 1967-02-02 1969-10-21 Westinghouse Electric Corp Semiconductor fabrication technique permitting examination of epitaxially grown layers
US3512056A (en) * 1967-04-25 1970-05-12 Westinghouse Electric Corp Double epitaxial layer high power,high speed transistor
US3560809A (en) * 1968-03-04 1971-02-02 Hitachi Ltd Variable capacitance rectifying junction diode
US3544863A (en) * 1968-10-29 1970-12-01 Motorola Inc Monolithic integrated circuit substructure with epitaxial decoupling capacitance

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3964089A (en) * 1972-09-21 1976-06-15 Bell Telephone Laboratories, Incorporated Junction transistor with linearly graded impurity concentration in the high resistivity portion of its collector zone
US4354309A (en) * 1978-12-29 1982-10-19 International Business Machines Corp. Method of manufacturing a metal-insulator-semiconductor device utilizing a graded deposition of polycrystalline silicon
US4902633A (en) * 1988-05-09 1990-02-20 Motorola, Inc. Process for making a bipolar integrated circuit
US4980315A (en) * 1988-07-18 1990-12-25 General Instrument Corporation Method of making a passivated P-N junction in mesa semiconductor structure
US5166769A (en) * 1988-07-18 1992-11-24 General Instrument Corporation Passitvated mesa semiconductor and method for making same
US5688714A (en) * 1990-04-24 1997-11-18 U.S. Philips Corporation Method of fabricating a semiconductor device having a top layer and base layer joined by wafer bonding
US5739570A (en) * 1990-12-19 1998-04-14 Texas Instruments Incorporated Integrated circuit
US5182223A (en) * 1990-12-19 1993-01-26 Texas Instruments Incorporated Method of making an integrated circuit with capacitor
US5686319A (en) * 1994-12-10 1997-11-11 Robert Bosch Gmbh Method for producing a diode
WO1997023900A1 (en) * 1995-12-21 1997-07-03 Philips Electronics N.V. Method of manufacturing a semiconductor device with a pn junction provided through epitaxy
US5915187A (en) * 1995-12-21 1999-06-22 U.S. Philips Corporation Method of manufacturing a semiconductor device with a pn junction provided through epitaxy
EP1139434A2 (de) 2000-03-29 2001-10-04 Tyco Electronics Corporation Variable Kapazitätsdiode mit hyperabruptem Übergangsprofil
EP1139434A3 (de) * 2000-03-29 2003-12-10 Tyco Electronics Corporation Variable Kapazitätsdiode mit hyperabruptem Übergangsprofil
EP1229584A2 (de) * 2001-02-05 2002-08-07 Matsushita Electric Industrial Co., Ltd. Halbleiterbauelement und zugehöriges Herstellungsverfahren
EP1229584A3 (de) * 2001-02-05 2004-10-27 Matsushita Electric Industrial Co., Ltd. Halbleiterbauelement und zugehöriges Herstellungsverfahren

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GB1312510A (en) 1973-04-04
DE2031831A1 (de) 1972-03-02

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