US3638196A - Learning machine - Google Patents
Learning machine Download PDFInfo
- Publication number
- US3638196A US3638196A US54231A US3638196DA US3638196A US 3638196 A US3638196 A US 3638196A US 54231 A US54231 A US 54231A US 3638196D A US3638196D A US 3638196DA US 3638196 A US3638196 A US 3638196A
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- learning
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- threshold value
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/023—Comparing digital values adaptive, e.g. self learning
Definitions
- ABSTRACT A learning machine in which threshold values corresponding 30 F l n A licati Priorlt Data 1 ores pp on y to the desired output conditions and having a dead zone J y I969 J p 44/545642 therehetween are used during the learning process for the dis Ju y 1969 Japan 44/ crimination of the output from a memory storing a plurality of standard pattern information, and this discriminating faculty is l i v l a s a ..34 /l72-5 utilized for the discrimination of input pattern information [5 l] Int.
- FIG 6 LEARNING MACHINE This invention relates to learning machines and more particularly to a learning machine of the kind having such a learning faculty that a set of given input conditions and a set of output conditions given for the input conditions are simultaneously stored in a memory so as to derive any desired output condition therefrom.
- Learning machines of this kind are generally provided with an adaptive logic circuit which has such a learning faculty that an output satisfying the desired condition can be obtained for each input condition so that a correct output response can be provided for each input condition after learning.
- retraining can be done as required so as to deliver a new output response for a new input condition.
- FIG. 1 showing the basic structure of a learning machine of this kind, it comprises a plurality of weight elements A, B, C, having respective weight factors W,, W W which may, for example, be a voltage, a summing circuit D, a decision circuit B, an output terminal F, a terminal G to which a desired output is applied, and a learning control cir cuit H.
- W weight factors
- W W weight factors
- the inputs X,, X,, X may be one ofa set of l and or one of a set of+l and -l.”
- the inputs X,, X X are multiplied by the weights W,, W W of the respective weight elements A, B, C, and the products are summed up in the summing circuit D.
- the sum is compared with the threshold value W; in the decision circuit E, and the output delivered from the decision circuit E is "+1" and 0" respectively when the sum is larger and smaller than the threshold value W; in the embodiment of the present invention described hereinbelow.
- the learning control circuit H adjusts the weight factors until they are decreased to give the actual output 0"
- the above procedure is repeated for all the input patterns each consisting of a set of numerals so that all the input patterns can be classified into two categories consisting ofa class 1 and a class 2.
- the present invention contempla es the provision of a learning machine which is free front the above problem by virtue of the fact that it is provided with a memory for storing a plurality of standard patterns and a decision circuit acting as a one'out-of-three decision element during the learning process so as to cooperate with threshold values having a dead zone therebetween.
- Another object of the present invention is to provide a learning machine in which the classification of standard patterns in a decision circuit during the learning process is carried out on the basis of threshold values having a dead zone therebetween and the discrimination is effected on the basis on only one threshold value as heretofore so as to enhance the precision ofdiscrimination.
- FlG, l is a block diagram showing the basic structure ofa learning machine
- FIG. 2 is a block diagram showing the structure of an improved learning machine according to the present invention.
- FIGS. 3 through 6 and 8 are circuit diagrams showing the detail of parts of the learning machine shown in FIG. 2;
- FIGS. 7a and 7b are charts showing the operation of parts of the structure shown in FIG. 6.
- a plurality of inputs are applied to respective input terminals 1, 2 and 3 and are held in respective circuits 4, 5 and 6 for any desired period of time.
- the circuits 4, 5 and 6 may be bistable multivibrators.
- a plurality of weight factor selective circuits 7, 8 and 9 include weight elements for multiplying the outputs from the bistable multivibrators 4, S and 6 by respective weight factors W,, W, and 1,.
- W weight factors
- n bistable multivibrators and n weight factor selective circuits only three of them are shown herein for the sake of simplicity.
- the input signals applied to the input terminals 1, 2 and 3 are either l or "0,” and these signals are multiplied by the respective weight factors W W, and W, so that the products appear at the output sides of the respective weight factor selective circuits 7, 8 and 9.
- a memory 10 stores successively the outputs from the bistable multivibrators 4, 5 and 6, and at the same time, stores successively expected outputs for standard patterns applied from a terminal 11.
- a trigger pulse generator 12 controls the writing and reading of input patterns into and out of the memory 10 during the learning process, depending on a signal applied thereto from a manual signal input terminal 13 or an output signal delivered from a learning pulse generator 14 having a function which will be described later.
- a summing circuit 15 sums up the weighted values delivered from the weight factor selective circuits 7, 8 and 9,
- a decision circuit 16 compares the output from the summing circuit 15 with a threshold value We.
- a threshold value selection circuit 18 supplies to the decision circuit 16 the threshold value W; corresponding to a desired output which may be H or "0" appearing at an output terminal 101 of the memory 10 during learning, while a threshold value W" applied to the selection circuit 18 from an input terminal thereof is directly supplied to the decision circuit 16 during discrimination.
- the practical structure of the memory 10 is shown in H6. 3.
- the function of the memory 10 is to store standard patterns and output signals desired for the patterns as described above.
- a switch S is thrown to the side of the terminals 0 and b to apply a voltage of E volts to the gates of gating transistors 6,, G G and G, so as to urge these transistors to conduct.
- the desired output supplied from the terminal 1 l is written in a memory means such as a shift register SR, through the transistor 0,, while the components constituting the standard pattern supplied from the bistable multivibrators 4, 5 and 6 are written in memory means such as shift registers SR,, SR, and SR through the transistors 0,, G and 0,,
- the switch S In reading out the contents written in the shift registers SR,, SR,, SR, and SR, the switch S, is thrown to the side of the contacts c and d so that the shift registers SR,, SR SR, and SR, are connected in a ring with respective transistors G G G and G On the other hand, the gates of the transistors G,, 6,, G and G are grounded and these transistors are cut off.
- the contents stored in the shift registers SR,, SR SR, and SR are read out by the pulse supplied from the trigger pulse generator 12 and are rewritten in the shift registers SR,, SR SR and SR, through the respective transistors 6 G G and G
- the outputs appearing at terminals 101, I02, 103 and [04 are applied to the learning pulse generator 14 and the threshold value selection circuit 18, and to the bistable mul tivibrators 4, 5 and 6, respectively,
- the state of the bistable multivibrator BS is inverted by the pulse supplied from the pulse generator PO, to stop the operation of the learning pulse generator 14 and the bistable multivibrator BS, is restored to the original state by a signal applied thereto through a delay means DE, and a monostable multivibrator M5,.
- +l represents a high level at +5 volts and 0" represents a low level at 0 volts.
- the inputs applied to an AND-gate A include the actual output and the desired output which is passed through an invertor I, while the inputs applied to a NAND-gate NA, include the desired output and the actual output which is passed through an invertor 1,.
- one of the three input signals applied to the AND-gate A, and NAND-gate NA is in the low level and the two input signals applied to a NAND- gate NA remain in their high level with the result that a bista ble multivibrator BS, is not actuated and no learning pulse is generated.
- the desired output is in the low level and the actual output is in the high level. Therefore, all the input signals applied to the AND-gate A, are in the high level. and a bistable multivibrator 58,, a monostable multivibrator MS, and the NAND-gate NA, are operated.
- the weight factors W W, and W, of the respective weight elements in the weight factor selective circuits 7, 8 and 9 must be decreased to reduce the output from the summing circuit 15.
- the situation is opposite in the case Ill. That is, the weight factors W W and W, must be increased, and the learning is completed when the output from the summing circuit 15 exceeds the threshold value +w.
- a switch 8 in the threshold value selection circuit 18 is thrown to the side of the terminal a in the case of the learning and to the side of the terminal b in the case of the discrimination.
- the threshold value W supplied from the threshold value selection circuit I8 to the decision circuit 16 corresponds to the desired output "+1" or 0" stored in the memory 10, while when the switch S is thrown to the side of the terminal b, the threshold value W. supplied from the threshold value selection circuit 18 to the decision circuit 16 is proportional to the threshold value We
- the decision circuit 16 acts as a conventional one out-ofltwo decision element because there is only one threshold value as seen in FIG. 7b.
- FIG. 8 shows the practical structure of the weight factor selective circuit 7 including the weight element.
- the remaining weight factor selective circuit 8 and 9 have the same structure as the selective circuit 7.
- the weight factor of the weight element is variable over five levels which are +2 volts, +l volts, 0 volts, l volts and 2 volts.
- bistable multivibrators BS BS BS BS; and 85 have the function of selecting the weight factor and the outputs from the respective bistable multivibrators control the conduction and cutoff of five gating transistors 6 G G G and G More precisely, when anyone of the bistable multivibrators BS BS B8,, BS and BS delivers an output l at a level of-IO volts (herein, the negative logic is applied), the voltage at the drain electrode of the transistor connected to the output of the specific bistable multivibrator appears at its source electrode.
- the input signal is applied from the bistable multivibrator 4, which sets the potential of the gate electrode of a transistor G at a level of 0 volts, this transistor G is cut off and the voltage appearing at the source electrode of the specific transistor is supplied to the summing circuit as the weight. Since two or more outputs of the bistable multivibrators B5,, B8,, BS BS, and B8,, cannot simultaneously take the value 1, only one of the five voltages representing the respective weights should appear as the weight. Gating transistors G 0,, and G,,, are cut off when their gate voltage is 0 volts.
- the bistable multivibrator BS When the bistable multivibrator BS, is delivering I," the transistor 0,, is cut off due to the fact that 0 volts is applied to the gate thereof, and all of the five learning pulses pass through the point A to shift the position of l until it returns to the bistable multivibrator BS again so that no shift can substantially occur. Similarly, an increment control signal of negative voltage appears as soon as the learning pulses are supplied from the terminal [43 of the learning pulse generator 14, and since the transistor 0,, is cut off unless the bistable multivibrator B8,, is delivering l the position of the output "1 is shifted to the higher place in response to the learning pulses.
- the stored information is supplied to the learning pulse generator 14 and the bistable multivibrators 4, 5 and 6 from the respective output terminals 101, 102, 103 and 104 of the memory 10.
- the information supplied to the bistable multivibrators 4, 5 and 6 is weighted by the weight factor selective circuits 7, 8 and 9, and is passed through the summing circuit I5 to be applied to the decision circuit 16 wherein the sum is compared with the threshold value W and the result appears at the output terminal 17 as an output +l or "0.”
- the switch S in the threshold value selection circuit 18 is connected to the output terminal 101 of the memory 10 so that the threshold value W corresponds to the value +l or
- the decision circuit 16 has a function similar to the fu nction of a one-outof-three decision element for the threshold values having a dead zone therebetween and the output therefrom is classified under a severe condition compared with the classification by a one-out-of-two decision element.
- a learning machine comprising a memory for storing a plurality of standard pattern information, a plurality of weight elements connected to respective weight selective circuits for applying a variable weight factor, selecting means for selecting the output from said memory and input pattern information to be discriminated, a threshold value selection circuit, a decision circuit for generating an output corresponding to the relative magnitude of the sum of outputs from said weight elements and an output supplied from said threshold value selection circuit, and a learning pulse generator for supplying learning pulses to said weight selective circuits thereby varying the weight factors of said weight elements when the output from said decision circuit does not coincide with a desired output and driving said memory for deriving the next standard pattern information when the output from said decision circuit coincides with the desired output, whereby the standard pat tern information can be successively learned for the discrimination of input pattern information.
- said memory comprises a plurality of shift registers, first gate means connected across the input and output terminals of said shift registers, second gate means interposed between signal input terminals and the input terminals of said shift registers, and common selectively conducting means for causing one of the groups of said first and second gate means to conduct while cutting off the other group, so that said first gate means are cut oh and said second gate means are urged to conduct by said selectively conducting means so as to successively write the standard pattern information supplied from said signal input terminals in said shift registers, and at the completion of the writing, said second gate means are cut off and said first gate means are urged to conduct by said selectively conducting means so as to successively supply the standard pattern information stored in said shift registers to said weight elements, and at the same time, to circulate same through said first gate means.
- each said weight selective circuit comprises a plurality of bistable multivibrators connected in cascade, first gate means for gating the output from said learning pulse generator and supplying a trigger pulse to said bistable multivibrators and a plurality of second gate means applied with different voltages representative of weight factors, so that one of said second gate means is selected by the output from said bistable multivibrators connected in cascade.
- each said weight element comprises gate means which controls the passage of the voltage representative of the weight factor supplied from said weight selective circuit in response to the standard pattern information supplied from said memory or the externally supplied input pattern information to be discriminated.
- said learning pulse generator comprises two inverse coincidence circuits to which the output from said decision circuit and the desired output are applied as inputs, first pulse-generating means connected to one of said inverse coincidence circuits, weight factor decrement control signal generating means connected to said first pulse-generating means for controlling the decrement of the weight factor, weight factor increment control signal generating means receiving the output from the other said inverse coincidence circuit for controlling the increment of the weight factor, second pulse-generating means receiving the output from the other said inverse coincidence circuit and the output from said first pulse-generating means for responding to the logical sum of the inputs thereto for generating at least one learning pulse, and third pulse-generating means for reading out another standard'pattern informatlon stored In said memory upon detection 0 the coincidence between the two inputs applied to said inverse coincidence circuits,
- said threshold value selection circuit comprises selecting means for selecting one of a set of a desired output and a threshold value, and the desired output is selected during learning so that it is supplied as the threshold value.
- a learning machine as claimed in claim 1 in which said threshold value selection circuit comprises means for selecting one of means generating a threshold value representative of a desired output and means generating a single threshold value and supplying the output from the selected means to said decision circuit 8.
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- Pure & Applied Mathematics (AREA)
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Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP5664369 | 1969-07-14 | ||
JP44056642A JPS5040301B1 (es) | 1969-07-14 | 1969-07-14 |
Publications (1)
Publication Number | Publication Date |
---|---|
US3638196A true US3638196A (en) | 1972-01-25 |
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ID=26397603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US54231A Expired - Lifetime US3638196A (en) | 1969-07-14 | 1970-07-13 | Learning machine |
Country Status (6)
Country | Link |
---|---|
US (1) | US3638196A (es) |
DE (1) | DE2034683C3 (es) |
FR (1) | FR2051725B1 (es) |
GB (1) | GB1317745A (es) |
NL (1) | NL7010423A (es) |
SU (1) | SU414823A3 (es) |
Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3934231A (en) * | 1974-02-28 | 1976-01-20 | Dendronic Decisions Limited | Adaptive boolean logic element |
US4326259A (en) * | 1980-03-27 | 1982-04-20 | Nestor Associates | Self organizing general pattern class separator and identifier |
US4518866A (en) * | 1982-09-28 | 1985-05-21 | Psychologics, Inc. | Method of and circuit for simulating neurons |
US4593367A (en) * | 1984-01-16 | 1986-06-03 | Itt Corporation | Probabilistic learning element |
US4599692A (en) * | 1984-01-16 | 1986-07-08 | Itt Corporation | Probabilistic learning element employing context drive searching |
US4599693A (en) * | 1984-01-16 | 1986-07-08 | Itt Corporation | Probabilistic learning system |
US4620286A (en) * | 1984-01-16 | 1986-10-28 | Itt Corporation | Probabilistic learning element |
US4751673A (en) * | 1982-03-22 | 1988-06-14 | The Babcock & Wilcox Company | System for direct comparison and selective transmission of a plurality of discrete incoming data |
US4876731A (en) * | 1988-02-19 | 1989-10-24 | Nynex Corporation | Neural network model in pattern recognition using probabilistic contextual information |
US5040214A (en) * | 1985-11-27 | 1991-08-13 | Boston University | Pattern learning and recognition apparatus in a computer system |
US5060277A (en) * | 1985-10-10 | 1991-10-22 | Palantir Corporation | Pattern classification means using feature vector regions preconstructed from reference data |
US5077807A (en) * | 1985-10-10 | 1991-12-31 | Palantir Corp. | Preprocessing means for use in a pattern classification system |
US5101361A (en) * | 1989-09-29 | 1992-03-31 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Analog hardware for delta-backpropagation neural networks |
US5140538A (en) * | 1988-12-27 | 1992-08-18 | University Of Arkansas | Hybrid digital-analog computer parallel processor |
US5263122A (en) * | 1991-04-22 | 1993-11-16 | Hughes Missile Systems Company | Neural network architecture |
US5293459A (en) * | 1988-12-23 | 1994-03-08 | U.S. Philips Corporation | Neural integrated circuit comprising learning means |
US5355438A (en) * | 1989-10-11 | 1994-10-11 | Ezel, Inc. | Weighting and thresholding circuit for a neural network |
US5361328A (en) * | 1989-09-28 | 1994-11-01 | Ezel, Inc. | Data processing system using a neural network |
US5416850A (en) * | 1988-01-11 | 1995-05-16 | Ezel, Incorporated | Associative pattern conversion system and adaption method thereof |
US5479575A (en) * | 1991-02-12 | 1995-12-26 | Mitsubishi Denki Kabushiki Kaisha | Self-organizing neural network for pattern classification |
US5479574A (en) * | 1993-04-01 | 1995-12-26 | Nestor, Inc. | Method and apparatus for adaptive classification |
US5517667A (en) * | 1993-06-14 | 1996-05-14 | Motorola, Inc. | Neural network that does not require repetitive training |
US5555439A (en) * | 1991-06-12 | 1996-09-10 | Hitachi, Ltd. | Learning system and a learning pattern showing method for a neural network |
US5633988A (en) * | 1989-06-02 | 1997-05-27 | Yozan Inc. | Adaptation method for data processing system |
US5742740A (en) * | 1990-09-20 | 1998-04-21 | Atlantic Richfield Company | Adaptive network for automated first break picking of seismic refraction events and method of operating the same |
US6625588B1 (en) * | 1997-03-26 | 2003-09-23 | Nokia Oyj | Associative neuron in an artificial neural network |
US6652283B1 (en) | 1999-12-30 | 2003-11-25 | Cerego, Llc | System apparatus and method for maximizing effectiveness and efficiency of learning retaining and retrieving knowledge and skills |
FR2859799A1 (fr) * | 2003-09-16 | 2005-03-18 | Lionel Mabille | Procede et dispositif pour l'aide au diagnostic de l'etat de fonctinnement d'un processus |
US6995702B2 (en) | 1998-10-01 | 2006-02-07 | Biosgroup Inc. | Automatic evolution of mixed analog and digital electronic circuits |
US20150347896A1 (en) * | 2014-05-27 | 2015-12-03 | Purdue Research Foundation | Electronic comparison systems |
US20160019454A1 (en) * | 2014-07-18 | 2016-01-21 | James LaRue | J Patrick's Ladder A Machine Learning Enhancement Tool |
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1970
- 1970-07-10 FR FR707025776A patent/FR2051725B1/fr not_active Expired
- 1970-07-13 DE DE2034683A patent/DE2034683C3/de not_active Expired
- 1970-07-13 SU SU1466335A patent/SU414823A3/ru active
- 1970-07-13 US US54231A patent/US3638196A/en not_active Expired - Lifetime
- 1970-07-13 GB GB3395870A patent/GB1317745A/en not_active Expired
- 1970-07-14 NL NL7010423A patent/NL7010423A/xx unknown
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Cited By (41)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3934231A (en) * | 1974-02-28 | 1976-01-20 | Dendronic Decisions Limited | Adaptive boolean logic element |
US4326259A (en) * | 1980-03-27 | 1982-04-20 | Nestor Associates | Self organizing general pattern class separator and identifier |
US4751673A (en) * | 1982-03-22 | 1988-06-14 | The Babcock & Wilcox Company | System for direct comparison and selective transmission of a plurality of discrete incoming data |
US4518866A (en) * | 1982-09-28 | 1985-05-21 | Psychologics, Inc. | Method of and circuit for simulating neurons |
US4593367A (en) * | 1984-01-16 | 1986-06-03 | Itt Corporation | Probabilistic learning element |
US4599692A (en) * | 1984-01-16 | 1986-07-08 | Itt Corporation | Probabilistic learning element employing context drive searching |
US4599693A (en) * | 1984-01-16 | 1986-07-08 | Itt Corporation | Probabilistic learning system |
US4620286A (en) * | 1984-01-16 | 1986-10-28 | Itt Corporation | Probabilistic learning element |
US5060277A (en) * | 1985-10-10 | 1991-10-22 | Palantir Corporation | Pattern classification means using feature vector regions preconstructed from reference data |
US5077807A (en) * | 1985-10-10 | 1991-12-31 | Palantir Corp. | Preprocessing means for use in a pattern classification system |
US5347595A (en) * | 1985-10-10 | 1994-09-13 | Palantir Corporation (Calera Recognition Systems) | Preprocessing means for use in a pattern classification system |
US5040214A (en) * | 1985-11-27 | 1991-08-13 | Boston University | Pattern learning and recognition apparatus in a computer system |
US5506915A (en) * | 1988-01-11 | 1996-04-09 | Ezel Incorporated | Associative pattern conversion system and adaptation method thereof |
US5416850A (en) * | 1988-01-11 | 1995-05-16 | Ezel, Incorporated | Associative pattern conversion system and adaption method thereof |
US4876731A (en) * | 1988-02-19 | 1989-10-24 | Nynex Corporation | Neural network model in pattern recognition using probabilistic contextual information |
US5293459A (en) * | 1988-12-23 | 1994-03-08 | U.S. Philips Corporation | Neural integrated circuit comprising learning means |
US5140538A (en) * | 1988-12-27 | 1992-08-18 | University Of Arkansas | Hybrid digital-analog computer parallel processor |
US5633988A (en) * | 1989-06-02 | 1997-05-27 | Yozan Inc. | Adaptation method for data processing system |
US5361328A (en) * | 1989-09-28 | 1994-11-01 | Ezel, Inc. | Data processing system using a neural network |
US5101361A (en) * | 1989-09-29 | 1992-03-31 | The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration | Analog hardware for delta-backpropagation neural networks |
US5355438A (en) * | 1989-10-11 | 1994-10-11 | Ezel, Inc. | Weighting and thresholding circuit for a neural network |
US5742740A (en) * | 1990-09-20 | 1998-04-21 | Atlantic Richfield Company | Adaptive network for automated first break picking of seismic refraction events and method of operating the same |
US5479575A (en) * | 1991-02-12 | 1995-12-26 | Mitsubishi Denki Kabushiki Kaisha | Self-organizing neural network for pattern classification |
US5263122A (en) * | 1991-04-22 | 1993-11-16 | Hughes Missile Systems Company | Neural network architecture |
US5555439A (en) * | 1991-06-12 | 1996-09-10 | Hitachi, Ltd. | Learning system and a learning pattern showing method for a neural network |
US5479574A (en) * | 1993-04-01 | 1995-12-26 | Nestor, Inc. | Method and apparatus for adaptive classification |
US5574827A (en) * | 1993-06-14 | 1996-11-12 | Motorola, Inc. | Method of operating a neural network |
US5720002A (en) * | 1993-06-14 | 1998-02-17 | Motorola Inc. | Neural network and method of using same |
US5781701A (en) * | 1993-06-14 | 1998-07-14 | Motorola, Inc. | Neural network and method of using same |
US5517667A (en) * | 1993-06-14 | 1996-05-14 | Motorola, Inc. | Neural network that does not require repetitive training |
US6625588B1 (en) * | 1997-03-26 | 2003-09-23 | Nokia Oyj | Associative neuron in an artificial neural network |
US6995702B2 (en) | 1998-10-01 | 2006-02-07 | Biosgroup Inc. | Automatic evolution of mixed analog and digital electronic circuits |
US6652283B1 (en) | 1999-12-30 | 2003-11-25 | Cerego, Llc | System apparatus and method for maximizing effectiveness and efficiency of learning retaining and retrieving knowledge and skills |
FR2859799A1 (fr) * | 2003-09-16 | 2005-03-18 | Lionel Mabille | Procede et dispositif pour l'aide au diagnostic de l'etat de fonctinnement d'un processus |
US20150347896A1 (en) * | 2014-05-27 | 2015-12-03 | Purdue Research Foundation | Electronic comparison systems |
US9489618B2 (en) * | 2014-05-27 | 2016-11-08 | Purdue Research Foudation | Electronic comparison systems |
US20170047913A1 (en) * | 2014-05-27 | 2017-02-16 | Purdue Research Foundation | Electronic comparison systems |
US9813048B2 (en) * | 2014-05-27 | 2017-11-07 | Purdue Research Foundation | Electronic comparison systems |
US10476487B2 (en) * | 2014-05-27 | 2019-11-12 | Purdue Research Foundation | Electronic comparison systems |
US20160019454A1 (en) * | 2014-07-18 | 2016-01-21 | James LaRue | J Patrick's Ladder A Machine Learning Enhancement Tool |
US10242313B2 (en) * | 2014-07-18 | 2019-03-26 | James LaRue | Joint proximity association template for neural networks |
Also Published As
Publication number | Publication date |
---|---|
DE2034683B2 (de) | 1973-08-16 |
DE2034683C3 (de) | 1974-03-14 |
SU414823A3 (es) | 1974-02-05 |
DE2034683A1 (de) | 1971-02-18 |
FR2051725A1 (es) | 1971-04-09 |
FR2051725B1 (es) | 1973-04-27 |
GB1317745A (en) | 1973-05-23 |
NL7010423A (es) | 1971-01-18 |
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