US3623218A - Method for determining depth of lapping of dielectrically isolated integrated circuits - Google Patents

Method for determining depth of lapping of dielectrically isolated integrated circuits Download PDF

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Publication number
US3623218A
US3623218A US791659*A US3623218DA US3623218A US 3623218 A US3623218 A US 3623218A US 3623218D A US3623218D A US 3623218DA US 3623218 A US3623218 A US 3623218A
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United States
Prior art keywords
depth
lapping
integrated circuits
gauges
dielectrically isolated
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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US791659*A
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English (en)
Inventor
Hajime Mitarai
Carroll E Nelson
Albert P Younmans
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Signetics Corp
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Signetics Corp
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Publication of US3623218A publication Critical patent/US3623218A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0641—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region without components of the field effect type
    • H01L27/0647—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. vertical bipolar transistor and bipolar lateral transistor and resistor
    • H01L27/0652—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/049—Equivalence and options
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/115—Orientation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation
US791659*A 1969-01-16 1969-01-16 Method for determining depth of lapping of dielectrically isolated integrated circuits Expired - Lifetime US3623218A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US79165969A 1969-01-16 1969-01-16

Publications (1)

Publication Number Publication Date
US3623218A true US3623218A (en) 1971-11-30

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Family Applications (1)

Application Number Title Priority Date Filing Date
US791659*A Expired - Lifetime US3623218A (en) 1969-01-16 1969-01-16 Method for determining depth of lapping of dielectrically isolated integrated circuits

Country Status (5)

Country Link
US (1) US3623218A (de)
DE (1) DE2001564A1 (de)
FR (1) FR2030159A1 (de)
GB (1) GB1258354A (de)
NL (1) NL7000502A (de)

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755012A (en) * 1971-03-19 1973-08-28 Motorola Inc Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor
US3769562A (en) * 1972-02-07 1973-10-30 Texas Instruments Inc Double isolation for electronic devices
JPS4960182A (de) * 1972-07-26 1974-06-11
US3902936A (en) * 1973-04-04 1975-09-02 Motorola Inc Germanium bonded silicon substrate and method of manufacture
US3911559A (en) * 1973-12-10 1975-10-14 Texas Instruments Inc Method of dielectric isolation to provide backside collector contact and scribing yield
US4047195A (en) * 1973-11-12 1977-09-06 Scientific Micro Systems, Inc. Semiconductor structure
US4070748A (en) * 1972-04-10 1978-01-31 Raytheon Company Integrated circuit structure having semiconductor resistance regions
JPS5360184A (en) * 1976-11-10 1978-05-30 Oki Electric Ind Co Ltd Production of semiconductor wafer
US4120744A (en) * 1971-06-25 1978-10-17 Texas Instruments Incorporated Method of fabricating a thermal display device
US4309813A (en) * 1979-12-26 1982-01-12 Harris Corporation Mask alignment scheme for laterally and totally dielectrically isolated integrated circuits
US4312115A (en) * 1976-12-14 1982-01-26 Heinz Diedrich Process to obtain multielement linear bidimensional infrared detectors having improved exactness of geometry and high degree of integration
US4338620A (en) * 1978-08-31 1982-07-06 Fujitsu Limited Semiconductor devices having improved alignment marks
US4861731A (en) * 1988-02-02 1989-08-29 General Motors Corporation Method of fabricating a lateral dual gate thyristor
US5051378A (en) * 1988-11-09 1991-09-24 Sony Corporation Method of thinning a semiconductor wafer
US5329156A (en) * 1992-12-22 1994-07-12 Spectrian, Inc. Feed bus for RF power transistors
US5414296A (en) * 1992-12-22 1995-05-09 Spectrian, Inc. Venetian blind cell layout for RF power transistor

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3755012A (en) * 1971-03-19 1973-08-28 Motorola Inc Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor
US4120744A (en) * 1971-06-25 1978-10-17 Texas Instruments Incorporated Method of fabricating a thermal display device
US3769562A (en) * 1972-02-07 1973-10-30 Texas Instruments Inc Double isolation for electronic devices
US4070748A (en) * 1972-04-10 1978-01-31 Raytheon Company Integrated circuit structure having semiconductor resistance regions
JPS5858810B2 (ja) * 1972-07-26 1983-12-27 テキサス インストルメンツ インコ−ポレ−テツド 半導体装置の製作法
JPS4960182A (de) * 1972-07-26 1974-06-11
US3902936A (en) * 1973-04-04 1975-09-02 Motorola Inc Germanium bonded silicon substrate and method of manufacture
US4047195A (en) * 1973-11-12 1977-09-06 Scientific Micro Systems, Inc. Semiconductor structure
US3911559A (en) * 1973-12-10 1975-10-14 Texas Instruments Inc Method of dielectric isolation to provide backside collector contact and scribing yield
JPS5360184A (en) * 1976-11-10 1978-05-30 Oki Electric Ind Co Ltd Production of semiconductor wafer
US4312115A (en) * 1976-12-14 1982-01-26 Heinz Diedrich Process to obtain multielement linear bidimensional infrared detectors having improved exactness of geometry and high degree of integration
US4338620A (en) * 1978-08-31 1982-07-06 Fujitsu Limited Semiconductor devices having improved alignment marks
US4309813A (en) * 1979-12-26 1982-01-12 Harris Corporation Mask alignment scheme for laterally and totally dielectrically isolated integrated circuits
US4861731A (en) * 1988-02-02 1989-08-29 General Motors Corporation Method of fabricating a lateral dual gate thyristor
US5051378A (en) * 1988-11-09 1991-09-24 Sony Corporation Method of thinning a semiconductor wafer
US5329156A (en) * 1992-12-22 1994-07-12 Spectrian, Inc. Feed bus for RF power transistors
US5414296A (en) * 1992-12-22 1995-05-09 Spectrian, Inc. Venetian blind cell layout for RF power transistor
WO1995030245A1 (en) * 1994-05-02 1995-11-09 Spectrian, Inc. Venetian blind cell layout for rf power transistor

Also Published As

Publication number Publication date
FR2030159A1 (de) 1970-10-30
DE2001564A1 (de) 1970-07-30
GB1258354A (de) 1971-12-30
NL7000502A (de) 1970-07-20

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