US3593035A

US3593035A - Marginal switching arrangement

Info

Publication number: US3593035A
Application number: US776473A
Authority: US
Inventors: Jean Victor Martens
Original assignee: International Standard Electric Corp
Current assignee: Alcatel Lucent NV
Priority date: 1967-12-29
Filing date: 1968-11-18
Publication date: 1971-07-13
Anticipated expiration: 1988-07-13
Also published as: BE708711A; DE1815681B2; DE1815681A1; NL6818685A; GB1246815A; ES361970A1

Abstract

The arrangement provides two long-tail transistor pairs with paralleled collector outputs and a detecting device branched across the above pair of outputs. The input signal is compared with the upper and lower levels of the selected range by means of the first and a second transistor pair and gives rise to equal potentials at both ends of the detecting device except when this input signal is above or below the range.

Description

United States Patent Inventor Jean Victor Martens Deurne-Zuid, Belgium Appl. No. 776,473 Filed Nov. 18, 1968 Patented July 13, 1971 Assignee International Standard Electric Corporation New York, N.Y. Priority Dec. 29, 1967 Belgium BL 29 MARGINAL SWITCHING ARRANGEMENT 7 Claims, 2 Drawing Figs.

U.S. Cl 307/235, 3 1 7/1 48.5

Int. Cl H03k 5/20 Field of Search 307/235,

[56] References Cited UNITED STATES PATENTS 3,139,562 6/1964 Freeborn 307/235 X 3,428,826 2/1969 Berry 307/235 3,470,497 9/1969 Kotter 307/235 X Primary Examiner-Donald D. Forrer Assistant Exam iner-John Zazworsky Attorneys-C. Cornell Remsen, Jr., Walter J. Baum, Percy P. Lantzy, Philip M. Bolton, Isidore Otogut and Charles L. Johnson, Jr.

ABSTRACT: The arrangement provides two long-tail transistor pairs with paralleled collector outputs and a detecting device branched across the above pair of outputs. The input signal is compared with the upper and lower levels of the selected range by means of the first and a second transistor pair and gives rise to equal potentials at both ends of the detecting device except when this input signal is above or below the range.

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Q5 05 i 42 M 3 1 W iz/7 @g A Home y MARGINAL SWITCHING ARRANGEMENT BACKGROUND OF THE INVENTION The present invention relates to a marginal switching arrangement for operating an output detecting device when the amplitude of the input signal lies outside a predetermined range.

Such a marginal switching arrangement is known from the Dutch patent application Ser. No. 250,589. This known-arrangement has a low performance, since its characteristics depend on temperature and supply voltage variations.

SUMMARY OF THE INVENTION An object of the present invention is to provide an improved marginal switching arrangement of the above type, which does not present the mentioned drawbacks.

The present marginal switching arrangement is characterized by the fact, that said device is included in the branch of a 4-pole circuit having no common pole with a source of energy feeding said circuit which includes at least two branches whose impedances are jointly controlled by said input signals and two fixed reference sources defining said range so that it acts as a substantially balanced bridge except when said input signals are above or below said range.

BRIEF DESCRIPTION OF THE DRAWINGS The abov: mentioned and other objects and features of the invention will become more apparent and the invention itself will be best understood by referring to the following description of embodiments taken in conjunction with the accompanying drawings in which:

FIG. 1 shows a marginal switching arrangement in accordance with the invention;

FIG. 2 shows a modification of a detecting device used in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 the marginal switching arrangement shown therein comprises two long-tail transistor pairs .Q lQ and Q /Q The bases of transistors Q and Q are connected in common and their junction point is connected to an output of a signal source S via a resistor R The other output of signal source S is connected to ground.

The bases of transistors Q and Q are connected through respective resistors R, and R to the junction point of a resistor R and a Zener diode W forming potentiometer. The other end of resistor R and the anode of diode W are respectively connected to a source V of positive DC potential and to ground. The base of transistor Q is further connected to ground via a resistor R The common connection points of the emitters of transistor pairs Q lQ and Q /Q, are connected to ground via a resistor R, and a resistor R (R /1R respectively. ResistorsR and'lit simulate constant current sources. The collectors of transistors Q and Q 3 are connected together as are the collectors of transistors Q and Q and the respective junction points are connected to the source V via resistors IR and R respectively; (R =R The junction points of the collectors of transistors Q,Q and Q Q, are interconnected via a relay Pr. The output of the arrangement, referred to as OUT, is taken across a make contact p of relay Pr.

The marginal switching arrangement of FIG. 2 is similar to the arrangement of FIG. 1, except that the output relay Pr and its contact p are replaced by a bistate circuit comprising the PNP transistors Q Q and Q The bases of transistors Q and Q; are connected to the junction points of the collectors of transistors Q,--Q and Q Q respectively. The emitters of transistors Q and Q, are connected to each other and their junction point is connected to the source V via the emittercollector junction of the transistors Q which plays the role of a Zener diode. The collectors of transistors Q and Q are also connected to each other, their junction point being connected to ground via a resistor R The output of the arrangement, referred to as OUT, is taken from the interconnected collectors of transistor pair Q lQ The principle of operation of the marginal switching arrangement of FIG, 1 is as follows:

As long as the output voltage level of the source S, lies inside a predetermined range defined by the upper and lower reference voltages M and m applied to the bases of transistors Q and Q respectively, relay Pr remains in its nonenergized condition and consequently its make contact p remains open. Indeed, the constant currents i, and i feeding the long-tail transistor pairs (),/Q and Q /Q circulate from the bias source V to ground via the resistors R, and R the collectoremitter junctions of transistors Q and Q and the resistor R, and R respectively. Due to the voltage drop across resistor R being equal to the voltage drop across resistor R (R =R i =i no current circulates through relay Pr so that contact 5 remains open. As soon as the output voltage level of signal sources becomes higher than the reference level M applied to the base of transistor Q transistors Q and Q conduct, whereas transistors Q and Q are cut off. Alternatively, as soon as the output voltage level of signal source S becomes lower than the reference level m applied to the base of transistor Q transistors Q and Q conduct, whereas transistors Q, and Q are cutoff. Assuming that the resistance of the winding of relay Pr is very low with respect to the resistances R and R a current equal to current i or i 2 (i,=i circulates through relay Pr. Relay Pr is thus energized and closes its contact p. The closure of contact p causes the activation of an alarm circuit (not shown).

The marginal arrangement of FIG. 2 is adapted for being used in applications where a high degree of accuracy is required or where high operation speed requirements exclude the use of relay Pr. This arrangement provides a positive output voltage when the voltage applied to its input by the signal source S is outside the range fixed by the limits M and m. The operation of the arrangement of FIG. 2 is similar to that of FIG. I as far as transistor pairs Q IQ and Q3/Q4 are concerned. The output bistate circuit comprising the transistors 5 to Q operates as follows:

The total threshold voltage V of the latter circuit, constituted by the Zener voltage of transistor Q plus the base-emitter voltage of transistor Q, or Q, is higher than the voltage drop across resistor R or R when the voltage provided by source S is within the range fixed by the limits M and m. In this condition neither transistor Q nor Q conducts; thus the output of the arrangement is at the ground potential.

When the voltage provided by source S is above or below the range fixed by the limits M and m, all the current from transistors Q, and Q or Q and Q tends to flow through only one of the resistors R or R respectively. The voltage drop across this one resistor R or R doubles and is higher than the aforementioned threshold voltage V The corresponding transistor Q or Q, is then conducting and the voltage across resistor R jumps up to the emitter voltage of transistors Q and I claim:

I. A marginal switching circuit comprising:

a first transistor;

a second transistor, the emitter of which is coupled to the emitter of said first transistor;

a third transistor, the collector of which is coupled to the collector of said first transistor;

a fourth transistor, the emitter of which is coupled to the emitter of said third transistor and the collector of which is coupled to the collector of said second transistor;

means for providing a first reference voltage level to the base of said second transistor;

means for providing a second reference voltage level, different than said first reference voltage level to the base of said fourth transistor;

means for applying a third variable voltage level to the base of said first and third transistors; and

means coupled between the collectors of said first and second transistors for responding when the level of said third voltage lies outside the range bounded by said first and second reference voltage levels.

2. A marginal switching circuit, according to claim 1, wherein said responsive means is a current energized relay.

3. A marginal switching circuit, according to claim 2, wherein said first and third transistors conduct and said second and fourth transistors are cut off when the level of said third variable voltage exceeds the range bounded by said first and second reference voltage levels thereby providing a current flow through said relay.

4. A marginal switching circuit, according to claim 2, wherein said second and fourth transistors conduct and said first and third transistors are cut off when the level of said third variable voltage is below the range bounded by said first and second reference voltage levels, thereby providing a current flow through said relay.

5. A marginal switching circuit, according to claim 1, wherein said responsive means comprises:

a fifth transistor, the base of which is coupled to the collector of said first transistor;

a sixth transistor, the base of which is coupled to the collector of the second transistor, the emitters of said fifth and sixth transistors being coupled one to the other, and the collectors of said fifth and sixth transistors being coupled one to the other; and

means for providing a fourth reference voltage level to the junction of the emitters of said fifth and sixth transistors.

6. A marginal switching circuit, according to claim 5, wherein said first and third transistors conduct and said second and fourth transistors are cut off when the level of said third voltage exceeds the range bounded by said first and second reference voltage levels, thereby providing that said fifth transistor conducts and said sixth transistor is cut off.

7. A marginal switching circuit, according to claim 5, wherein said second and fourth transistors conduct and said first and third transistors are cut off when the level of said third voltage is below the range bounded by said first and second reference voltage levels, thereby providing that said sixth transistor conduct and said fifth transistor is cut off.

Claims

1. A marginal switching circuit comprising: a first transistor; a second transistor, the emitter of which is coupled to the emitter of said first transistor; a third transistor, the collector of which is coupled to the collector of said first transistor; a fourth transistor, the emitter of which is coupled to the emitter of said third transistor and the collector of which is coupled to the collector of said second transistor; means for providing a first reference voltage level to the base of said second transistor; means for providing a second reference voltage level, different than said first reference voltage level to the base of said fourth transistor; means for applying a third variable voltage level to the base of said first and third transistors; and means coupled between the collectors of said first and second transistors for responding when the level of said third voltage lies outside the range bounded by said first and second reference voltage levels.

5. A marginal switching circuit, according to claim 1, wherein said responsive means compriSes: a fifth transistor, the base of which is coupled to the collector of said first transistor; a sixth transistor, the base of which is coupled to the collector of the second transistor, the emitters of said fifth and sixth transistors being coupled one to the other, and the collectors of said fifth and sixth transistors being coupled one to the other; and means for providing a fourth reference voltage level to the junction of the emitters of said fifth and sixth transistors.