US3582682A - Data bus transfer system - Google Patents

Data bus transfer system Download PDF

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Publication number
US3582682A
US3582682A US790927A US3582682DA US3582682A US 3582682 A US3582682 A US 3582682A US 790927 A US790927 A US 790927A US 3582682D A US3582682D A US 3582682DA US 3582682 A US3582682 A US 3582682A
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US
United States
Prior art keywords
register
switching means
diodes
data bus
bistable
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Expired - Lifetime
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US790927A
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English (en)
Inventor
James C Carroll
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
U S Holding Co Inc
Alcatel USA Corp
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Deutsche ITT Industries GmbH
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Assigned to ITT CORPORATION reassignment ITT CORPORATION CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL TELEPHONE AND TELEGRAPH CORPORATION
Assigned to U.S. HOLDING COMPANY, INC., C/O ALCATEL USA CORP., 45 ROCKEFELLER PLAZA, NEW YORK, N.Y. 10111, A CORP. OF DE. reassignment U.S. HOLDING COMPANY, INC., C/O ALCATEL USA CORP., 45 ROCKEFELLER PLAZA, NEW YORK, N.Y. 10111, A CORP. OF DE. ASSIGNMENT OF ASSIGNORS INTEREST. EFFECTIVE 3/11/87 Assignors: ITT CORPORATION
Assigned to ALCATEL USA, CORP. reassignment ALCATEL USA, CORP. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: U.S. HOLDING COMPANY, INC.
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/411—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only
    • G11C11/4113—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using bipolar transistors only with at least one cell access to base or collector of at least one of said transistors, e.g. via access diodes, access transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/74—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733—Controllable logic circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable

Definitions

  • FIG. 1 illustrates,.in a block diagram, a data transfer system according to the present invention
  • FIGS. 2A, 2Band 2C illustrate the operation of a basic bistable multivibrator or flip-flop in three different modes and show specific collector, base, and emitter biases for each mode
  • FIG. 3 shows the use of single flipaflop circuits from FIGS. 2A-2C in a data transfer system utilizing several registers.
  • FIG. 4 includes a tabulation of the system voltages when a flip-flop, such as is shown in FIGS. ZA-ZC', is incorporated in the transfer system of FIG. 3 and exposed to all combinationsof the three register operating modes, i.e.. normal, transmit.
  • FIG. 5 depicts how integrated circuit logic elements, connected to function as reset-set flip-flops, can be utilized as active elements in the data transfer system.
  • the 01. flip-flops of six registers are shown in block diagram form, while the.
  • FIG. 6A shows how the lCregistersof FIG. 5 are switched into the transmit or receive mode as required by system operation.
  • the operation differs from that depicted in FIG. 2 in that both the ground and the +Vcc busses to the register in question are raised or lowered by one volt with respect to normal bus voltages to effect receiving or transmitting.- This leaves the +Vcc bus to ground bus voltage, in the register proper constant regardless of operating modes
  • FIG. 6B illustrates waveforms. related toFIG. 6A, and
  • FIG. 7 presents a three dimensional representation of a system using at least three registers of two flip-flops each. Data bus interconnecting diodes are shownv while the flip-flop input and outputsteering diodes are shown. as part of the flipflops themselves.
  • registers A, B and C are indicated by dashed blocks with input-output interfaces. represented by flip-flops in blocks AFFl, AFF2, BFF], BFFZ,
  • FIGS. 2A, 2B and, 2C an unusuaT number of details concerning specific operating voltages'and other circuit conditions are shown in FIGS. 2A, 2B and, 2C. Itwill be clear from this'figure that in an operating embodiment of the invention there are three possible operating modes for each registerdetermined' by the voltage on the emitter bus common to all flip-flops in the register in question. These states, as shown respectively in FIGS. 2A, 2B and 2C are normal, transmit and receive. The normal state occurs when the emitter bus is at ground potential 0V and the register can neither transmit its contents to or receive the contents from any other register on thedata bus.
  • the transmit state exists when the emitter bus is at a --lV potential with respect to ground and the register can nondestructively transmit its contents to one or more registers operating in the receive mode .via the data bus.
  • the receive state is present when the emitter bus is at a +1V potential with respect to ground and the register will be set to agree with the trans- CF F1 and. CF F2.
  • the registers are interconnected through the diodes DI, D2...D28, and over the lines L1, L2.. L16 and the busses Bl, B2...B8. Due to the existence of these interconnections it is possible to transfer information from one register to another. Transfer is effected. by increasing the bias potential across three normally nonconductive diodes in series, to enable them to conduct and, transfer data from oneregister to another.
  • gister emitter switch ASW to the emitters (FIG. 2A) of a flip flop AFFl at the same time that another appropriate bias change is applied from a register emitter switch BSW to the emitters of flip-flop BFFI. Assuming that the flip-flops are operating in suitable transmit and receive modes, a change will occur in the bias on diodes D1 and D2 at the same time.
  • FIG. 3 Details concerning the nature of the present invention may be gleaned from a more detailed review of the interconnections and operations of exemplary flip-flops AFF] and BFFl as illustratedin FIG. 3.
  • the labels in FIG. 3 are repeated from FIG. 1 to the extent the same circuits and circuit elements are illustrated in both Figures.
  • the flip-flops AFFl and BFFl are shown to include transistors which have been labeled T1, T2, T3 and T4. Pairs of these transistors, i.e. Tl paired with T2 and T3 paired with T4 serve as the dynamic elements of the flip-flop circuits and are set in their normal condition (see FIG. 2A) initially either by signals from circuits (not shown) in their respective registers or by transferred signals originating from one of the other registers.
  • each of these switches is arranged to connect all of the emitters of the transistors of the flip-flops in the associated register to ground, as indicated by zero on the emitters of FIG. 2A, or to connect them to +1 or1 potentials, as indicated in FIGS. 28 and 2C.
  • the effect of lowering the emitter potentials of transistors in flip-flop AFFI of Register A by one volt (placing it in the transmit mode) and raising the emitter potentials of transistors in BFFl of Register B by 1 volt (placing it in the receive mode) is to initiate the transfer of information (one or zero) from AFFl to BFFI. Bias on the interconnecting diodes at this time is such that current can flow through three diodes in series between AFFl and BFFI.
  • the bases of T2 and T3 must be +0.6 volts relative to the emitters to remain on.
  • T2 and T3 each conducting and with biases of+l 2 volts at terminals A2 and -12 volts at terminals A4 and A6 the effective potentials on their collectors are each +0.2 volts.
  • the registers in order to transfer information in Register A to Register B the registers must be set in Transmit and Receive states respectively.
  • the switch BSW is operated to raise the potential on the emitters in Register B to +1 volt and, at the same time the corresponding switch ASW lowers the voltage applied to the emitters in Register A from ground to 1 volt.
  • the potential on the collector of T2 With a decrease in its emitter voltage to 1 volt, the potential on the collector of T2 will also drop 1 volt to a new value of 0.8 volts (line 8 of FIG. 4).
  • An increase of +1 volt in the emitter voltage of T3 at the same time will cause the base potential of T3 to rise by one volt to a new value of +1.6 volts.
  • the difference between these two potentials is applied over diodes D3, D11 and D13 causing them to conduct.
  • the diodes conduct with a potential drop of 0.6 volt each or a total of 1.8 volts when they are in series.
  • the collector of T2 serves under these circumstances as a current sink to pull down the potential on base T3 to a value limited by the initial potential on the collector of- 0.8 volt plus the +1.8 volts drop across the diodes or one (+1) volt. This causes T3 to turn off.”
  • T3 turns off T4 turns "on" and the conversion of BFFI to the one" state ofAFFl is completed.
  • FIGS. 1, 2A, 2B, 2C and 3 are typical and are only used to facilitate circuit descriptions. This data transfer technique has been applied to RTL, DTL, and TTL integrated circuits, as shown in FIG. 5, with excellent results. Both ready-made flip-flops of the JK and D configurations have been used as well as flip-flops made by cross connecting standard gate functions. In these applications, external steering diodes must be provided when they are not part of the IC proper. When lCs are used, transfer is effected by simultaneously raising or lowering both the positive and negative power supply busses of the register in question by the use of a pulse transformer with a bifilar secondary as shown in FIG.
  • a data bus transfer system comprising a data bus
  • each register including bistable switching means coupled via diodes to the data bus,
  • bias control switching means coupled to said bistable switching means to control the level of the voltage applied by said bistable means to the diodes
  • bistable switching means having three possible modes of operation determined by the level of the voltage applied by the bias control switching means to the bistable switching means, in which a first voltage level causes a normal mode in the bistable during which no conduction can occur in the diodes, a second voltage level causes a transmit mode in the bistable during which the bistable is able to transmit data to the diodes, and a third voltage level produces a receive mode in the bistable in which it is able to receive data over the diodes from registers in the transmit mode.
  • bistable switching means are formed by flip-flop circuits in each register.
  • bias control switching means includes register switches to introduce bias changes to the flip-flop circuits and thereby control the mode of operation of the flip-flop circuits forming the bistable switching means.
  • the bistable switching means in response to the changes in the mode of operation, provide a change in biasing potential across the diodes to enable the transfer of information from one register to another.
  • bistable switching means includes a flip-flop circuit in each register
  • means including the diodes and the data bus connected in series, for interconnecting electrodes of a flip-flop circuit of the first register and a flip-flop circuit of the second register.
  • a data bus transfer system comprising:

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
US790927A 1969-01-14 1969-01-14 Data bus transfer system Expired - Lifetime US3582682A (en)

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US79092769A 1969-01-14 1969-01-14

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US (1) US3582682A (enrdf_load_stackoverflow)
DE (1) DE1964878A1 (enrdf_load_stackoverflow)
GB (1) GB1251634A (enrdf_load_stackoverflow)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3938094A (en) * 1971-08-31 1976-02-10 Texas Instruments Incorporated Computing system bus
US4107554A (en) * 1976-06-30 1978-08-15 International Business Machines Corporation Data bus arrangement for Josephson tunneling device logic interconnections

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3280344A (en) * 1964-07-06 1966-10-18 Sylvania Electric Prod Stored charge information transfer circuits

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3280344A (en) * 1964-07-06 1966-10-18 Sylvania Electric Prod Stored charge information transfer circuits

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3938094A (en) * 1971-08-31 1976-02-10 Texas Instruments Incorporated Computing system bus
US4107554A (en) * 1976-06-30 1978-08-15 International Business Machines Corporation Data bus arrangement for Josephson tunneling device logic interconnections

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DE1964878A1 (de) 1970-07-23
GB1251634A (enrdf_load_stackoverflow) 1971-10-27

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AS Assignment

Owner name: ITT CORPORATION

Free format text: CHANGE OF NAME;ASSIGNOR:INTERNATIONAL TELEPHONE AND TELEGRAPH CORPORATION;REEL/FRAME:004389/0606

Effective date: 19831122

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Owner name: U.S. HOLDING COMPANY, INC., C/O ALCATEL USA CORP.,

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST. EFFECTIVE 3/11/87;ASSIGNOR:ITT CORPORATION;REEL/FRAME:004718/0039

Effective date: 19870311

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Free format text: CHANGE OF NAME;ASSIGNOR:U.S. HOLDING COMPANY, INC.;REEL/FRAME:004827/0276

Effective date: 19870910

Owner name: ALCATEL USA, CORP.

Free format text: CHANGE OF NAME;ASSIGNOR:U.S. HOLDING COMPANY, INC.;REEL/FRAME:004827/0276

Effective date: 19870910