US3512038A

US3512038A - Pin system

Info

Publication number: US3512038A
Application number: US582857A
Authority: US
Inventors: Benjamin Kazan
Original assignee: Xerox Corp
Current assignee: Xerox Corp
Priority date: 1966-09-29
Filing date: 1966-09-29
Publication date: 1970-05-12
Anticipated expiration: 1987-05-12
Also published as: GB1201497A; DE1614392A1

Description

May 12, 1970 B. KAzAN 3,512,038

PIN SYSTEM Filed sept. 29, 196e United States Patent O 3,512,038 PINSYSTEM BenjaminKazan, Pasadena, Calif., assignor to Xerox Corporation, Rochester, N.Y., a corporation of New York Filed Sept. `29, 1966, Ser. No. 582,857 Int. Cl. H01j 29/41 ULS. Cl. 315-12 20 Claims This invention relates generally to graphic imaging apparatus and more'particularlytoapparatus wherein the electrical condition of conductive elements in a matrix is made to vary on an elemental basis in accord with an information input to the apparatus.

At present numerous devices are available in which matrices of electrically conductive pins are by some means or other activated to effect electrical variations among the pins corresponding to an optical or electrical input to the device. Asimple and common approach, for example, is shown in U.S. Pat. No. 3,186,839 in which a plurality of such pins are mounted in an insulating sheet, each pin -being in series with a photoconductive element. When an electrical potential is applied across the sandwiched structure and the apportioned photoconductor in series with an individual pin is impinged by light, that pin is electrically activated and presumably may be utilized to deposit a point charge on an adjacent dielectric web. If desired, the resulting charge pattern may be thereafter developed in accord with standard xerographic techniques to produce a visible replica of the input pattern. Numerous problems are associated with operating this type of apparatus, but` even at its best such device is only an image converter and requires a constant input-and in an optical formin order to produce an output.

Another very common type of device-but one of much greater complexity-is the well known cathode ray pin tube` of which several designs are commercially available. In general such devices are used to produce a charge pattern on a moving dielectric web in accordance with an electrical input signal supplied to the tube control grid. In addition to requiring that the input be electrical in form such tubes require high potentials of the order of hundreds of volts, and do not usually have storage capability.

In` accordance with the foregoing it is one object of the present invention to provide imaging apparatus adapted to produce an electrical output at a pin matrix in accordance` with an electrostatic charge pattern established and in effect stored at an input surface of the device.

It is a further object of the present invention to provide imaging apparatus in which the electrical properties of a lpin matrix may be varied in accordance with an electrostatic charge pattern established at an input surface ofthe device, which charge pattern may optionally be established through electrical or optical means.

It is an additional object of the present invention to provide imaging apparatus wherein the electrical character of pin members of a conductive pin matrix are varied in accordance with an electrostatic charge pattern established on a separate control layer, and wherein the pin matrix may be utilized for production of additional images without in any way altering the electrostatic charge pattern present at the control surface.

It is yet a further object of the present invention to provide` a novel pin tube structure having low voltage requirements, and which is furthermore adapted to store an input image whereby multiple xerographic copies may be produced at the tube face without substantially affecting the electrostatic pattern stored therein.

Now in accordance with the present invention these objects, and others as will become apparent upon reading ofthe ensuing specification, are achieved by means of a 3,512,038 Patented May 12, 1970 ICC structure including an insulating input surface upon which an electrostatic charge pattern may be established either through direct electrical deposition or-where the surface is suitably composed-via optical projection of a light pattern. The resulting electrostatic charge pattein serves by means of iield eect action to selectively establish a conductivity pattern in an adjacent semiconductor. A matrix of conductive pins and an electrically conductive grid are positioned with respect to each other such that portions of the semiconductor material now possessing the varying conductivity pattem are interposed between Y' individual of the pins and adjacent elements of the grid. Accordingly, if the grid is for example electrically grounded, an impedance pattern will be established between the pins and ground in accord with the conductivity pattern in the semiconductor which in turn reflects the electrostatic charge pattern present on the insulating input surface of the device.

Such a variable impedance pattern may then be readily used to produce images or the like corresponding to the electrostatic pattern present at the insulating surface in a variety of ways, many of which are well known in the art of xerography. Since the charge pattern present at the insulating surface referred to is in no way in contact with either the conductive grid or the pin matrix, which is to say that the charge pattern serves merely to control the electrical state of the pins, such pattern is in no way dissipated or otherwise disturbed by the use to which such pins may be put. It follows therefore that a device of the nature described possesses storagability in a very simple manner for information input supplied to the insulating surface, and it also follows in consequence that numerous and successive output images or the like may be obtained from such a structure without effecting renewal or reintroduction of the pattern present at the insulating input surface.

A fuller understanding of the present invention may now best be gained by a reading of the following detailed specification and by a simultaneous examination of the drawings appended hereto in which:

FIG. 1 diagrammatically illustrates a basic embodiment of the present invention.

FIG. 2 illustrates the manner in which the FIG. 1 apparatus may be utilized to produce a developable image output.

FIG. 2A schematically depicts on a much magnified scale a portion of the apparatus shown in FIGS. l and 2.

FIG. 3 illustrates a variation on the FIG. l embodiment.

FIG. 4 illustrates a form of the present invention wherein electro deposition from an electrolyte is utilized to achieve an image output.

FIG. 5 diagrammatically illustrates the embodiment of the present invention into a novel pin tube structure possessing both storability and low voltage requirements.

In FIG. l a simplified cross section View is shown of a basic embodiment of the instant invention. The structure 3 is seen to include an insulating plate 5 containing a matrix 2 of conducting pins 7 extending therethrough. These pins 7 may protrude slightly from the outside face of the plate as this surface will normally be brought into contact with a printing sheet, dielectric web or the like when the structure is utilized for imaging purposes. The other ends of pins 7 terminate flush with the inner face of plate 5, thereby presenting a matrix of conductive points at this planar face. The insulating layer 5 can be formed from any of numerous materials having high dielectric breakdown properties and may for example be thought of as comprising glass.

A semi-conductor layer 9 is in intimate contact with the iunerface of plate 5 and hence is also in contact with the exposed flush ends of pins 7. The semiconductor layer 9 3 Will be chosen with some Variation depending upon the impedance range that one ultimately desires to establish at the pin matrix 2. Thus, for example, one may choose a relatively conductive type of material such as zinc oxide, or alternatively one may utilize a relatively low conductivity semiconductor material such as cadmium sulfide, cadmium selenide or arsenic sulfide. The semiconductor layer 9 will ordinarily be quite thin and will be deposited upon the innerface of plate 5 in such a manner that a low resistance contact between the flush ends of pins 7 and the semiconductor layer is assured. Well-known thin film techniques may be utilized for such purposes including sputtering and evaporation in vacuum methodology. Typically layer 9 will have a thickness less than 1 mil; however superior electrical properties are usually achievable where the layer is held thinner. Thus for example the layer 9 may suitably comprise a micro-crystalline layer of cadmium sulfide having a thickness of the order of 1 micron or so.

At the surface of semiconductor layer 9 and adjacent to the pin matrix 2 a fine conductive grid structure 11 is established in such a manner that a low resistance contact is made between this structure and the semiconductor. With many semiconductors as, for example, cadmium sulfide, this grid structure may be formed from evaporated gol-d or the like. Vacuum deposited copper may also be utilized, or as another and concrete example indium may be electroplated upon a cadmium sulfide surface from an indium uoroborate solution. In the depiction of FIG. 1 it may be assumed that grid structure 11 has a parallel line structure. For reasons that will become clearer in what ensues the grid structure 11 is deposited over semiconductor layer 9 as a series of very fine lines, so that the open space in the grid is very large, on a percentage basis approaching in a representation case 80% of the total grid area.

Finally to complete the structure 3 a highly insulating layer 13 is established overlying the semiconductor layer 9 and adjacent conductive grid 11. This insulating layer may by way of example suitably comprise a thin evaporated layer of silicon monoxide or magnesium fluoride, either element of which is so highly insulating as to retain a charge pattern deposited thereon for many hours or even days. Layer 13 may further be chosen to be an insulating photoconductor such as a thin layer of vitreous selenium or the like; however in such event, an additional insulating layer of about 1 micron may prove desirable between layers 9 and 13 -to prevent charge injection from the photoconductor to the semiconductor-the necessity for such an extra layer will depend on the particular photoconductor utilized. Such a choice enables a charge pattern to be established on layer 13 by means of an optical input to the previously uniformly charged layer. It will be appreciated too that where layer 13 does possess photoconductivity and the ability as well to retain charge patterns on its surface for reasonable durations of time, the functions of

layer

9 and 13 may be taken over by a single layer. This aspect of the invention will be discussed further in connection with FIGURE 3.

The present inventive structure is utilized by establishing at the outside surface of insulating layer 13 an electrostatic charge pattern representative-in a general sense-of input data. Such a pattern may be established in numerous ways and will be of a polarity chosen in accord with the nature of the particular semiconductor material utilized for layer 9. Where a negative electrostatic pattern is desired for layer 13 the pattern may readily be laid down by direct electron deposition. For such purposes a stream emanating from an electron gun may be made to impinge upon the surface of layer 13 in an evacuated chamber. Modulation of the electron stream as it sweeps across the surface of layer 13 in a rastered manner achieves the desired pa-ttern. Positive patterns can be achieved by use of similar electron gun techniques, provi-ded conditions and compositions are utilized to achieve adequate secondary emission at the surface layer 13.

The pattern may also be established in a quite simplified fashion by deposition of charged particles emanating from a positive or negative corona source positioned adjacent but spaced from layer 13. The conductive grid structure 11 may Ibe grounded during such a charging operation to assure the presence of an accelerating electric eld between the corona source and the insulator. A conductive stencil positioned between the corona source and insulating layer 13 may be utilized here to selectively intercept particles whereby charge is deposited in desired character configurations or so forth.

Another simple technique, and one that like corona charging requires no evacuated atmosphere, utilize dielectric breakdown between the layer and a shaped conducting character or the like separated from layer 13 and its grounded conductive grid 11 to deposit charge on the surface of layer 13 corresponding to the shaped characters utilized. Processes of this latter type have become generally known under the acronym TESI printing, and numerous references may be cited to systems of this general type including, for example, U.S. Pat. Nos. 3,060,432 and 3,060,481.

The manner in which the present structure operates to produce an output image faithfullyV representative of the electrostatic charge pattern present at layer 13 may now be readily understood. Referring specifically to FIG. 2 a structure 3 is shown having an electrostatic charge pattern 15 present upon the ou-tside face of insulating layer -13. The pattern as would be expected varies across the face of the layer as is suggested by the non-uniform application of positive charge `symbols to the face of this layer. With the grid structure 11 connected to ground by lead 17 an insulating receptor sheet 19 which may be a dielectric web, a piece of paper, or so forth, is positioned over the conductive backplate 20 and brought into contact with the pins 7 of pin matrix 2. The sheet 19 has been previously charged to a uniform negative potential as is suggested by the charge pattern depicted schematically by reference numeral 21. Structure 3 now functions so as to vary the impedance between individual pins 7 and ground lead 17 in accordance with charge pattern 15 so that varying degrees of discharge of the uniform charge pattern 21 occurs through the pins 7, thereby establishing an electrostatic charge image upon the surface of 19 which is a replica of the pattern 15 present on insulating layer 13.

Alternatively the sheet 19 may be brought into contact with the matrix 2 without prior application of charge. In this instance a DC potential may be impressed upon backplate 20, lwhereby charge build-up is effected on sheet 19 via the various individual pins in a manner analogous to that described for dissipation of an initially uniform charge. In this latter instance however it Will be observed that an inverse effect is brought about in that a pin associated with a low impedance path `will effect higher charge build-up than a pin associated with a high impedance path. Relative to an image obtainable by the first technique described, the resulting image in this latter technique is obviously an inverseor negative The variation in impedance path to ground occurs in accordance with the charge pattern 15 because by field effect action the pattern 15 selectively controls the electrical conductivity in semiconductor layer 9 in accord with pattern 15. For the embodiment depicted in FIG. 2 this type of action is basically quite similar to what takes place in an insulated-gate field effect transistor. More specifically we may consider the case where as has been previously suggested as one possibility, layer 9 comprises a thin layer of the semiconductor cadmium sulfide. Each of the pins 7 by virtue of its proximity to the charge on the sheet 19 serves in effect as a source Similarly the grounded grid structure 11 effectively acts as a drain With a positive polarity charge pattern as shown in FIG. 2 the conductivity in volumes of the semiconductor layer 9 immediately below charged areas Will be increased by attraction of electron carriers so that the impedance path between associated pins 7 below such volumes and ground is correspondingly increased. The result here is thus to effectively discharge areas on receptor sheetl 19 immediately below charged areas on insulating layer 13. Like the transistor structure of which the device is reminiscent, a negative bias may also be utilized on surface lli-which is to say that the electrostatic charge pattern deposited thereon may be of negative polarity. With the connections otherwiselas shown the effect of charged areas on layer 13` will then be such as to repel electrons out of the semiconductor layer 9 `so that decreased conductivity results insuch affected areas. In this manner a charge image may be established upon receptor sheet 19 which ignoring the polarity of the charge is in terms of charge variation directly in accord with pattern rather than in inverse accord as` would be the case where positive charge is utilized for pattern 15.

After sufficient time has transpired for the output charge` pattern to be formed upon sheet 19 the sheet is removed and where desired may be developed according to methods commonplace in the art of xerography. In the simplest instance the visual pattern may thus be produced `by applying to the charge pattern now on receptor sheet `19 a colored particulate material which selectively adheres, in those areas of high charge density.

It hasibeen previously indicated that grid structure 11 in FIG. `2 is initially deposited as a series of very ne lines, with the object of maintaining very high percentages of open areas in the plane` of the grid. The reason for this is now obvious in view of the fact that operation of struct-ure 3 is dependent upon field-effect action. This is to say that in order to achieve maximum control by the charge patternlS it is desirable that the associated electric field penetrate semiconductor layer 9 to a high degree. In this same connection it will of course be appreciated that the thickness of layer 9 has been -greatly exaggerated in FIG. 2 for the purposes of illustration. In practice the dimensionalthickness of this layer lmay be so slight that the separation between a given pin and an adjacent grid element is principally in a lateral direction, i.e., parallel to the planeof layer 9 rather than in a direction transverse to such layer. This aspect of the construction is illustrated in FIG. 2A showing a representative pin 7A and on a somewhat more realistic scale than in FIG. 2 the semiconductor layer 9. Thus it is seen here that the separation between a particular pin 7A and a given grid element 11A is principally the lateral distance 23. It is thus true that ther electric field provided by pattern 15 is essentially transverse to the flow of current in semiconductor layer 9 in accord with the usual case for field-effect devices.

In this same connection it may be observed that a slight variation on the FIGS. 2 and 2A structure is achievable by depositing grid 11 on the alternate side of layer 9- which is to say directly on plate 5. The overall operation of the device in such a case remains as has been specified. However somewhat greater sensitivity to the charge pattern 15 is gained in that the electric field produced by the latter is even more transverse to current flow in layer 9 than Wasthe case with the FIGS. 2 and 2A geometry.

The apparatus shown in FIGS. 1 and 2 has -been particularly` described for the case where the electrostatic charge `pattern established upon insulating layer 15 is derived through non-optical means. It will be appreciated by those skilled in the art, however, that one may effectively employ as the insulating material in layer 13 a compositionwhich exhibits in addition to insulating characteristics substantial photoconductivity. In this manner one may establish the charge pattern `15 through intermediate use of an optical input. Thus the layer 13 rnay suitably comprise a thin coating of vitreous selenium. In such case the charge pattern 15 `may be established by methods well known to the art of xerography. That is to say that one may initially provide a uniform positive or negative charge on such a selenium surface in darkness and thereafter with grid 11 grounded may expose the photosensitive surface to the optical pattern of the light and shadow that one desires to ultimately reproduce. The light source is then inactivated and the charge pattern produced by this method is then utilized in precisely the manner as has been set forth for the case where charge is provided more directly.

In FIG. 3 a variation upon the FIGS. 1 and 2 embodiment is shown which eliminates the necessity for separate semiconductor and insulating layers. In FIG. 3 the pin matrix 2 and insulating plate 5 are identical with corresponding elements discussed in connection with FIGS. 1 and 2. The conductive grid 11 is similar to that discussed in connection with the FIG. 1 embodiment; however, in the present instance the conductive grid is deposited-in a manner such as has been previously set forth-directly upon the face of plate 5; that is to say, that in this case grid 11 is essentially coplanar with the ends of pin 7. A layer of storing semiconductor material 23 is now deposited directly over the gridll and plate 5 at the surface of which are the exposed ends of pin 7. As in previously described embodiments this deposition process is carried forth in such a manner that a low resistance contact is made between the semiconductor material and the electrically

conductive elements

7 and 11.

For purposes of the present discussion the term storing semiconductor materials refers to members of a subclass of field-effect semiconductors which in addition to exhibiting conductivity changes in response to an electric eld imposed thereon-as do all the field-effect semiconductors--exhibit as well the ability to retain electrostatic charge on their surface, and to dissipate such charge in response to impinging radiation. Zinc oxide is the best known example of such material; however in addition to zinc oxide there are other materials such as lead oxide and cadmium oxide which exhibit similar characteristics and which are generally suitable for use in formation of layer 23.

Where the preferred zinc oxide composition is utilized for layer 23 it may be deposited by any convenient means including spraying. In a typical instance a coating having a thickness of approximately 1 mil is desirable. This coating composition may have the same formulation as that used for electrophotographic paper coating. A specic example of such coating composition is as follows:

Material Pounds per gallons Zinc oxide 533.000 Pliolite S5D 1 107.000 Chlorinated paraffin 27.000 Toluene 533.000 yBromophenol blue 0.021 Methyl green 0.016 Acridine orange 0.016

1 Pliolite S-D is a styrene butadine copolymer produced by the Chemical Division of the Goodyear Tire and Rubber C0., Akron, Ohio. A detailed discussion of the aforementioned zinc oxide composition is set forth in the publication titled Tech- B-ook Facts, Formulations PLS-37, Chemical Division Goodyear Tire and 'Rubber Co., Akron, Ohio.

Besides substantially pure zinc oxide a wide variety of zinc oxide compositions can be utilized which consist essentially of zinc oxide dispersed in a non-conductive binder resin. Zinc oxide to non-conducting resin ratios as set forth in the aforementioned composition is approximately 5:1. However, zinc oxide concentration may be increased so that the ratio is increased up to 50:1 or decreased so that the ratio is about 3:1. Similarly various dyes and sensitizers may be added to the composition to extend the spectral response of the composition with the ones inwthe table noted being typical.

Layer 23 can alsobe deposited by many of the wellknown thin film techniques including sputtering and evaporation in vacuum. In these latter cases the zinc may be deposited in an elemental form and converted to the oxide by subsequent heating. Much thinner layers can be deposited by these latter techniques than is possible by spraying; thicknesses can effectively range down to the vicinity of several microns.

The apparatus depicted in FIG. 3 may be used in essentially the same manner as has been described in connection with the prior embodiments. As a rule an initial deposition of charge upon the surface of layer 23 however is effected by use of negative ion corona in an atmosphere including oxygen. Where such technique is utilized the charge deposition is principally effected by negative oxygen ions which then appear to create blocking contacts on the storing photoconductor surface whereby the dark conductivity of layer 23 is greatly decreased. The negative charge pattern may either be established upon the storing semiconductor layer by the direct methods that have been previously alluded to or alternatively the photoconductive properties of zinc oxide itself may be utilized to directly establish a charge image in accord with an optical input.

In the situation where a negative charge pattern is directly applied to the layer 11 the mechanism of operation of device 4 is essentially similar to the operation of the FIG. 1 apparatus 3. That is to say that the presence of negative charge at points on layer 23 acts by iield effect action to repel negative carriers in the vicinity of the underlying grid and pin elements, as a result of which conductivity in the volumes of semiconductor so affected is reduced, and the to-ground impedance path presented to associated pins correspondingly increased. As has been previously discussed in connection with FIG. 2A it will once again be appreciated that the thickness of layer 23 has been greatly exaggerated and that in reality the field imposed on the semiconductor material in the vicinity of the conductive elements is very appreciable. It may be additionally noted that the structure of FIG. 3 is perhaps more closely analogous to the conventional field effect transistors in that the conductive elements 7 and ll-corresponding to source and drain in the analogous transistors-are now practically coplanar with the electric eld imposed by the charge distribution on layer 23 being almost precisely transverse to such common plane.

In the case where the photoconductive properties of layer 23 are utilized to enable formation of the controlling electrostatic image, the surface of layer 23 is initially corona charged by a negative source. Thereafter the surface electrostatic charge is selectively dissipated by the radiant energy image whose reproduction is desired.

FIG. 4 illustrates a form of the present invention wherein electro-deposition from an electrolyte is utilized to achieve an image output. In general the apparatus therein depicted resembles prior embodiments and corresponding parts are similarly identified. It is to be noted in the present instance however that the pins 7 comprising matrix 2 no longer extend beyond face 37 but terminate flush therewith in a manner similar to the way in which such pins terminate at their opposite ends. The output image in the present embodiment is produced by electro-deposition, preferably of metallic ions from a-n electrolyte 35, contained in a cell, the electrodes of which are the pin matrix 2 and the conductive face 39 of transparent glass electrode 41. The latter electrode may suitably comprise a sheet of glass provided with a thin coating of conductive tin oxide, this type of material being available commercially from the Corning Glass Works, Corning, N.Y., under the trade name NESA.

The apparatus depicted in FIG. 4 may be utilized in a number of ways. In all instances however, and as in prior embodiments, a charge pattern is established upon insulating layer 13 which pattern acts by eldeffect control of the semiconductor layer 9 conductivity to vary the conductive path between individual pins 7 and adjacent conductive grid elements 11. In the present instance a source of DC potential 43 is provided which through intermediate use of a reversing switch 45 may be switched in polarity so that the current through the electrolytic cell is in a chosen direction. In a typical instance the electrolyte 35 may comprise a transparent metal electrolyte such as an acid solution of a metallic salt e.g. a solution of copper perchlorate Cu(ClO)4 with 10% HC1O4 with a concentration of 1.5 g./l. of Cu; however various other forms of electrolytes may be used as well.

Once the charge pattern 15 is established the conductive grid 11 may be connected to the negative side of potential source 43 whereby individual pins 7 of pin matrix 2 will to varying degrees be raised to negative potentials with respect to conductive surface 39 of glass plate 31. Under such conditions the metallic ions present in electrolyte 35 will deposit upon the adjacent surface of plate 5 in varying degrees according to the controlling charge pattern 15. Once sufcient density of the depositing pattern is reached, the reversing switch 45 is thrown to a neutral position, and the resulting image may be viewed directly through the transparent glass plate 41. If desired the image may thereafter be readily destroyed by merely reversing polarity of switch 45 for a period sufficient to return the deposited metallic ion to solution without substantial deposition at the now cathodic surface 39. It may be noted at this point that more sophisticated schemes can be used to avoid the reverse deposition problem. Reference may be made, for example, to U.S. Pat. No. 3,153,113 relating to an electroplating light valve, wherein utilization of a salt bridge layer in a double electrolyte sandwich structure obviates the problem of reverse deposition.

The apparatus depicted in FIG. 4 may be utilized in other modes in addition to that which has ibeen indicated. IFor example, where electrolyte layer 35 is very thin, it is practical to utilize the conductive layer 39 as the cathode or imaging surface. This is to say that where the distance separating the conducting surface 39 and adjacent pin elements 7 is very small, metallic ions streaming across the cell will deposit in loci quite close to the end of the pin from which the ion derives its field-accelerated energy. In a related mode of operation surface 39 may be covered with a conductive sheet or a thin semiconductivity sheet. With a negative potential connected to plate 41, and with as previously suggested a very thin electrolyte layer, image deposition may then be carried out directly on the intervening sheet. Alternatively an insulating or semiconductivity sheet may be placed over face 37, whereupon regardless of the cell width dimensions image deposition may be made to occur on the sheet rather than on the face 37. It will be appreciated in view of discussion of prior embodiments that the operation of the present device is such that depending upon the particular insulator comprising layer 13 numerous such sheets may be imaged without substantially dissipating charge pattern 15.

FIG. 5 diagrammatically illustrates the embodiment of the present invention into a novel cathode ray pin tube structure possessing both storaga'bility characteristics and low voltage requirements. The pin tube 51 therein is seen to comprise the evacuated envelope 53 in which the conventional elements appear including a cathode 55, a cathode potential supply 57, illustratively operating at about 5 kilovolts, a control grid 59, focusing electrodes 61, deection electrodes 63, and collimating electrodes 64; all these elements are of conventional construction. The face plate of the tube 51 comprises essentially the apparatus depicted in connection with FIG. 1 and in accordance with that figure similar parts are correspondingly labeled. Slightly spaced from the insulating layer 13 now appears a secondary electron collector grid 65 the function of which is to control the equilibrium charging potential of insulating layer 13 when scanned by the electron beam emanating from cathode 55. The collector grid is provided with lead 67 which may be optionally connected to a potential of about -10 volts in the erase mode of operating the apparatus, or to a ground potential in the write mode.

In operation collector grid 65 initially is connected to a low negative potential such as the -10 volts illustratively shown. The surface of insulator 13 is then scanned with the electron beam through collect or grid 65 at electron beam energies lying between the first and second cross-overs of the secondary emission characteristic curve of the material comprising insulator 13, so that a uniform potential of about -10 volts is `established on the surface of layer 13. Subsequently the collector grid 65 is connected to ground in the write mode. The electron beam `is1 now made to scan `the surface of layer 13 in a rastered` manner as the beam is intensity modulated by'video input i'information'-injected at terminal 68 to control grid 59.* An electrostatic charge pattern illustratively varying from -10 to 0 volts results on layer 13 that is in accord with the modulating input applied at terminal 67.

With this electrostatic pattern now stored on insulating layer 13 the structure may be utilized in precisely the manner as has been set forth in connection with previous ernbodiments of the invention, or in addition yet other techniques-may be` used. For example, under the field-effect control of the electrostatic pattern now present on layer 13, `and with conductive grid 11 grounded as indicated, a uniform charge may be applied to face plate 69 by means of a corona source or the like. After a short period of time the uniform charge distribution will have been selectively dissipated due to the varying conductivity paths to ground presented to the several pins 7. The switch 70 may then be opened to prevent further dissipation of the deposited charge and a xerographic toner or the like may be dusted upon the face plate directly to produce a visible image in accord with the video input previously supplied. This image then maybe transferred to paper or the like by techniques well known in the art of xerography, such as by positioning a paper sheet against the face plate and applying a uniform potential to the back surface thereof.

As was the case with prior embodiments the instant one is again such that the charge pattern established upon layer 13 may be retained for high periods of time depending only upon the choice of the insulating material utilized. Accordingly, numerous output images may be produced by` means of the present apparatus Without renewing the stored electrostatic pattern. It may be noted further, however, that the instant embodiment paricularly lends itself to rapid changing of the stored patterns since control and establishment of such patterns is entirely by electronic means. The stored information, for example, may be a single frame of a TV `image which in a typical instance may be recorded by the tube in the order of 176,0 of a second.

While the present invention has been particularly described in terms of specific embodiments thereof it will be understood that in view of the present disclosure numerous deviations therefrom and modifications thereupon may be readily devised by those skilled in the art. Accordingly the present invention is to be broadly construed and limited only by `the scope of the claims now appended hereto.

What is claimed is:

1.\A structure for establishing an impedance pattern in a pin matrix corresponding to an image-configurated electric field comprising:

(a) a matrix of mutually insulated electrically conductive pins, said pins being disposed in electrical circuits to a common point including a common fieldeffect semiconductor layer, portions of said layer being in series with the electrical path of individual of said pins to said common point, and

(b) means to impose `an image-conligurated electric field upon said semiconductor layer whereby the conductivity of said layer is varied in accord with said field and whereby the electrical impedance to ground of said pins is varied in accordance with said field.

2. Apparatus according to claim 1 wherein said semiconductor layer is adapted to receive an electrostatic charge pattern thereon, said pattern serving as the source for said electric field.

3. Apparatus according to claim 1 wherein said means for imposition of said field comprise an insulating layer positioned adjacent said semiconductor layer, said insulating layer being adapted for establishment thereon of an electrostatic charge pattern, said pattern serving as the source for said field.

4. A structure for establishing an impedance pattern on a pin matrix corresponding to an electrostatic charge pattern ona control surface comprising:

(a) an insulating layer having a plurality of electrically conductive pins extending therethrough;

(b) a control surface adapted for establishment thereon of said electrostatic charge pattern;

(c) a field-effect semiconductor layer adjacent said control surface and adjacent to and contacting said insulating layer and the ends of said pins; said semiconductor layer being adapted to respond to the congurated electric field produced by said charge pattern by varying the electrical conductivity at portions of said layer in correspondence with said field;

(d) an electrically conductive grid spaced from said pins, said grid being separated from said pins by semiconductor material of said layer, whereby the impedance of the electrical path between said pins and said conductive grid varies in accord with said electric field.

5. A structure according to claim 4 in which a second insulating layer is positioned in contact with the face of said semiconductor layer non-adjacent said pins, the noncontacting face of said second insulating layer serving as said control surface.

6. A structure according to claim 4 wherein said semiconductor layer is adapted to have an electrostatic charge pattern established thereon, whereby said control surface bounds said semiconductor layer.

7. A structure according to claim 6 wherein said semiconductor layer comprises a storing semiconductor.

y8. A structure according to claim 7 wherein said storing semiconductor comprises zinc oxide.

9. A structure for establishing an impedance pattern on a pin matrix corresponding to an electrostatic charge pattern on a control layer comprising:

(a) a first insulating layer having a plurality of electrically conductive pins extending therethrough;

(b) a semiconductor layer adjacent to and contacting said insulating layer and the ends of said pins;

(c) an electrically conductive grid spaced from said pins, points on said grid being separated from said pins by semiconductor material of said layer; and

(d) an electrically insulating control layer positioned adjacent the side of said semiconductor layer nonadjacent to said rst insulating layer, said control layer being adapted to have said electrostatic charge pattern formed thereon, said charge pattern serving to control by field-effect action the conductivity of adjacent portions of said semiconductor layer whereby the impedance of the electrical path between said pins and said conductive grid varies in accord with said charge pattern.

10. Apparatus according to claim 9 wherein said electrically insulating control layer is further a photoconductor whereby said electrostatic charge pattern may be established on said layer by the selective dissipation of uniform charge by an optical input of light and shadow.

11. A cathode ray pin tube adapted to produce an impedance pattern on a pin matrix corresponding to stored input information comprising:

(a) an evacuated glass envelope including an insulating end plate having a plurality of electrically conducting pins extending therethrough;

(b) a semiconductor layer adjacent to and contacting said end plate and the ends of said pins;

(c) an electrically conductive grid spaced from said pins, points on said grid being separated from said pins by semiconductor material of said layer;

(d) an electrically insulating control layer positioned adjacent the side of said semiconductor layer nonadjacent to said end plate, said control layer being adapted to have an electrostatic charge pattern formed thereon, said charge pattern serving to control by field effect action the conductivity of adjacent portions of said semiconductor layer whereby the impedance of the electrical path between said pins and said conductive grid varies in accord with said charge pattern; and

(e) electron Ybeam writing means positioned within said evacuated envelope and adapted to deposit a charge pattern on said insulating control layer in accord With'said input information.

12. Apparatus according to claim 11 in which said electron beam writing means includes an electron stream source intensity modulatable in accord with said input information, and a secondary electron emission collector grid spaced from said insulating control layer, said collector grid being associated with switching means for setting the potential thereof at one of two discrete levels indicative of the upper and lower voltage limits of the potential distribution desired in said electrostatic charge pattern, whereby one of said two levels may be utilized with said electron beam source operative to uniformly charge said control layer and the other said two levels may be utilized with said beam operative and intensity modulated to selectively discharge said layer to produce said electrostatic charge pattern.

13. The structure of claim 4 wherein said grid is on the opposite side of said field-effect semiconductor layer from said insulating layer having the plurality of electrically conductive pins extending therethrough.

14. The structure of claim 4 wherein said grid is in direct contact with the surface of said insulating layer adjacent said yfield-effect semiconductor layer.

15. The structure of claim 4 wherein said grid is laterally displaced with respect to the ends of said pins adjacent said eld-eifect semiconductor layer.

16. The structure of claim 4 wherein the ends of said 12 pins` adjacent said field-effect semiconductor layer are ush with the surface of the insulating layer through which said pins extend.

17. The structure of claim 16 wherein the other ends of said pins protrude slightly from the opposite surface of said insulator layer.

18. The structure of claim 5 wherein said insulating layer is a photoconductive insulator.

19. A method of forming a latent electrostatic image on an insulator surface comprising providing the structure of claim 4, forming an electrostatic charge pattern on said control surface, bringing a uniformly charged insulator into contact with the exposed ends of said pins whereby a portion of the uniform charge on said insulator is dischargedcthroughrY at least some of said pins, said discharge being controlled by the eld-effect action of said electrostatic charge pattern on said `field-effect semiconductor layer, whereby there is formed a latent electrostatic image on said insulator.

20. A method of forming a latent electrostatic image on an insulator surface comprising providing the structure of claim 4, forming an electrostatic charge pattern on said control surface, bringing an uncharged insulator into contact with the exposed yends of said pins, impressing a direct current potential on the reverse side of said insulator whereby a corresponding charge will be induced on the side of said insulator in contact with said pins and a portion of said induced charge will be discharged through said pins, said discharge being controlled by the lfield-effect action of said electrostatic charge pattern on said field-effect semiconductor layer, whereby there is formed a latent electrostatic image on said insulator.

References Cited UNITED STATES PATENTS 3,398,317 8/1'968 Shoulders 313-68 XR 3,401,294 9/1968 Cricchi et al. 315-12. XR 3,433,996 3/1969 Carnahan et al 315-12 RICHARD A. FARLEY, Primary Examiner J. P. MORRIS, Assistant Examiner U.S. Cl. X.R.

Claims

1. A STRUCTURE FOR ESTABLISHING AN IMPEDANCE PATTERN IN A PIN MATRIX CORRESPONDING TO AN IMAGE-CONFIGURATED ELECTRIC FIELD COMPRISING: (A) A MATRIX OF MUTUALLY INSULATED ELECTRICALLY CONDUCTIVE PINS, SAID PINS BEING DISPOSED IN ELECTRICAL CIRCUITS TO A COMMON POINT INCLUDING A COMMON FIELDEFFECT SEMICONDUCTOR LAYER, PORTIONS OF SAID LAYER BEING IN SERIES WITH THE ELECTRICAL PATH OF INDIVIDUAL OF SAID PINS TO SAID COMMON POINT, AND (B) MEANS TO IMPOSE AN IMAGE-CONFIGURATED ELECTRIC FIELD UPON SAID SEMICONDUCTOR LAYER WHEREBY THE CONDUCTIVITY OF SAID LAYER IS VARIED IN ACCORD WITH SAID FIELD AND WHEREBY THE ELECTRICAL IMPEDANCE TO GROUND OF SAID PINS IS VARIED IN ACCORDANCE WITH SAID FIELD.