US3489962A - Semiconductor switching device with emitter gate - Google Patents

Semiconductor switching device with emitter gate Download PDF

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US3489962A
US3489962A US602837A US3489962DA US3489962A US 3489962 A US3489962 A US 3489962A US 602837 A US602837 A US 602837A US 3489962D A US3489962D A US 3489962DA US 3489962 A US3489962 A US 3489962A
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region
contact
main
gate
auxiliary
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James E Mcintyre
Dante E Piccone
Istvan Somos
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General Electric Co
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General Electric Co
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D18/00—Thyristors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1203—Rectifying Diode
    • H01L2924/12032—Schottky diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1301—Thyristor
    • H01L2924/13034—Silicon Controlled Rectifier [SCR]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Definitions

  • This invention relates generally to solid-state electric current switches of the multilayer semiconductor type, and more particularly it relates to a high power silicon controlled rectifier (known generally as a thyristor or SCR) having improved switching characteristics.
  • a high power silicon controlled rectifier known generally as a thyristor or SCR
  • an SCR typically comprises a thin, broad area disc-like body having four distinct layers of semiconductor material (silicon), with contiguous layers being of different conductivity types to form three back-to-back PN (rectifying) junctions in series.
  • a pair of main current-carrying electrodes (anode and cathode) are provided in low resistance (ohmic) contact with the outer surfaces of the respective end layers of the silicon body, and for triggering conduction between these electrodes the body is normally equipped with at least one control electrode (gate contact).
  • the silicon body is sealed in an insulating housing, and it can be externally connected to associated electric power and control circuits by means of its main and control electrodes.
  • an SCR When connected in series with a load impedance and a source of forward bias voltage, an SCR will ordinarily block appreciable current flow between its anode and cathode until a small gate current of suitable magnitude and duration is supplied to the control electrode, whereupon it abruptly switches from a high impedance to a very low impedance, forward conducting (turned on) state. Subsequently the device reverts to its blocking (turned off) state in response to load current being reduced below a given holding level.
  • the SCRs of primary interest herein are those having relatively high power ratings: when off they can successively block high reverse voltages of the order of 2,000 peak reverse volts; when on they can normally conduct high forward currents of the order of 250 amperes (average) or more. Of interest also are high frequency (e.g., 3,000 Hz.) ISCRS of lesser voltage ratings (e.g., 300 PRV).
  • high frequency e.g., 3,000 Hz.
  • ISCRS of lesser voltage ratings (e.g., 300 PRV).
  • the conventional construction and operating theory of such devices are well known in the art, as are their limitations.
  • an electrode-less auxiliary region in one end layer of the device which region is physically disposed between the main electrode connected to that end layer and the gate contact and is characterized by a lateral resistance sufficiently high to cause some of the current that initially traverses this region immediately to transfer to a parallel path in the adjoining layer where it acts as a relatively high energy trigger signal for the broad area portion of the semiconductor body subtending the main electrode.
  • the referenced construction has the additional beneficial result of enabling the minimum rise time of an SCR to be shortened.
  • Rise time which is one part of the total time required to switch an SCR from a forward blocking state to a conducting state, may be defined as the time that elapses while forward anode-to-cathode voltage across the triggered device is decreasing from to 10% of its original value.
  • the other part of the overall tum-on time is known as delay time (t which may be defined as the initial length of time required after a stepped trigger signal is applied to the control electrode of the device for anode voltage to drop to its 90% level.
  • a general object of the present invention is to provide further improvements in a high current, high voltage ISCR, whereby it can be turned on with the same or better di/dt capability and with an even shorter delay time than any prior art device heretofore available.
  • V Turn-on voltages under 0.9 volt have been difficult to obtain in conventional high voltage SCRs because the semiconductor bodies of such devices need to have comparatively thick internal (base) layers.
  • base internal layers
  • a typical device rated 1,800 PRV might have an internal N layer that is approximately 10 mils thick contiguous with an internal P layer that is approximately 2 mils thick.
  • Such thicknesses are not compatible with low magnitudes of V For the same reason it has been difiicult to obtain extremely small values of t in such high voltage devices.
  • a low turn-on voltage is particularly important in extra high current applications wherein two or more SCRs are connected in electrically parallel relationship so as to share equally the total load current. While theoretically all of the paralleled devices can be simultaneously triggered, there is in practice a real possibility that one will turn on or fire slightly before the remainder, in which event the forward voltage on the latter then collapses and becomes equal to the low forward drop across the first one fired. Usually the device with the lowest turn-on voltage tends to turn on first. Unless and until the forward voltage across this device exceeds the turn-on voltages of the slower devices, the rest of the parallel combination will not turn on.
  • any appreciable delay in turning on the slower devices might result in failure of the first fired device if the imposed di/dt is more than the first device alone can safely absorb, and if the delay lasts longer than the duration of the trigger signal, the slower devices will never turn on.
  • both an extremely short delay time and the lowest possible turn-on voltage are desirable, and another object of our invention is to provide novel means for obtaining this result in a high voltage device.
  • SCRs having higher di/dt capabilities, shorter delay times, and lower turn-on voltages are desirable in other contexts too. Such characteristics make it possible to reduce costs and to increase efficiency in the manufacture and the operation of the associated control circuits that supply trigger signals to the device. Short delay times and low turn-on voltage are generally useful in static inverter applications and where zero voltage switching is required, and high di/dt capability can significantly prolong the life of a device so endowed. Thus improvements in these characteristics are important design goals in the trade.
  • One of the general objects of the present invention is to reduce the delay time and the turn-on voltage of a solid state controlled rectifier.
  • Another object of this invention is to provide an improved controlled rectifier in which all of the above- .reviewed attributes can be realized to a surprisingly high degree by overdriving the gate.
  • To overdrive the gate is to supply it with substantially more than the critical magnitude of gate current needed to just trigger the device.
  • a more specific object of our invention is the provision of an SCR having significantly improved electrical characteristics that are obtainable by a comparatively simple mechanical modification of a previously available production design.
  • Yet another object is the provision of improved SCRs that can be profitably produced in large quantities and that are characterized by consistently short delay times and uniformly low turn'on voltages.
  • a further object is the provision of a new SCR that lends itself to being triggered by applying to its control electrode a gate voltage of either positive or negative polarity.
  • the term rectifying contact distinguishes our structure from the common prior art practice of joining metal to semiconductor material by means of low resistance, ohmic contacts, such as is shown, for example, in US. Patent 3,006,067-Anderson et al. and in this context the words non-ohmic and rectifying are hereinafter used interchangeably.
  • the control electrode comprises a metallic wire which directly contacts the exposed face of the semiconductor auxiliary region to thereby form a small-area non-ohmic junction therewith.
  • this auxiliary region so that the electrical resistance between the control electrode contact and the one main electrode is appreciably higher than the lateral resistance of the auxiliary region of the DeCecco et a1. device.
  • the latter modification is accomplished by etching or abrading a portion of the outer surface of the prior auxiliary region to remove an appreciable amount of semiconductor material, whereby the material remaining under the exposed face of our auxiliary region is very thin (e.g., 0.4 mil).
  • FIG. 1 is an elevational view, partly in section and not to scale, of a semiconductor switching device constructed in accordance with one form of our invention
  • FIG. 2 is a plan view of the device shown in FIG. 1;
  • FIG. 3 is a schematic diagram of this device connected in an electric circuit
  • FIG. 4 a graph of voltage vs. time illustrating the extremely short delay time of a device made according to our invention
  • FIG. 5 is a hybrid diagram of a semiconductor device embodying our invention.
  • FIGS. 6a and 6b are typical gate-cathode current vs. voltage characteristics of devices embodying our invention.
  • FIG. 7 is a partial elevational view, similar to FIG. 1, of a modified form of the invention.
  • FIG. 8 is a similar view of a device embodying an alternative form of the invention.
  • FIG. 9 is a plan view of the device shown in FIG. 8;
  • FIG. 10 is a partial plan view of a presently preferred form of the invention.
  • FIG. 11 is a partial elevational view of another form of the invention.
  • FIG. 12 is a plan view of a different species of the invention.
  • FIGS. 13 and 14 are partial plan views of two other embodiments of our invention.
  • FIG. 15 is a schematic diagram of an electric circuit wherein at least three of our devices are connected in parallel relation to each other;
  • FIG. 16 is a partial side elevation of yet another embodiment, with external circuits shown connected thereto.
  • FIGS. 1 and 2 we have shown a disc like asymmetrical conductive body 11 comprising four layers or zones 12, 13, 14, and 15 of semiconductor material (preferably silicon) arranged in succession between a pair of spaced-apart metallic main electrodes 16 and 17.
  • Contiguous layers of the body 11 are of different conductivity types, and their interface boundaries thereby form rectifying junctions J1, J2, and J3, respectively. More particularly, as is shown in FIG. 1, the lower end layer 12 of the body 11 is of P-type conductivity, the contiguous internal layer 13 is of N-type conductivity, the next intermediate layer 14 is of P-type conductivity, and the upper end layer 15 is of N-type conductivity.
  • One of the main electrodes 16 is ohmically connected to the P-type end layer 12 and is referred to as an anode of the illustrated device, while the companion main electrode 17 is similarly connected to the opposite N-type end layer 15 and is referred to as a cathode.
  • the PNPN body 11 is really quite thin, e.g., approximately 18 mils.
  • the diameter of the body typically is relatively large, e.g., 1.16 inches.
  • each of the three rectifying junctions J1, J2, and J3 that are serially disposed between anode 16 and cathode 17 has a broad area. While the various junctions within the illustrated device have been depicted in FIG. 1 by solid horizontal lines, those skilled in the art will understand that actually these boundaries are not such discretely definable plane surfaces.
  • the above-described device can be constructed by any of a number of different techniques that are well known in the semiconductor are today.
  • a known diffusion process can be used to form the two P-type layers 12 and 14 in a thin wafer of N-type bulk material comprising phosphorous-doped silicon having a resistivity of approximately 60 ohm-centimeters.
  • acceptor impurities e.g., gallium
  • the surface concentration of gallium being atoms per cubic centimeter.
  • the remainder of the gold-antimony disk comprises the cathode 17 which consequently is in broad area ohmic contact with the N-type layer 15.
  • a broad area ohmic junction can be obtained between the P-type end layer 12 of the silicon body and a conforming layer 16 of aluminum foil or the like, which layer herein is referred to as the anode of the device.
  • a thicker substrate of tungsten or molybdenum or the like is usually bonded to the bottom surface of this anode.
  • a predetermined one of the semiconductor end layers of the above-described device is divided into at least two juxtaposed regions that are disposed laterally adjacent to each other.
  • the end layer 15 has been so divided into first and second regions which hereinafter will be referred to as the main region A and auxiliary region B of this layer. Both regions are contiguous with the intemediate P-type layer 14 of the body 11 that adjoins the end layer 15.
  • the main region A has a major face of relatively broad area in ohmic contact with the cathode 17 which is coextensive therewith; this region is the only part of the end layer 15 that touches the cathode.
  • the adjacent auxiliary region B which is shown smaller than the main region A, has an exposed minor face 18 that is free of cathode connections.
  • the device 11 is triggered (turned on) by means impinging directly and only on the exposed face 18 of the auxiliary region B of the end layer 15.
  • Any conventional triggering means is suitable.
  • electromagnetic radiation more partiularly infrared light, has been successfully employed.
  • triggering means that comprises a metallic control electrode 19 connected by way of at least one non-ohmic contact to a limited area of the auxiliary region B that is spaced apart from the nearest edge or border of the main region A.
  • the auxiliary region B is so constructed and arranged that the lateral resistance between the control electrode contact 20 and the main region A is appreciably higher than that of any adjacent section of the main region having a lateral dimension corresponding to the shortest distance between the area of contact 20 and the bordering main region. While this result can be obtained by altering the electrical properties of the auxiliary region B relative to the main region A, we prefer to obtain it by geometry effects.
  • the auxiliary region B extends laterally from a peripheral border of the adjoining main region A, and to increase its lateral resistance the thickness of the auxiliary region has been materially reduced.
  • the main and auxiliary regions have discretely different thicknesses, with the latter being thinner than the former.
  • the thickness of the region refers to its dimension parallel to the direction of principal current flow between the anode 16 and the cathode 17 of the device, and lateral refers to a direction oriented per pendicular thereto.
  • the thinner auxiliary region B is formed by etching or abrading a portion of the original outer surface of the end layer 15 to remove an appreciable amount of semiconductor material comprising this layer, whereby the remaining material is disposed under an etched-out recess and its thickness consequently is reduced.
  • the material remaining under the removed portion of layer 15 constitutes the auxiliary region B, and its exposed face 18 is depressed but still generally parallel with respect to the plane of the major face of the adjoining main region A.
  • auxiliary region B Since the surface portion of the semiconductor layer 15 in contact with the overlaying gold cathode 17 has a lower resistivity (higher impurity concentration and less tightly bound majority carriers) than the homogenous material comprising the monocrystal interior of this same layer, where this N+ outer surface is removed by etching the remaining material (auxiliary region B) will be characterized by a resistivity appreciably higher than that of the original material (main region A). This then is one means for increasing the electrical resistance between the main region A and the part of auxiliary region B that subtends the limited area of contact with the control electrode 19.
  • auxiliary region B has been formed generally in accordance with the prior teachings of the above-mentioned copending application of De- Cecco et al.
  • PN rectifying
  • the control electrode 19, which is illustrated in FIGS. 1 and 2 as an elongated metallic conductor, makes direct contact with the depressed minor face 18 of the auxiliary region B of the end layer 15.
  • the conductor 19 comprises an aluminum wire that is bonded by ultrasonic welding to the face 18 of the auxiliary region to form at least one small-area non-ohmic metal-to-semiconductor contact 20 therewith.
  • the pointed end of a thin metal probe could be axially pressed against the face 18 to form a point contact thereon. In either case, due to the relatively low elevation of the face 18, the control electrode contact 20 is disposed in the proximity of the intermediate P-type layer 14 of the body 11 as shown.
  • the face 18 of the auxiliary region B extends laterally at least ten mils beyond the periphery of the limited area on which the triggering means 19 impinges in all directions.
  • This peripheral area is barren in the sense that it is free of any effective connections to either the main region A or the control electrode 19.
  • the contact 20 is set back from the perimeter or edge of the face 18, and consequently it is remote from the nearest exposed edge of the PN junction J3.
  • the device shown in FIGS. 1 and 2 can be mounted in an hermetically sealed insulating housing of any suitable design, with its electrodes 16, 17, and 19 being respectively connected to separate terminal members of the housing which members in turn are adapted to be connected to external electric circuits in which the device will be used.
  • an improved housing for this purpose is fully disclosed in a copending patent application Ser. No. 585,428-Sias filed on Oct. 10, 1966, and assigned to the assignee of the present invention.
  • FIG. 3 is a schematic diagram of a semiconductor controlled rectifier 21 connected in series with a load 22 between a pair of electric power input or source terminals 23 and 24.
  • Load di/dt limiting means shown as an inductor 25, is also included in this series circuit.
  • the illustrated rectifier 21 is symbolic of the previously described device 11.
  • a trigger signal is applied to its control electrode or gate 19 by a suitable source of energy represented in FIG. 3 by the serially connected combination of a D-C control current supply 26 (e.g., a battery), a normallyopen switch 27, and a resistor 28.
  • a D-C control current supply 26 e.g., a battery
  • normallyopen switch 27 e.g., a normallyopen switch
  • the negative terminal of the control current supply 26 is shown connected to the cathode 17 of the controlled rectifier 21, and the resistor 28 is connected to the gate 19, whereby the direction of conventional current flow on closing the switch 27 is into the gate and out of the cathode.
  • the controlled rectifier 21 is shunted by a conventional snubber circuit comprising a resistor 29 and a capacitor 30 in series, which circuit is often used to reduce the maximum rate of rise of forward anode voltage on the controlled rectifier. (Note that during the turn-on process, the discharge of the capacitor 30 will initially impose a high di/dt on the controlled rectifier.)
  • cathode current can be sufliciently increased by closing the switch 27 to cause the controlled rectifier to change abruptly from a blocking or oif state to a conducting or on state, whereupon the gate 19 loses control until anode current in the rectifier is subsequently reduced below the holding current level and the device reverts to its forward blocking state.
  • this turn-on process can be accomplished at unusually low magnitudes of forward bias voltage and with unusually short delay times, without sacrificing any of the advantageous characteristics of prior art devices.
  • the short delay time is illustrated in FIG.
  • time traces 31 and 32 represent, respectively, the anode voltage and the gate voltage of a typical device embodying our invention.
  • the device tested had a rating of over 250 amperes and 1800 PRV, and a forward bias voltage of 15 volts D-C was used.
  • the switch 27 in the control circuit was closed.
  • the resulting positive gate current had a magnitude of approximately 1 amp., and gate-to-cathode voltage was initially 15 volts.
  • Load current increased from zero at a rate of 1 amp. per microsecond.
  • the elapsed delay time was approximately 0.1 microsecond.
  • a sampling of devices constructed in accordance with our invention reveals that they consistently turn on when triggered by a very short-duration pulse of positive gate current and that they have uniformly low turn-on voltages.
  • successful switching can be achieved by energizing the gate with a positive trigger signal as small as 0.1 amp. at 2 volts, overdri-ving is preferred for most applications presently contemplated. In this manner we can obtain a di/dt capability at least as good as that attained in practicing the above-mentioned DeCecco et al. invention.
  • FIG. 5 is a hybrid diagram similar to FIG. 1 except that the main and auxiliary regions A and B of the N-type semiconductor layer at the cathode end of the device are shown remote from each other but conductively interconnected by a resistor R.
  • the resistor R represents a path of relatively high lateral resistance provided by the etched auxiliary region B for gate current between the control electrode contact on the exposed face of this region and the cathode 17.
  • the rectifying (PN) junction between the auxiliary region B and the contiguous P layer of the device is labeled J3, and when positive gate: voltage V is first applied this junction is reverse biased.
  • the resulting depletion region or space charge has been depicted by the parallel broken lines on opposite sides of J3.
  • the broken lines embracing the blocking junction J2 between the internal N and P layers 13 and 14 of the device delineate a depletion region or space charge established there by forward bias voltage applied to the anode 16 prior to triggering the device.
  • the junction J4 is forward biased, and the metalsemiconductor contact, or the P-type zone 33, emits holes which are injected into the N-type auxiliary region B, as is indicated in FIG. 5 by the arrow 35.
  • These holes comprise minority carriers in the region B, and being in close proximity to the reverse-biased junction J3, most of them are immediately influenced by its space charge and transported across this junction into the adjoining P-type layer 14, as indicated by the arrow 36.
  • the minority carrier transit time is extremely short because of the relatively small distances involved and because of the accelerating effect of the space charge under the gate contact.
  • the transport efliciency is very high because the part of the auxiliary region B traversed by the holes is so thin and because the surrounding material of the original N- type end layer having a relatively high density of recombination centers was removed when the auxiliary region was formed by surface etching.)
  • the injection of holes 36 into the P-layer 14 will be accompanied by simultaneous ejection of an equal quantity of holes from the same layer. So long as the PN junctions J2 and J3 are both reverse biased, this equal quantity of holes will prefer to cross the junction J3 into the N-type main region A, as indicated by the arrow 37.
  • This hole current is in the forward direction across 13 and necessarily results in minority carriers (electrons) being contemporaneously injected into the P- layer 14 from the main region A, as is indicated by the broken arrow 38.
  • the main region A has a higher impurity concentration and is a better electron emitter, serving in effect like a reservoir of free electrons for forced injection across the forward-biased junction J3 into the adjoining P layer 14.
  • the critical magnitude of gate current that will successively trigger the device can be controlled by the abovementioned etching of the auxiliary region B and by the position and size of the gate contact thereon. These parameters determine the lateral resistance between the gate contact and the main region A. The thinner the auxiliary region the lower the critical gate current but the higher the gate voltage required to produce it. After selecting a desired gate current, the initial turn-on area of the device can be enlarged and the delay time and turn-on voltage both reduced by overdriving the gate. The voltagecurrent characteristic of the gate is also affected by the degree of etching done before the control electrode is attached to the exposed face of the auxiliary region.
  • the non-ohmic contact between the control electrode 19 and the auxiliary region B of the N-type end layer 15 of the semiconductor body 11 is preferably obtained by welding an aluminum wire directly to the exposed face 18 of the auxiliary region.
  • aluminum is advantageous because it not only is capable of bonding to silicon but also is an acceptor.
  • Other metals so characterized include gallium, indium, gold, copper, zinc, or brass.
  • the part of the control electrode that contacts the exposed face of this semiconductor region should preferably comprise a metal characterized as a donor.
  • metals include phosphorous, arsenic, antimony, tungsten, and nickel.
  • FIG. 5 An examination of FIG. 5 suggests the alternative possibility of obtaining a non-ohmic junction between the control electrode 19 and the N-type auxiliary region B by adding a thin zone of semiconductor material having P- type conductivity on a limited area of the face of this region between it and the control electrode.
  • FIG. 7 Such a modified form of our invention has been shown in FIG. 7 which is essentially the same as FIG. 1 except for a narrow zone 41 of P-type semiconductor material on the face 18 of the auxiliary region B of the end layer 15 of the device 11a.
  • the control electrode 19 has been connected to the added zone 41 which is electrically in series therewith, and the turn-on process of the modified device is like that of the first form of our invention previously described.
  • the added zone 41 in FIG. 7 can be deposited by a known epitaxial technique or the like, whereby a rectifying (PN) junction is formed between it and the contiguous region B. Note that a gap is maintained between this zone and the border of the thicker main region of the end layer 15, whereby the lateral resistance of the auxiliary region between the periphery of the control electrode contact and the main region remains high compared to the corresponding parameter of the main region.
  • the auxiliary region B and its thin and narrow overlay 41 could be extended along an appreciable border length of the main region.
  • a ring-like auxiliary region could circumscribe a circular main region, with the zone 41 being a narrow annular band concentrically disposed on this auxiliary region.
  • FIGS. 8 and 9 illustrate another alternative form of the invention.
  • the device 11b shown in these two figures is similar to that shown in FIGS. 1 and 2 except that the auxiliary region B of the end layer 15 has been made circular and is located inboard with respect to the gold cathode 17 overlaying the adjoining main region A. This can conveniently be done by etching an aperture in the original cathode 17.
  • the auxiliary region B is exposed through this aperture, and its face 18 is therefore completely circumscribed by both the main region A and the cathode 17 of the device.
  • the face of this auxiliary region B is in non-ohmic contact with the control electrode 19.
  • the face 18 extends laterally beyond the periphery of the control electrode contact 20, and the portion of the end layer 15 subtending this face is appreciably thinner than any bordering portion of the main region A.
  • the auxiliary region B shown in FIGS. 8 and 9 can be concentrically located on the axis of the disk-like semiconductor body 1111.
  • FIG. 10 shows a device wherein a peripheral segment of the cathode 17 has been removed by etching and a conforming segment of the end layer 15 of semiconductor material has been additionally etched to form the auxiliary region B of our invention.
  • This auxiliary region measures about 0.1 inch across, and a central part of its exposed face 18 is in non-ohmic contact with the control electrode 19 at one or more points.
  • FIG. 11 Another form of the invention is illustrated in FIG. 11.
  • high lateral resistance between the main region A of the end layer and the part of the N- type auxiliary region B in contact with the control electrode 19 is obtained by circumscribing the auxiliary region being spaced from the main region by a gap 42 devoid of any semiconductor material.
  • FIG. 12 we have shown a device He that has two spaced-apart diametrically disposed auxiliary regions B1 and B2 in the periphery of its upper end layer of semiconductor material.
  • This device is equipped with a control electrode 19 having two different parts or branches 43 and 44.
  • the exposed face of the auxiliary region B1 is in non-ohmic contact with the wire comprising part 43 of the control electrode
  • the exposed face of the second auxiliary region B2 is in nonohmic contact with the wire comprising the parallel part 44 of the control electrode.
  • Both auxiliary regions and their respectively associated control electrode contacts are constructed and arranged in accordance with the precepts previously explained in connection with the description of FIGS. 1-5.
  • the FIG. 12 embodiment is intended to double the initial turn-on area of the device and hence to further improve its di/dt capability.
  • still more auxiliary regions could be employed if desired, and at least one of them could be inboard.
  • FIG. 13 shows devices wherein there are at least two spaced-apart points of direct contact between an auxiliary region and its control electrode.
  • FIG. 13 the exposed face of the auxiliary region B of the device 11 is in nonohmic contact with each of two different parts or branches 43 and 44 of the control electrode 19.
  • auxiliary region B whose exposed face has limited area in non-ohmic contact at a, 20b, and 20c with three separate parts of a wire 19 that comprises the control electrode; if desired the auxiliary region B could completely circumscribe the main region A, and additional points of contact with the wire 19 could be provided on the annular face of the former.
  • the several areas of contact with the control electrode are preefrably located with respect to the border between the main and auxiliary regions of the device so that an appreciable length of the border is substantially equidistantly spaced therefrom.
  • the gate contacts 20a and 200 shown in FIG. 14 could be interconnected by a wire or a narrow strip of metal in continuous contact with the exposed face of the auxiliary region B.
  • FIG. 15 is a schematic circuit diagram of a parallel array of semiconductor switching devices 21 constructed in accordance with our invention. Three such controlled rectifiers have been shown, and they are jointly connected between an anode bus 45 and a cathode bus 46 that can also serve as common heat sinks for the rectifiers.
  • the anode bus 45 is connected to one input terminal 47 of a source of electric power, and the cathode bus 46 in series with an extra high current load 48 is connected to another input terminal 49 of the power source.
  • the gate 19 of each rectifier 21 is connected via a separate impedance 50 (shown as a resistor) to a common source of positive gate current which in FIG.
  • a normally open switch 51 and a battery 52 whose negative pole is connected to the cathodes of the respective rectifiers.
  • any suitable gate current source could be used, such as a transformer secondary winding in series with a diode.
  • load current conduction can be initiated by closing the switch 51 and thereby triggering all three rectifiers 21.
  • a conventional snubber circuit can be connected across the parallel array of controlled rectifiers 21, and load di/dt limiting inductance can be connected in series therewith.
  • the controlled rectifiers 21 shown in FIG. 15 are selected from a graded lot to ensure matching characteristics.
  • the relative ohmic values of the respective impedances 50 are chosen to promote simultaneous turn-on or firing of the three rectifiers; if these values were all the same, the three impedances could be consolidated into a single equivalent one or omitted altogether. Because the delay times of our rectifiers are so consistent and so short, it is realistic to expect the three of them to turn on in unison. Thus they equally share total current in the anode bus during turn-on action.
  • this PNPN device 11h is similar to the first embodiment described above.
  • One of the end layers 15 of semiconductor material is divided into at least two juxtaposed regions A and B of discretely different thicknesses.
  • the main region A has a major face in broad-area ohmic contact with the metallic cathode 17, while the thinner auxiliary region B has an exposed minor face 18 that is free of cathode connections.
  • the exposed face 18 of the auxiliary region of its end layer is in non-ohmic contact with a metallic control electrode 19 (e.g., an aluminum wire).
  • the physical construction of the auxiliary region B in the N-type end layer 15 of the device 1111 is essentially like that of the device 11 shown in FIG. 1. We again etch this region to reduce the thickness of the semiconductor layer 15 circumscribing the part of its surface 18 on which the control electrode impinges, thereby increasing the lateral resistance of the auxiliary region.
  • the control electrode contact 20 has been located on a mesa-like part of the exposed face 18 that is not depressed with respect to the major face of the adjoining main region A. Preferably this result is accomplished by connecting the wire 19 to the auxiliary region B before completing the etching of its surface.
  • the removal of semiconductor material to the right of the control electrode contact 20 (as viewed in FIG. 16) will reduce undesirable control current leakage over the relatively low-resistance exterior surface of the adjacent P-type layer 14 of the device.
  • FIG. 16 the anode 16 and the cathode 17 of the device 1111 are shown connected to an external circuit comprising electric power input terminals 53 and 54 and a load 55.
  • a trigger signal is applied to the exposed face 18 of its auxiliary region B by a suitable source of energy that comprises, for example, the combination of a D-C control current supply 56 (e.g., a battery), a normally open switch 57, and a resistor 58 serially connected between the cathode 17 and the control electrode or gate 19 of the device.
  • a suitable source of energy that comprises, for example, the combination of a D-C control current supply 56 (e.g., a battery), a normally open switch 57, and a resistor 58 serially connected between the cathode 17 and the control electrode or gate 19 of the device.
  • this embodiment of our invention is adapted to be 13 fired by negative gate current, and therefore, as can be seen in FIG. 16, the positive pole of the battery 56 is connected to the cathode 17.
  • cathode current can be sufficiently increased by closing the switch 57 to cause the device to change abruptly from a blocking or off state to a conducting or on state.
  • the turn-on characteristics of this embodiment have been found to differ from those previously described as follows: (1) the delay time is not as short, (2) the turn-on voltage is lower, and (3) the minimum magnitude of negative gate current required to trigger the device is lower.
  • the direct contact 20 between the metallic gate 19 and the minor face 18 of the semiconductor region B results in a non-ohmic junction therebetween.
  • this non-ohmic contact can be confirmed by measuring its voltage-current characteristic; a typical gate-cathode characteristic 59 of the device shown in FIG. 16 is reproduced in FIG. 6b.
  • This characteristic is different from the characteristic 34 shown in FIG. 6a because less semiconductor material was removed from the original outer surface of the auxiliary region B prior to attaching the gate thereto.
  • the original surface as mentioned hereinbefore, is characterized by a lower resistivity than the interior portion of the end layer 15, and consequently in FIG. 16 the face of the auxiliary region B in contact with the gate lead 19 has a relatively low barrier potential.
  • the negative gate voltage that is applied to the contact 20 increases the space charge of the blocking junction J2 in the vicinity of this contact, thereby augmenting whatever voltage is being applied to the anode of the device and allowing the above-described action to succeed with a lower forward bias voltage than would otherwise be possible.
  • the consequential cascade of carriers across the blocking junction J2 enables the device to start conducting anode current through the region of the semiconductor body subtending the gate contact 20. To reach the cathode 17, current necessarily passes laterally through the auxiliary region B, and as a result a voltage drop of substantial magnitude is developed across this region between the contact 20 and the cathode 17.
  • the high lateral resistance of the auxiliary region B forces a significant fraction of the current initially traversing this region to immediately transfer to a prallel path comprising the adjoining P-type layer 14 and the PN junction J 3 between it and the main region A of the N-type end layer 15 of the device 1111.
  • This transferred current serves as a relatively large trigger signal for a broad area of the device under the cathode 17.
  • Anode current will now transfer abruptly from the initially triggered area to the broad area portion of the device adjacent to a peripheral section of the main region A, and as this current increases in magnitude it can rapidly spread laterally across the whole area of the device.
  • triggering means other than the metallic control electrode 19 could be used.
  • a beam of light could be focused on the exposed face 18, thereby exciting the auxiliary region B of the FIG. 16 device.
  • a multigate arrangement can sometimes be advantageously used.
  • said other region being so constructed and arranged that (i) said limited area of its minor face is surrounded by a barren peripheral area of said minor face, whereby the limited area on which said triggering means impinges is set back by at least a predetermined minimum distance from the perimeter of said minor face and from any bordering portions of said first regions, and (ii) the portion thereof su-btending said peripheral area of said minor face is appreciably thinner than the bordering portions of said first region.
  • Said triggering means comprises an elongated metallic conductor in direct contact with said limited area of said minor face.
  • said controlled rectifier of claim 9 in which said triggering means includes a thin zone of semiconductor material, of a conductivity type opposite to that of said predetermined one end layer, overlaying only said limited area of said minor face of said other region.
  • a predetermined end layer of said body comprising a main region having a broad area major face and a laterally adjoining auxiliary region having a minor face;
  • control electrode comprising a metallic Wire in rectifying contact with said minor face
  • a disc-like body having four layers of semi-conductor material arranged in succession between said electrodes, with contiguous layers being of different conductivity types whereby rectifying junctions are formed therebetween, the areas of the respective junctions are formed therebetween, the areas of the respective junctions being at least as large as the lateral area of a predetermined one of the opposite end layers of said body;
  • said predetermined end layer comprising at least two juxtaposed regions of discretely different thicknesses
  • said other region being so constructed and arranged that (i) said limited area of its minor face is surrounded by a barren peripheral area of said minor face, whereby the limited area on which said electromagnetic radiation means impinges is set back by at least a predetermined minimum distance from the perimeter of said minor face and from any bordering portions of said first region, and
  • a predetermined one of said end layers comprising juxtaposed main and auxiliary regions both of which are contiguous with the intermediate layer of said body that adjoins said predetermined end layer, said main region having a major face in broad area contact with the main electrode that is connected to said predetermined end layer, and said auxiliary region having a minor face which is generally parallel to said major face and free of main electrode connections;
  • said predetermined end layer comprising (i) a main region in ohmic contact with said first main electrode
  • said predetermined end layer comprising juxtaposed main and auxiliary regions
  • said auxiliary region being free of main electrode connections and having an exposed face to which said control electrode is connected to form therewith a rectifying contact that is spaced apart from the nearest border of said main region, said auxiliary region being so constructed and arranged that the electrical resistance between the part thereof su'btending said rectifying contact and the-main region of said predetermined end layer is appreciably higher than that of any adjacent section of said main region having a lateral dimension corresponding to the shortest distance between said rectifying contact and the border of said main region.
  • each rectifier comprising (i) an asymmetrically conductive semiconductor body including four layers of semiconductor material arranged in succession, with contiguous layers being of different conductivity types,
  • said predetermined end layer comprising a main region having a major face that is substantially coextensive and in contact with said first main electrode and a laterally adjacent auxiliary region of reduced thickness having a minor face that is generally parallel to the plane of said major face, said minor face being free of main electrode connections;
  • (0) means impinging directly on only a limited area of the minor face of each of said rectifiers for simultaneously triggering said rectifiers, said limited area in each rectifier being set back by at least a predetermined minimum distance from the perimeter of the corresponding minor face.
  • a thin disc-like multilayer body of semiconductor material disposed between said electrodes, said body having a first and second opposite end layers connected to said first and second electrodes, respectively, and first and second intermediate layers arranged in succession between said end layers, with contiguous layers being of different conductivity types whereby a series of three rectifying junctions are formed between said first and second end layers, the junction between said first end layer and the contiguous intermediate layer having a lateral area that is substantially coextensive with said first end layer;
  • said first end layer comprising laterally adjoining regions of discretely different thicknesses
  • the adjoining region being disposed inboard with respect to said one region and being appreciably thinner than any bordering portion of said one region, said inboard region having an exposed face that is depressed with respect to said major face;
  • electromagnetic radiation means impinging directly on the exposed face of said inboard region for triggering the controlled rectifier.

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Cited By (17)

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US3577042A (en) * 1967-06-19 1971-05-04 Int Rectifier Corp Gate connection for controlled rectifiers
US3641404A (en) * 1968-06-05 1972-02-08 Asea Ab Thyristor circuit
US3697833A (en) * 1970-02-20 1972-10-10 Mitsubishi Electric Corp Light activated thyristor
US3708732A (en) * 1967-08-03 1973-01-02 Bbc Brown Boveri & Cie Compound electrical circuit unit comprising a main power type thyristor and auxiliary control semiconductor elements structurally and electrically united to form a compact assembly
US3740584A (en) * 1971-06-08 1973-06-19 Gen Electric High arrangement frequency scr gating
US3864726A (en) * 1972-07-28 1975-02-04 Semikron Ges For Gleichrichter Controllable semiconductor rectifier
US3914783A (en) * 1971-10-01 1975-10-21 Hitachi Ltd Multi-layer semiconductor device
US3967308A (en) * 1971-10-01 1976-06-29 Hitachi, Ltd. Semiconductor controlled rectifier
DE2538549A1 (de) * 1975-08-29 1977-03-03 Siemens Ag Mit licht steuerbarer thyristor
DE2648404A1 (de) * 1975-11-03 1977-05-05 Gen Electric Strahlungsempfindliches halbleiter- bauelement
US4028721A (en) * 1973-08-01 1977-06-07 Hitachi, Ltd. Semiconductor controlled rectifier device
US4063278A (en) * 1975-01-06 1977-12-13 Hutson Jearld L Semiconductor switch having sensitive gate characteristics at high temperatures
US4092703A (en) * 1977-03-15 1978-05-30 Kabushiki Kaisha Meidensha Gate controlled semiconductor device
US4207583A (en) * 1978-07-27 1980-06-10 Electric Power Research Institute, Inc. Multiple gated light fired thyristor with non-critical light pipe coupling
US4219833A (en) * 1978-05-22 1980-08-26 Electric Power Research Institute, Inc. Multigate light fired thyristor and method
US4305084A (en) * 1979-11-16 1981-12-08 General Electric Company Semiconductor switching device capable of turn-on only at low applied voltages using self pinch-off means
US4635086A (en) * 1984-10-08 1987-01-06 Kabushiki Kaisha Toshiba Self turnoff type semiconductor switching device

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US3176147A (en) * 1959-11-17 1965-03-30 Ibm Parallel connected two-terminal semiconductor devices of different negative resistance characteristics
US2993154A (en) * 1960-06-10 1961-07-18 Bell Telephone Labor Inc Semiconductor switch
FR1324783A (fr) * 1961-06-05 1963-04-19 Gen Electric Perfectionnements aux dispositifs à semi-conducteurs et procédés de leur fabrication
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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3577042A (en) * 1967-06-19 1971-05-04 Int Rectifier Corp Gate connection for controlled rectifiers
US3708732A (en) * 1967-08-03 1973-01-02 Bbc Brown Boveri & Cie Compound electrical circuit unit comprising a main power type thyristor and auxiliary control semiconductor elements structurally and electrically united to form a compact assembly
US3641404A (en) * 1968-06-05 1972-02-08 Asea Ab Thyristor circuit
US3697833A (en) * 1970-02-20 1972-10-10 Mitsubishi Electric Corp Light activated thyristor
US3740584A (en) * 1971-06-08 1973-06-19 Gen Electric High arrangement frequency scr gating
US3914783A (en) * 1971-10-01 1975-10-21 Hitachi Ltd Multi-layer semiconductor device
US3967308A (en) * 1971-10-01 1976-06-29 Hitachi, Ltd. Semiconductor controlled rectifier
US3864726A (en) * 1972-07-28 1975-02-04 Semikron Ges For Gleichrichter Controllable semiconductor rectifier
US4028721A (en) * 1973-08-01 1977-06-07 Hitachi, Ltd. Semiconductor controlled rectifier device
US4063278A (en) * 1975-01-06 1977-12-13 Hutson Jearld L Semiconductor switch having sensitive gate characteristics at high temperatures
DE2538549A1 (de) * 1975-08-29 1977-03-03 Siemens Ag Mit licht steuerbarer thyristor
DE2648404A1 (de) * 1975-11-03 1977-05-05 Gen Electric Strahlungsempfindliches halbleiter- bauelement
US4092703A (en) * 1977-03-15 1978-05-30 Kabushiki Kaisha Meidensha Gate controlled semiconductor device
US4219833A (en) * 1978-05-22 1980-08-26 Electric Power Research Institute, Inc. Multigate light fired thyristor and method
US4207583A (en) * 1978-07-27 1980-06-10 Electric Power Research Institute, Inc. Multiple gated light fired thyristor with non-critical light pipe coupling
US4305084A (en) * 1979-11-16 1981-12-08 General Electric Company Semiconductor switching device capable of turn-on only at low applied voltages using self pinch-off means
US4635086A (en) * 1984-10-08 1987-01-06 Kabushiki Kaisha Toshiba Self turnoff type semiconductor switching device

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SE322579B (enrdf_load_stackoverflow) 1970-04-13
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ES348224A1 (es) 1969-03-01
BE708190A (enrdf_load_stackoverflow) 1968-06-19

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