US3484755A - Magnetic core encoding device and method - Google Patents

Description

Dec. 16, 1969 J. P. SWEENEY 84,75

MAGNETIC CORE ENCODING DEVICE AND METHOD Filed April 28, 1964 2 Sheets-Sheet 1 INVENTOR. \J sEPH PATRICK SWEENEY J. P. SWEENEY MAGNETIC CORE ENCODING DEVICE AND METHOD Filed April 28, 1964 Dec. 16, 1969 2 Sheets-Sheet 2 INVENTOR. JOEEPH PATRICK SWEENEY BY M J United States Patent MAGNETIC CORE ENCODING DEVICE AND METHOD Joseph Patrick Sweeney, Harrisburg, Pa., assiguor to AMP Incorporated, Harrisburg, Pa. Filed Apr. 28, 1964, Ser. No. 363,165 Int. Cl. Gllb 5/00 US. Cl. 340-174 8 Claims ABSTRACT OF THE DISCLOSURE A device is disclosed featuring multiaperture cores linked by a circuit providing an input of binary intelligence to such cores. The input circuit includes a common winding linking a minor aperture of each of the cores with distinctive patterns of windings linking the major apertures of the cores. The combination of the single winding linking the minor aperture and a winding linking the major aperture of a core provides an MMF which sets half the fiux of the core. The cores are also linked with a circuit to provide a nondestructive readout of the intelligence states stored in the cores.

BACKGROUND OF THE INVENTION The multi-aperture magnetic core makes an ideal component for encoding and decoding devices, because it is quite stable and has, practically speaking, an infinite life when used in circuits free of diodes, capacitors or the like. Even when employed with elements having a finite life the magnetic core has a substantial advantage over other comparable solid state components, because it is capable of maintaining or storing an intelligence state without requiring holding power. One of the problems in the art of magnetic cores, however, is that in order to reduce the amount of power required to drive the cores and to accomplish readout and the other functions necessary to store and transfer intelligence it is advisable to make the individual core switching paths as small as is feasible, considering the degree of reproducibility achievable with present production techniques. This design requirement has led to the development of commercial memory cores 3O thousandths of an inch in diameter with an aperture of 20 thousandths of an inch, and to the development of multi-aperture cores having minor apertures on the order of 15 thousandths of an inch in diameter. One of the larger commercial multi-aperture cores has a major aperture of approximately 270 thousandths of an inch with minor apertures approximately 25 thousandths of an inch. This smallness, which is desirable for power considerations, creats a distinct problem with respect to encoding and decoding equipments wherein a relatively large number of codes must be developed through wiring patterns linking the cores. This problem is aggravated further by magnetic core techniques which practically require that core input be effected through a circuit including turns linking the core minor aperture. For the foregoing reasons the use of multi-aperture core devices for encoding has been heretofore limited to applications wherein either the number of codes is relatively small or the number of cores permitted is relatively large; in either case the relatively small minor apertures of the cores operating to limit the number of windings which maybe applied and therefore the number of codes which may be handled per core.

SUMMARY OF THE INVENTION This invention relates to a multi-aperture magnetic core encoding circuit and to an output technique. The invention is particularly useful with encoding circuits wherein a relatively large number of distinct binary codes must be generated from a device which is as physically small as possible.

Accordingly, it is an object of the present invention to provide a compact multi-aperture magnetic core encoding device and technique which permits the generation of large numbers of binary codes with relatively few magnetic cores.

It is another object of the invention to provide a novel circuit for developing binary codes through the use of multi-aperture cores.

It is yet another object of the invention to provide a multi-aperture encoding device which has fewer input windings required than heretofore possible.

It is yet a further object of the invention to provide a simple and economical encoding device wherein the working part of the circuit may be made of magnetic material and copper wire only.

Other objects and attainments of the: present invention will become apparent to those skilled in the art upon a reading of the following detailed description when taken in conjunction with the drawings in which there is shown and described an illustrative embodiment of the invention; it is to be understood, however, that this embodiment is not intended to be exhaustive nor limiting of the invention but is given for purposes of illustration and principles thereof and the manner of applying it in practical use so that they may modify it in various forms, each as may be best suited to the conditions of a particular use.

In the drawings:

FIGURE 1a is a schematic diagram showing the circuit of the invention relative to a one bit shift register;

FIGURE 1b is a schematic diagram showing a preferred type of input to a core;

FIGURES 1c and 1d show magnetization states for the binary conditions of ONE and ZERO relative to flux orientation in cores; and

FIGURE 2 is a schematic diagram of the circuit of the invention in another embodiment.

DESCRIPTION OF PREFERRED EMBODIMENT Referring now to FIGURE 1b, there is shown a multiaperture magnetic core 10 (greatly enlarged from actual size) having a single central major aperture 12 and a series of minor apertures 14, generally symmetrically disposed in the body of the core. Core 10 is of saturable magnetic material capable of being driven into a number of distinct states of magnetization and remaining in such states indefinitely without applied power. The core material has, of course, square loop characteristics with a finite and a substantially balanced degree of positive and negative remanent saturation which may be represented by lines of flux closure. FIGURE 10 shows the Clear or ZERO state of magnetization wherein the flux lines are oriented clockwise throughout the core material, and FIG- URE 1d represents the Set or ONE state of the jCOI'B wherein the outside leg is negatively saturated with flux in the clockwise sense and the inner leg is positively saturated with fiux in the counterclockwise sense, as represented by the lines shown thereon. The state shown in FIGURE id is, in reality, a Half-Set or MAD-Set condition of magnetization, as contrasted with the positive Set utilized in memory applications wherein the core is positively saturated throughout its cross-section. The Half-Set condition is preferred for MAD-R type circuits, because of the inherent isolation between cores, provided by switching only one half of the material through one leg, inner or outer, during the core transfer operation.

The core states depicted in FIGURES 1c and 1d are accomplished by windings applied to the core through the major or minor apertures. The Clear or ZERO state shown in FIGURE 10 is accomplished by providing current through a number of turns applied through the major aperture 12 to develop an MMF overcoming the core threshold for a suflicient time to drive the core substantiallyinto negative saturation. The state of FIGURE 1d is developed by applying an MMF sufficient to switch the material about the major aperture, but either limiting the amplitude or the time of application of the pulse developing the MMF to a value, when considering the turns of the winding, such that only half the core material is switched. The inner half of the material will switch first and so the normal Set state of the core is as shown in FIGURE 1d with the inner leg of material positively saturated and the outer leg negatively saturated. A winding such as winding 16 shown in FIGURE lb may be impulsed With a positive or negative current to accomplish either the clearing or setting function. With respect to the clearing function there is no particular problem about overdriving the core, since it is intended to be set in the full negative saturation state. With respect to the ONE or Set state, there is a problem since the core should only be half or MAD-Set. For this reason a set winding of the type indicated as 18 in FIGURE lb is preferred with the winding wound as indicated and a current applied in the polarity shown. With this type of input the core 10 for practical purposes will not be overset. The reason for this is that the MMF from the turn passing down through the minor aperture tends to counteract the MMF from the turn passing up through the major aperture with respect to the outer path of material forming the major path of the code.

Thus then, for clearing of multi-aperture cores, a winding such as 16 is preferred, and for setting such cores, except where the current pulse may be reasonably limited, a winding of the configuration shown as 18 or its equivalent preferred.

Referring now to FIGURE 1a, there is shown a pair of multi-aperture cores in a circuit arranged to accomplish an intelligence handling function. These cores are limited by a circuit designed to accomplish transfer through the MAD-R technique. A general description of the MAD- R technique is given in my US. Patent No. 2,995,731. The cores are normally assigned to positions in the cycle which include odd and even identified by O and E. The advance circuit is similarly identified, being arranged to include an ADV. O winding and an ADV. E winding, shown as 30 and 32, respectively, and each including turns adapted to apply a clearing MMF to the cores. A further portion of the drive circuit is identified as winding 34, which links the transmitting minor apertures of the core in a sense to apply a priming MMF locally about such transmitting minor aperture. The function of priming is Well understood by those skilled in the art, but reference may be had to my US. Patent above mentioned for a more complete description. Transfer into, through and out of the magnetic device formed by the O and E cores is accomplished through the input winding to the core shown as 40, a coupling loop shown as 42 linking the 0 core to the E core, and an output winding shown at 44 linking the transmitting aperture of the E core to a utility device shown as 46. It is to be understood that winding 44 could, of course, be made to link a further core in a series of cores and the basic circuit can be expanded from tWo to fifty, or a hundred cores arranged to transfer intelligence fed into the first 0 core. Not shown, but also to be understood, the cores could be arranged for a parallel transfer which would invoke an input simultaneously to each of the two cores shown, or an onput simultaneously, therefrom, as will be described with respect to FIG- URE 2.

From the foregoing it should be apparent that binary intelligence in the form of current pulses representing ONE or ZERO (the ZERO pulse being either no pulse or at least a very small pulse) may be transferred into the 0 core and then to the E core and then out to drive the utility device 46. In many applications there is a need to monitor or sample the intelligence states of the cores either continuously or at intervals. A preferred circuit for this is shown in FIGURE 1a to include an RF drive winding, which upon the closure of a switch S will apply an RF or alternating current signal to the cores through available minor apertures as indicated. This winding, which is shown as 50, links the core minor apertures through a number of turns to apply the RF signal in a manner to switch flux locally about the core minor aperture, but sufiiciently limited in amplitude and duration so as not to switch 'fiux about the major aperture. For cores having an approximate total flux content of 60 maxwells and a threshold of 1000' milliampere turns an RF signal suitable for this purpose has been found to-be at a frequency of about 300 kilocycles at an amplitude of 300 milliamperes, peak-to-peak. The application of RF through the closure of switch S will, as above indicated, produce a localized switching of flux around the minor aperture threaded by the lead 50, and such switching will be considerable if the core is in the Set ONE state shown in FIGURE 1d, and inconsiderable if the core is in the Clear or ZERO state shown in FIG- URE 1c.

Linking the outer leg adjacent to minor aperture threaded by 50 is a readout circuit including a winding shown as 52 connected to drive a utility device shown as a lamp 54. The substantial and localized fiux switching of a Set core under RF drive will produce an output lighting the lamp 54. If the core is Clear, however, the RF drive will produce no output or an insubstantial output which is insufficient to overcome the threshold of the lamp. Thus then, with this circuit the instantaneous intelligence states of the cores 0 and B may be monitored by the application of RF by closure of switch S and by opening the switch S the parallel interrogation of the cores will be terminated. In practice, it is preferred that the readout circuit, including the RF windings and the readout windings, be as disclosed in US. patent application Ser. No. 249,466, titled Magnetic Core Read-Out Means and Method, filed Jan. 4, 1963, in the name of J. C. Mallinson and J. P. Sweeney, now US. Patent No. 3,328,784 granted June 27, 1967. The reason for this is that with the circuit of Ser. No. 249,466 a fully continuous and nondestructive read-out can be obtained even while the cores are being driven to advance intelligence therethrough. With the simplified circuit shown in FIG- URE 1a care must be taken to avoid eifects causing a degradation of the intelligence content if the RF drive is left on during transfer.

The above-described circuit then is capable of receiving and transferring binary intelligence in serial or parallel form and of being caused to display or output the instantaneous or stored intelligence states in parallel through the RF read-out circuit or in series through circuit 46. With this type of circuit as a basic ingredient, encoding devices may be constructed wherein the cores are independently set in patterns of binary ZEROS or ONES with such patterns representing intelligence messages in any siutable form, as for example in a form representating a digital or decimal count. The means for accomplishing inputs to the core may generally be as described with respect to FIGURES la-ld, such as to set or clear certain of the cores. For the reasons heretofore described, in the applications where only a few codes are of necessity required, the problem is straight-forward and separate windings to set or clear the respective cores as desired may be employed. Where, however, there are a considerable number of codes and hence, leads required to be linked to the cores, including leads which must half-set the cores, the problem is aggravated and the basic concept of the invention comes into its own.

In FIGURE 1a there is provided an encoding circuit generally shown as 60, which is capable of inputting to the two cores, the binary combinations or patterns of ZERO ZERO, ONE ONE, ONE ZERO And ZERO ONE, which is in fact all of the possible binary codes which two simple core structures can handle. An advantageous feature of circuit 60 is that the type of set input, which as above described is preferred, is achieved with only a single winding linking a core minor aperture, with such winding serving in common all of the distinct circuits for providing the separate patterns of intelligence input. This winding is shown as 62 and is connected at point C to four other windings shown as 64, 66, 68 and 70. The common winding 62 threads through available core minor apertures, as indicated, by a number of turns labeled N Each of the windings 64, 66, 68 and 70 link the core major apertures by turns denominated N and while only a single turn is shown with respect to N and N in the circuit of FIGURE 1a, it is to be under stood that to get a suflicient MMF with lower applied current more turns are employed. In an actual embodiment utilizing a core of the characteristics above-described, the number of turns N and N were six each.

The polarity of winding 62 is as indicates such as to apply an MMF in a clockwise sense with respect to the core major aperture, although the winding is, of course, applied to the core minor aperture. The turns N on windings 64, 66, 68 and 70 are applied in different senses to the core major apertures depending upon their particular function in operating along with the turns N to either set or clear the cores to form the codes desired. Connected as an input to each of the leads 64, 66, 68 and 70 are a series of switches shown as S S S and S which are linked to some positive source of current pulses. The source of current pulses may be in common to all of the switches and may be a simplified source such as a .battery or capacitor discharge circuit, or alternatively,

may be individual intelligence channels. The switches S S which are shown symbolically as mechanical switches, may of course, be solid state switches formed by transistors or even other magnetic cores.

Upon closure of a selected one of the switches the.

associated lead is energized such that the turns N and the turns N are energized to establish an MMF acting upon the cores to accomplish the particular function-sought. Taking the switch S and associated winding 64 first, it will be observed that the particular turns N are in a sense, with respect to the O and E cores, to clear the 0 core and set the E core to thus put into the two cores the binary code ZERO ONE. The return path associated with lead 64 is lead 62, which develops an MMF in a sense such that the E core is MAD-Set in the manner described with respect to FIGURES lb-1d, and particularly with respect to the winding 18. The composite winding 64, 62 functions identically as winding 18 was stated to function with respect to FIGURE 1b. Thereafter, by closure of S the ZERO, ONE pattern can 'be read out in parallel via 52, 54; or by the application of prime, ADV. O and ADV. E the pattern can be shifted out via 46.

- The closure of switch S will energize lead 68 and the turns associated therewith to clear both the O and E cores to thus effect the pattern ZERO ZERO. The closure of switch S will, through the turns linked to winding 70, operate to set both such cores to input the code ONE -.ONE. The closure of switch S through the lead 66 will operate to set the 0 core and clear the E core of the register for a code input ONE ZERO.

The circuit in FIGURE 1 is much simplified as compared to the usual case, in that it has only four codes, and as can be observed, some problem would be encountered with prior art techniques even with a limited function circuit of this type, since with standard cores the minor apertures are about 20 thousandths of an inch and the leads formed by 6468 and 62 are approximately 3.5 thousandths of an inch with two to six turns each. As a matter of fact the circuit of the type shown in FIGURE 1a could not practically be accomplished with standard cores and normal inputting techniques wherein for each code a separate input to each core minor aperture is used. With the circuit of the invention, and the common minor aperture winding feature, inputs of this size and much larger may be easily accomplished because all of the winding turns N are wound through the core major aperture which as mentioned may be as large as 270 thousandths of an inch.

In brief summary as to the arrangement shown in FIGURE 1a, a shift register device may be loaded serially by inputs applied to winding 40, the intelligency inputs transferred from the O to the E core and destructively readout to the utility device 46 by application of drive pulses of a proper cycle applied to the windings 30, 32 and 34. Additionally, the two cores may be simultaneously set in parallel by the various code inputs to any of the four binary cores indicated. The code input may be read non-destructively either while the cores are not being shifted, or may be read while their register is being shifted through the use of the RF and readout circuit described in the application Ser. No. 249,466 above mentioned.

FIGURE 2 shows a more complex circuit employing the principles of the invention, with a slightly difierent technique utilized to reset or clear all of the cores by separate means. In FIGURE 2 the cores are as above described, but do not include a serial transfer circuit; being adapted to be set and cleared in parallel by sep arate setting and clearing circuits. Theclearing circuit is shown as a winding 100, which links each of the cores through the major apertures in about the major legs thereof by turns N applied in series to the four cores. Closure of the switch S will then apply a current from the battery connected thereto to clear each of the cores by driving the core material into negative saturation. Further provided, threading each of the cores in series is an RF drive circuit similar to the one previously described but including figure-eight turns with an individual read-out circuit shown as 112 in figure eight fashion linking the same aperture threaded by the RF winding. Closure of the switch S will then energize the RF turns linking the core and cause the intelligence state of the core to be non-destructively read-out via lamp 113 shown connected to the output lead 112. Also linking each of the cores and by winding turns shown as N threading the core major aperture and encircling the major body of the core are further output leads shown as 114 connected to utility devices 115 which may be any type of device capable of responding to the type of pulse produced by the switching of magnetic cores. The input to the cores is similar to that shown in FIGURE la with the addition of sufficient wiring patterns to set up the binary codes for the decimal numbers 0 and 1 through 15. The particular binary code patterns are shown to the left in FIGURE 2 adjacent the particular switches 8 which, when closed operate through the battery supply to energize the leads such as 116 connected to switch S As before, the switches shown can be mechanical, electromechanical or solid state devices suitably gated by control signals.

In operation after the cores are first cleared by the closure switch S any one of the code patterns may be set into the register by closure of an associated switch. For example, closure of the switch S will operate to set the core threaded by the turns N via lead 116 and this will be a MAD-Set due to the counter MMF applied to the common return lead 120. The register will then contain the binary intelligence code ZERO ZERO ZERO ONE. Closure of the switch S will, through the turns linking the lead 122, set the third core to the right and leave the remaining cores Clear to provide the pattern ZERO ZERO ONE ZERO. Closure of switch S will accomplish a setting of the two cores to the right, leaving the other cores Clear to provide the pattern ZERO ZERO ONE ONE. The remaining switches are com nected to windings not shown, which are adapted to set particular cores in the same manner as immediately above-described; it being understood that between the setting of any pattern, the switch S will need to be closed to first clear the cores.

The operation of switch S by clearing the cores, will produce an instantaneous and destructive or dynamic output to the utility devices connected to the cores via the windings 114 shown connected to the cores of the register. The particular code pattern then in registry will be manifested in the utility devices connected to the cores.

In use, a circuit of the type shown in FIGURE 2 is employed, with a first operation of the readout switch S followed by the setting of a desired code pattern through closure of one of the switches 8 -8 This is followed by an operation of switch S to verify the proper setting of the input code without readout to the utility devices, and then, upon command, the closure of switch S again to accomplish the destructive readout function and drive the utility devices in the desired intelligence format set up by the inputting of the code.

It should be appreciated that without the technique of the invention wherein a common return is employed through the minor apertures of the cores, it would be diflicult to provide encoding devices having the preferred type of Set. In an actual embodiment employing the techniques of the invention, ten cores of the type above described were utilized to handle 160 distinct binary code patterns. While the invention has been described relative to distinct cores it is to be understood that the equivalent of separate cores may be used in a composite core shape wherein flux paths of closure are formed to define many bit positions each linked by the invention circuit in a manner which should now be apparent.

That part of the description relative to verification of the code in storage prior to destructive readout can be accomplished by visual observation or may be accomplished by use of comparator circuits of well known types.

Changes in construction will occur to those skilled in the art and various apparently different modifications and embodiments may be made without departing from the scope of the invention. The matter set forth in the foregoing description and accompanying drawings is offered by way of illustration only.

What is claimed is:

1. A device for providing distinctive binary codes including at least two multi-aperture cores of saturable magnetic material each capable of storing binary intelligence in one-zero form by a particular state of remanent magnetization, means for driving said cores to switch fiux therein proportional to the intelligence content input, means responsive to flux switched in a given core to provide an output signal representing the intelligence content thereof and input means to provide intelligence input to said cores including a winding for binary one inputs which links all of the cores in common in a manner to limit the flux switched to approximately half of the flux content of the core and with said winding also linking certain of the cores in a sense'to input a binary one and linking others of the cores in a sense to input a binary zero.

2. The device of claim 1 wherein there is included linking at least one of the cores means to provide nondestructive read-out of the binary state in registry.

3. The device of claim 1 wherein there is included means to provide non-destructive read-out of the binary states in registry and other means to provide destructive read-out of the binary states in registry and other means to provide destructive read-out of the binary states in registry.

4. A multi-aperture saturable magnetic core device including at least two cores each having a major aperture and at least two minor apertures, means linking the major apertures and adapted to drive said cores into saturation, means linking the minor aperture and major aperture of certain of said cores and adapted to drive said cores into states of magnetization representative of binary intelligence to establish a binary code in said device and means linking said major aperture to provide read-out of the binary code in said device with the said means adapted to drive said cores into saturation serving to preset the cores of said device with an all binary zero code, and said means linking a core minor and major aperture to set certain of said cores with a binary one.

5. The device of claim 4 wherein said means linking a core minor and major aperture further includes turns linking certain cores through the major apertures only whereby said certain cores are driven to binary one and zero states by the same means.

6. A device for generating distinct binary codes including a plurality of bit positions formed of saturable magnetic material each position having a major path and several minor paths, first means linking the major paths and adapted to drive the material thereof into substantial saturation, encoding means including second means linking at least certain of the bit positions through the major path and through a minor path and adapted to input a binary one to the position linked by driving the material thereof oppositely to the sense of saturation effected by said first means and said encoding means further includes third means linking at least certain of said bit positions through a major path and adapted to input a binary zero to the position linked by driving the material thereof into substantial saturation.

7. The device of claim 6 wherein there is further included a fourth means linking the bit positions to drive the material to provide flux switching proportional to the state of saturation and fifth means linking said bit positions and responsive to flux switched to provide a readout indicative of the state of saturation and thereby the binary code of said device.

8. A method for providing a verified dynamic output of binary intelligence codes stored in a chain of multiaperture magnetic cores of the type having a major aperture and at least a minor aperture including providing a drive MMF to switch flux locally about a core minor aperture without materially disturbing the flux state about the core major aperture to provide a non-destructive output sensing the locally switched flux to detect output signals for the chain of cores, comparing said output signals with the code stored, and then driving said cores to switch fiuX about the core major apertures to provide a further and destructive output from the chain of cores.

References Cited UNITED STATES PATENTS 3,290,513 12/1966 Sweeney 340174 3,312,959 4/1967 Bennion 340174 3,323,113 5/1967 Bennion 340--174 3,328,784 6/1967 Mallinson et a1 340174 3,337,857 8/1967 Dowling 340-174 3,343,146 9/1967 Walker v 340174 3,234,527 2/1966 Korkowski 340-174 BERNARD KONICK, Primary Examiner V. P. CANNEY, Assistant Examiner

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