US3482180A - Variable gain amplifier and circuits using same - Google Patents

Variable gain amplifier and circuits using same Download PDF

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US3482180A
US3482180A US550010A US3482180DA US3482180A US 3482180 A US3482180 A US 3482180A US 550010 A US550010 A US 550010A US 3482180D A US3482180D A US 3482180DA US 3482180 A US3482180 A US 3482180A
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Jean Victor Martens
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International Standard Electric Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/48—Servo-type converters

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  • Control signals are coupled to the gating transistors to adjust the gain of the amplifier by controlling the number of differential amplifiers receiving the constant current and, hence, the number of active differential amplifiers. This arrangement provides almost perfect decoupling between the control and transmission path and temperature compensation due to circuit symmetry.
  • the present invention relates to a variable gain amplifier and to circuits using same.
  • variable gain amplifiers are in companded analog digital converters as disclosed for instance in the US. Patent 3,067,291.
  • variable gain amplifiers use is made of diodes to perform the variation of the gain. It is well known that the diode characteristics are sensitive to temperature variations and diode ageing. Hence, there results an inaccuracy of the input-output characteristic of the amplifier, which is composed of straight line segments, and especially an uncertainty as to the exact location of the knee points of gain variation of this input-output characteristic.
  • Non-linear analog/ digital converters which have a piecewise linear characteristic obtained from different coding step sizes of these converters are also known in the art, e.g., from the US. Patent 3,016,528.
  • the main drawback of these converters resides in the difliculties encountered in the accurate production of the smallest coding steps, so that the present tendency is to abandon this type of converters in favor of the companded converters.
  • An object of the present invention is to provide a variable gain amplifier which does not present the above mentioned drawbacks.
  • the present variable gain amplifier is characterized by the fact that, it includes at least a first and a second amplifying section having a common output impedance and being fed by constant-current generator means, switching means controlled by control means being adapted to electrically disconnect said constant current generator means from one or more selected sections, whereby a substan- 3,482,180 Patented Dec. 2, 1969 "ice" Another object of the present invention is to provide an improved companded analog/ digital converter system.
  • a companded analog/digital converter system is characterized by the fact that it includes a variable gain amplifier of the type defined above, associated with a linear analog/digital converter, and that the digital side of said converter controls said switching means.
  • variable gain amplifiers are as phase-inverter modulators particularly those of the double balanced type.
  • Double balanced transistorized phase-inverter modulators are in themselves known.
  • Even in the US. Patent Nos. 2,994,044 and 3,010,079 it would not be possible in practice to avoid transformers, since the circuits would not allow both the signal and the carrier sources to have one of their terminals at a fixed reference potential without creating unbalance conditions.
  • transistors of opposite conductivity type are required.
  • Another object of the invention is to realize a novel double balanced transistorized modulator which avoids such drawbacks, i.e., which does not necessarily require transformers, transistors of opposite conductivity type and which may be driven by signal and carrier sources which can both be unbalanced with respect to ground.
  • a phase-inverter modulator is characterized by the fact, that it comprises a variable gain amplifier of the type previously defined, with said amplifying sections exhibiting linear input-output relationships with slopes of opposite signs.
  • a further object of the present invention is to provide an improved companded digital-to-analog converter system.
  • a companded digital-to-analog converter system is characterized by the fact that it includes a phase-inverter modulator of the type defined above, and that said phase-inverter modulator is coupled in series with a digital-to analog converter which produces analog signals of one polarity only, the setting of said phase-inverter modulator in its positive or negative gain condition depending on the nature of the highest Weight binary digit of the digital signal version.
  • the present invention also relates to a sequential comparison analog-to-digital converter system, including comparison means to compare an analog input signal with a number of successive reference signals for accordingly producing the binary digits of the digital signal version.
  • Another object of the present invention is to provide a sequential comparison analog-to-digital converter system which does not present the above drawbacks.
  • the present sequential comparison analog-to-digital converter system is characterized by the fact, that said comparison means include a discriminator circuit which is constituted by a differential amplifier having a first and a second input, the input analog signals being applied to both said first and said second input in push-pull, and that said reference signals, which are of one polarity only, are applied to said first or to said second input depending on the nature of the preceding binary digit(s) of the digital signal version.
  • said comparison means include a discriminator circuit which is constituted by a differential amplifier having a first and a second input, the input analog signals being applied to both said first and said second input in push-pull, and that said reference signals, which are of one polarity only, are applied to said first or to said second input depending on the nature of the preceding binary digit(s) of the digital signal version.
  • FIG. 1 represents a companded coder according to the invention and included in a PCM transmission system
  • FIG. 2 shows a variable gain amplifier constituting the compressor circuit of the companded coder of FIG. 1;
  • FIG. 3 represents the input-output characteristic of the variable gain amplifier, or compressor circuit of FIG. 2;
  • FIG. 4 shows in detail circuits of the encoder of FIG. 1;
  • FIG. 5 represents timing pulse patterns applied to the encoder of FIGS. 1 and 4;
  • FIGS. 6 and 7 show in more detail some block circuits of FIG. 1;
  • FIG. 8 diagrammatically represents an embodiment of an expander circuit according to the invention and included in the above PCM transmission system
  • FIG. 9 shows part of a phase-inverter modulator according to the invention.
  • FIG. 10 diagrammatically represents a further embodiment of an expander circuit according to the invention which includes the circuits of FIGS. 8 and 9.
  • the companded coder shown therein is constituted by a compressor circuit C followed by a linear encoder which is a digit-at-a-time, or sequential comparison encoder.
  • the compressor circuit C0 has an input 1' at which the PAM signals to be compressed are applied and two outputs 0, 0 through which the compressed PAM signals are supplied to the encoder.
  • the encoder comprises three functional parts: the decision part, the control part and the weighing part. It is assumed that the above encoder comprises 64 quantum steps, i.e., it
  • the control part comprises five gated-input flip-flops F to F each having three inputs numbered 1, 2, 3 and two outputs numbered 4, 5 and a gating circuit G.
  • the gated-input flip-flops F to F are well known in the art, e.g., they are Fairchild Micrologic Half Shift Register elements L906, and FIG. 7 schematically represents the block circuitry of such an element F, (1' 1 to 5).
  • the element F is constituted by four 2-input NAND (Not AND) gates L and L which are Resistor Transistor Logic, gate circuits, the gates L and L constituting the output flip-flop stage and the gates L L; the input gating stage.
  • the inputs 1 and 3 of the element F constitute one input of the gates L and L respectively, whereas the input 2 of the element F, constitutes the second common input of both these gates L L
  • the outputs 4 and 5 of the element F are the outputs of the gates L and L respectively and constitute the f, (1 or 0) and 7, (O or 1) com plementary outputs of the flip-flop stage L L or of the whole gated-input flip-flop F,.
  • the inputs 1 of the gated-input flip-flops F to F (FIG. 1) are connected .4 in parallel to each other and their parallel connection is connected to the outputs of the flip-flop FF.
  • the inputs 3- of the gated-input flip-flops F to F are paralleled and their parallel connection is connected to the output 5 of the flip-flop FF.
  • the inputs 2 of the gatedinput flip-flops F to F are connected to corresponding outputs ep to ep of a timing source (not shown).
  • the gating circuit G has, on the one hand, five inputs correspondingly connected to the outputs f T and f T of the gated-input flip-flops F and F and to the output ep of the above mentioned timing source, and, on the other hand, one output 0 which is connected to a homologue control input of the compressor C0.
  • the circuitry of the gating circuit G is schematically shown in FIG. 6.
  • This circuit G is constituted by four 2-input NAND gates L to L and one inverter N which are RTL circuits well known in the art and forms at its output c the logical function
  • the weighing part of the encoder comprises six synthesizing networks SN to SN each having two inputs bj b',- and two outputs a,-, a,- (j: 1 to 6).
  • the outputs a and a,- are paralleled and their parallel connection is connected to the input 0 and 0 of the discriminator DSC, respectively.
  • the inputs b b b of the synthetizing networks SN SN- 8N are connected in parallel and their parallel connection is connected to the output 3, of the gated-input flip-flop F
  • the inputs b b b of the networks SN 4, 5 are connected to the outputs f f f of the gated-input flip-flops F F F respectively.
  • the input b' of the network 8N is connected to the output 0 of the gating circuit G, whereas the inputs b' to b are connected to the outputs ep to 2 2 and e p' of the previously mentioned timing source (not shown), respectively.
  • the discriminator DSC comprises a pair of NPN transistors Q Q mounted as a differential amplifier, a switching NPN transistor Q and an output transformer T.
  • the collector electrodes of the transistors Q and Q are connected to each other through the primary winding of the transformer T which has a center-tapping connected to the positive terminal of a source S of DC fixed potential.
  • the emitter electrodes of the transistors Q and Q-; are connected to each other and further connected to the collector electrode of the transistor Q through a resistor R the emitter of the latter transistor Q being connected to ground and its base electrode to the output 1 of the previously mentioned source of clock pulses via an inverter N
  • the base electrodes of the transistors Q and Q'q constituting the two inputs 0, 0" between which the compressed PAM signals are applied to the discriminator, are, on the one hand, connected to the homologue outputs 0 and 0' of the compressor C0 and, on the other hand, to the junction point of two potentiometer resistors R R through the identical resistors R and R respectively.
  • the other ends of the potentiometer resistors R and R are connected to the positive terminal of the source S and to ground, respectively.
  • the secondary winding of the transformer T is also provided with a centertapping which is connected to ground.
  • the flip-flop FF comprises two 2-input NAND gates L and L one input of these gates L and L being connected to the one and to the other end of the secondary winding of the transformer T respectively.
  • the output s of the gate L constitutes the output of the encoder and is coupled to the transmission line (not shown).
  • the synthetizing network SN comprises a pair of NPN transistors Q and Q' which have their emitter electrodes connected to each other and further connected to the collector of a switching NPN transistor Q
  • the collector electrodes of the transistors Q and Q' constitute the outputs a,- and a, of the synthetizing network SN, and are connected to the base and on the other hand, to the anode electrode of a diode D of which the cathode electrode is connected to ground.
  • the emitter electrode of the transistor Q is connected, on the one hand, to the negative terminal of a reference source S of DC fixed potential through a weighing resistor 'R and, on the other hand, to the cathode of a diode D
  • the base electrode of the transistor Q and the anode electrode of the diode D constitute the inputs b and b of the synthetizing network SN respectively.
  • FIG. 5 shows the clock pulses and 0 provided at the corresponding two outputs of a double phase clock (not shown) which constitutes the previously mentioned source of clock pulses, as Well as, the pulse patterns ep to e17 and ep' applied to the circuits of FIG. 1.
  • the ⁇ 5 clock pulses occur midway in the interval between two successive 0 clock pulses, the time interval between two successive $5 or 75 clock pulses being equal to the length of a digit of the 6-digit PCM code.
  • the pulse patterns ep to ep and ep' are time positioned with respect to an encoding interval represented by the l-condition of an encoding pattern enc.
  • the negative logic convention is adopted throughout the present description and the logical levels 1 and 0 of the ON-OFF binary signals represent a ground and a positive, e.g., +6 v., DC potential, respectively.
  • the encoding interval given by the logical l-level of the pattern enc is allocated to the translation of a PAM signal into a 6-digit PCM code. This encoding interval may be divided into six consecutive digit encoding intervals by the $5 clock pulses (dotted verticals of FIG. 5).
  • the pattern ep assumes the O-level only during the first digit encoding interval, the pattern ep only during the first and second digit encoding intervals and so on for the patterns e12 e17 ep
  • These patterns ep to e17 may be obtained from five corresponding outputs of a five stage ring counter (not shown) controlled by the 0 clock pulses, the five stages of this counter assuming the siX positions represented in FIG. 5 during the six consecutive digit encoding intervals.
  • the compressor circuit shown therein is constituted by two main parts: an analog part and a control part.
  • the analog part comprises two pairs of NPN transistors Q Q and Q Q mounted as two differential amplifiers, which are connected in parallel to each other.
  • the control part comprises the switching NPN transistors Q Q and the NPN transistor Q which is mounted as a constant current generator.
  • the emitters of the transistors Q and Q are connected to each other via the series connection of two identical resistors R and R the junction point of which is connected to the collector of the switching transistor Q
  • the emitters of the transistors Q and Q are connected to each other through the series connection of two identical resistors R and R the junction point of which is connected to the collector of the switching transistor Q
  • the collectors of the transistors Q and Q are connected to the collectors of the transistors Q and Q respectively and the junction points of these collectors are connected to each other through the series connection of two identical output resistors R and R the junction point of which is connected to the positive terminal of the source S of DC fixed potential.
  • the base electrodes of the transistors Q and Q as well as, of the transistors Q and Q, are connected to each other and further connected to the junction point of two series connected resistors R and R through the identical resistors R and R respectively.
  • the other ends of the resistors R and R are connected to the positive terminal of the source S and to ground, respectively.
  • the interconnected base electrodes of the transistors Q and Q constitute the input terminal i of the compressor, Whereas the interconnected base electrodes of the transistors Q and Q may constitute a second input terminal i of the compressor.
  • the interconnected collector electrodes of the transistors Q and Q and of the transistors Q and Q constitute the output terminals 0 and 0 of the compressor C0, respectively.
  • the emitter electrodes of the switching transistors Q and Q are connected to each other through the series connection of the resistors R and R the junction point of which is connected to the collector of the transistor Q
  • the base electrode of the transistor Q is connected to the output 0 of the gating circuit G of the encoder, whereas the base electrode of the transistor Q is connected, on the one hand, to the positive terminal of the source S via a resistor R and, on the other hand, to ground via a resistor R
  • the base electrode of the transistor Q is connected to the positive terminal of the source S and to ground via the resistors R and R respectively.
  • the emitter electrode of the transistor Q is connected to ground through a resistor R
  • the PAM signals to be compressed are applied between the input terminals i, i of the compressor C0 through a symmetrical transformer (not shown), which performs the balancing of the input PAM signals, whereas the compressed balanced output signals are taken between the output terminals 0 and 0" of the compressor C0.
  • a more advantageous mode of operation which becomes possible with this type of compressor C0 is the semi-balanced mode here adopted, i.e., unbalanced input and balanced output.
  • the unbalanced input PAM signals are applied to the input terminal 1 and the balanced output signals are taken between the output terminals 0 and 0' of the compressor C0. In this way the use of the above input transformer is avoided.
  • the input-output characteristic of the compressor C0 (FIGS. 1, 2) is shown in the diagram of FIG. 3, wherein the input voltages AE y and the output currents A1 are reported on the homologue orthogonal axes;
  • the output currents OC and OC (0C OC',) on the axis A1 correspond to the quantum levels 48 and 1 6, or to the code numbers +16 and 16 of the PCM code, respectively.
  • the input-output characteristic of the compressor C0 is composed of the straight line segments B B B' B and B B As it will be explained later, the segments B' B and B B are vertically shifted to their parallel positions B' B' and B,B by means of a current B' B or B B applied to the input 0 or 0 of the discriminator DSC by means of the synthetizing network 8N
  • FIGS. 1 to 6 the principle of operation of the compressor C and of the encoder will be described, reference being made to FIGS. 1 to 6.
  • the differential amplifiers Q Q4 and Q Q are both active. This is performed by fixing the DC voltage at the base e of the transistor Q to a lower level than the DC voltage at the base d of the switching transistor Q and by fixing the control voltage Vc at the control terminal 0, e.g., equal to the DC voltage at the base 0! of the transistor Q e.g., +6 v.
  • the total emitter current of transistors Q to Q which is supplied by the constant current supply transistor Q and which is symmetrically shared by the collector resistors R and R flows through both transistor pairs Q Q and Q Q and the amplification coefficient 6 is approximately given by the relation:
  • a PAM signal applied to the input i of the compressor is amplified with this amplification coefiicient G and supplied to the discriminator DSC through the output 00' of the compressor C0.
  • the encoder then starts the sequential comparisons of the compressed PAM signal, which is applied to the discriminator inputs with reference signals.
  • the patterns ep to @17 and fi' assume their logical O-level which corresponds to a positive DC potential, c.g., +6 v.
  • the emitter of the NPN transistor Q in each synthetizing network SN is at a more positive potential than the corresponding base electrode, e.g., emitter at +5.3 v. and base at +0.7 v. assuming the voltage drop across the diodes D and D equal to 0.7 v.
  • the M and 5 outputs of the double phase clock normally are at the logical O-level, i.e., positive, and are brought to the logical 1- level, i.e., ground, during the occurrence of a $3 and ⁇ 5 phase clock pulse, respectively.
  • the base electrode of the transistor Q; Which is connected to the output 9 of the above said double phase clock via the inverter N is normally held at the ground potential and is brought at a positive potential, e.g., +6 v., during the occurrence of 9. e I
  • the transistor Q is normally cut off and is conductive only during the occurrence of a phase clock pulse. Consequently, the discriminator DSC is effective only during the occurrence of a phase clock pulse, i.e., the decision instants take place with the occurrence of P phase clock pulses.
  • the discriminator DSC is fired and performs the first decision which relates to the polarity of the compressed PAM input signal. This decision is registered 'by the flip-flop FF and is sent to the transmission line (not shown).
  • the current in the input terminal 0 of the discriminator DSC is larger than that in the input terminal 0', the reverse taking place for a negative input PAM signal.
  • the output 5 of the flip-flop FF being brought to the logical l-level and to the logical O-level during the first decision of the encoding process of a positive and of a negative PAM input signal, respectively, it is seen that a PCM code corresponding to a positive and to a negative PAM signal has as first or most weighted digit a land a 0-digit, respectively.
  • the gated-input flip-flops F to F which are coupled to the outputs s and E of the flip-flop FF and which are all enabled during the first digit encoding interval (cp to em at the O-level), memorize the result of this first decision.
  • the gated-input flip-flop F is inhibited, since the pattern ep applied to its input 2 then assumes the l-level, i.e., the ground potential, and consequently, it keeps its registration up to the end of the sixth digit encoding interval.
  • the transistor Q of the synthetizing networks SN; and SN,- is brought to the conductive condition due to the patterns cp and E being then at the l-level and the current path is established from the source S to the transistors Q and Q;, of these networks SN and SN; through the corresponding weighing resistors RW and RW
  • the base of the transistors Q being at the l-level, i.e., at the ground potential, by means of the corresponding fi outputs of F to F and the base of the transistors Q being biased at a positive potential, e.g., +4 v., the reference or constant currents given by the enabled networks 8N and SN flow from the source S through the weighing resistors RW and RW and the collectors a' and a of the corresponding transistors Q and are summed at the input 0, of the discriminator DSC, i.e., at the base of the transistor Q
  • the second decision which takes place in the same manner as thepreviously described first decision, relates to the current level C i.e., the compressed PAM signal above or below this level C,. It is now assumed that the second decision causes a 1-digit to appear again at the output s of the flip-flop FF, i.e., the output s remains in the same condition it has taken at the first decision, this meaning that the PAM input signal is at a higher level than the level C,.
  • the gated-input flip-flops F to F which are still enabled, register the above second digit, i.e., they remain in the same condition, and the gated-input flip-flop F is inhibited from the end of the second digit encoding interval up to the end of the sixth digit encoding interval.
  • the amplification coefiicients G and 6 for this mode of operation are as follows:
  • the synthetizing network 5N is enabled at the end of the previously mentioned second digit encoding interval and the constant current I/ k which flows through the weighing resistor RW and which is equal to the current B B (FIG. 3) is applied to the terminal 0 so that, one may say that the line B B of the compression characteristic is shifted to the parallel position B B
  • the segment B B corresponds to the code numbers +16 to +32.
  • the third decision results in a 0- digit, or O-level output PCM signal appearing on the output s of the flip-flop FF i.e., the level of the PAM signal compressed according to B B is lower than the reference level C,/2
  • the respective outputs f f f of the gated-input flip-flops F F F are brought to the logical O-level, e.g., +6 v., and the gated-input flip-flop F is inhibited from the end of
  • the synthetizing network 5N which gives a reference constant current 1/4 is enabled from the moment the third digit encoding interval ends.
  • This reference current I/4 nOW flows through the collector a since the base of the transistor Q' of the synthetizing network 8N is less positive, i.e., +4 v., than the base of the corresponding transistor Q e.g., +6 v.
  • the encoding process is continued in the same way by successively making active the synthetizing networks SN and 5N which give a reference currents I/ 8 and I/ 16, respectively.
  • a compressed negative PAM signal corresponds to a PCM code number beyond or below the code number 16 according to the two most weighted binary digits of the code being 00 or 01, respectively.
  • a PAM signal amplified according to the line B B and situated in the zone between the current levels C and C',, or outside this zone corresponds to a code number in the PCM code number-zone +16 and 16, or outside this zone according to the two most weighted binary digits of the PCM code being different, or identical to each other, respectively.
  • the identity or not of the above said two most weighted digits of the PCM code is detected by the gating circuit G and the gain of the compressor C0 is switched to the lower gain condition from the end of the second digit encoding interval if this identity occurs.
  • FIG. 8 shows in block diagram an expandor circuit EX similar to the circuit of FIG. 2, but having a complementary characteristic to that shown in FIG. 3, so that the whole compressor-expandor characteristic is linear.
  • the principle of operation of the expandor circuit EX can now readily be understood.
  • the decoder DEC receives the 6-digits of the previous mentioned PCM code in series form, stores them in its memory (not shown) and performs their conversion in parallel form.
  • gain is herein used with a broad meaning and that a gain condition may be an attenuation condition.
  • phase inverter modulator circuit which may provide a negative and a positive gain, e.g., i+1 and 1.
  • This modulator circuit which does not make use of transformers is similar to the circuit of FIG. 2, only the connections between the transistor pair Q Q and the output resistors R R being reversed.
  • the carrier or control signal is applied to the control terminal 0'.
  • the above circuit which may have many applications, e.g., in carrier telegraphy, can also advantageously be used with decoders which have no pedestal voltage, e.g., providing only positive analog signals.
  • the gain coefficient in the case of both pairs of transistors Q Q and Q Q being active (negative gain condition), is given by the relation:
  • the decoder DEC includes a memory (not shown) wherein the successively received PCM digits are stored and after the last digit, the sixth, being received the complete PCM code signal stored in the memory is translated to an analog signal which is applied to the expander.
  • the above memory may, for instance, be constituted by six flipflops. It is then sufiicient to take one output of the flip-flop which memorizes the most weighted digit of the PCM code as the control terminal 0' and to perform the setting of the circuit of FIG. 9 to the involved gain condition.
  • FIG. 10 shows a complete expander circuit adapted to be used with decoders which have no pedestal voltage. It comprises two stages EX and EX in series connection with each other and with the decoder DEC.
  • the first stage EX is similar to the demodulator circuit of FIG. 9 and the second stage EX to the circuit EX of FIG. 8.
  • the setting of the stage EX to the negative or positive gain condition is performed through the control terminal 0' in the manner described hereabove and the setting of the stage EX through the control terminal 0 in the same manner described in connection with the circuit of FIG. 8.
  • the compression or expansion characteristic was constituted by two straight line portions or gain conditions. This has been made only for simplification purposes and it is now obvious that these compressor and expander circuits may easily be adapted to provide a characteristic which is constituted by a larger number of gain conditions, e.g., by connecting in parallel more than two pairs of transistors Q Q and Q Q (FIG. 2) and eventually by providing more than one control terminal 0. It is also obvious that in the latter case of more than two gain conditions, the third and eventually a number of the successive other POM code digits may be used for detecting the zones of dilferent gain conditions, and the gating circiut G of FIG. 6 should comprise more elements.
  • a variable gain amplifier comprising:
  • said first section having at least a first input and at least a first output
  • said second section having at least a first input directly connected to said first input of said first section and at least a first output directly connected to said first output of said first section;
  • control means coupled to said switching means to control the coupling of said generating means to said sections;
  • said switching means being coupled to a predetermined point of both said sections to provide substantially perfect decoupling between the control of said sections and the useful signal path through said sections to said output impedance.
  • said switching means and said control means cooperate to control the electrical connection of said generating means to said predetermined point of said sections to establish at least two distinct linear inputoutput relationships having slopes of the same sign for said amplifier.
  • each of said sections includes a first output, and a second output;
  • said first output of said first section is directly connected to said first output of said second section;
  • said second output of said first section is directly connetced to said second output of said second section
  • said common output impedance includes a first impedance having a first terminal coupled to said first outputs of said sections and a second terminal, and
  • a second impedance having a first terminal coupled to said second terminal of said first impedance and a second terminal coupled to said second outputs of said sections;
  • At least one amplifier output terminal coupled to one of said first terminal of said first impedance and said second terminal of said second impedance.
  • a phase-inverter modulator comprising a variable gain amplifier according to claim 1, wherein said switching means and said control means cooperate to control the electrical connection of said generating means to said predetermined point of said sections to provide a linear input-output relationship having a slope selected from a first slope of given sign representing a positive gain condition and a second slope with a sign opposite said given sign representing a negative gain condition.
  • a phase-inverter modulator including a variable gain amplifier according to claim 1, wherein said first section includes a first output, and a second output; said second section includes a first output symmetrically disposed with respect to said first output of said first section, and a second output symmetrically disposed with respect to said second output of said first section; said first output of said first section is directly connected to said second output of said second section; said second output of said first section is directly connected to said first output of said second section; and said common output impedance includes a first impedance having a first terminal coupled to said second output of said first section and said first output of said second section and a second terminal, and a second impedance having a first terminal coupled to said second terminal of said first impedance and a second terminal coupled to said first output of said first section and said second output of said second section; and further including an amplifier input terminal coupled in common to said first input of both said sections;
  • At least one amplifier output terminal coupled to one of said first terminal of said first impedance and said second terminal of said second impedance.
  • each of said sections includes a first input
  • each of said sections are differential amplifiers.
  • said first section includes a first transistor having a base, an emitter and a collector, and
  • a second transistor having a base, an emitter and a collector
  • said second section includes a third transistor having a base, an emitter and a collector symmetrically disposed with respect to said first transistor, and
  • a fourth transistor having a base, an emitter and a collector symmetrically disposed with respect to said second transistor;
  • first means is coupled to said emitter of both said first and second transistors and said switching means
  • second means is coupled to said emitter of both said third and fourth transistors and said switching means
  • said first terminal of said first impedance is coupled to said collector of both said first and fourth transistors; and said second terminal of said second impedance is coupled to said collector of both said second and third transistors.
  • each of said sections are differential amplifiers.
  • said first section includes a first transistor having a base, an emitter and a collector, and a second transistor having a base, an emitter and a collector; said second section includes a third transistor having a base, an emitter and a collector, and a fourth transistor having a base, an emitter and a collector; said base of both of said first and third transistors are directly connected together; said base of both said second and fourth transistors are directly connected together; said collector of both said first and third transistors are directly connected together; said collector of both said second and fourth transistors are directly connected together; first means is coupled to said emitter of both said first and second transistors and said switching means; second means is coupled to said emitter of both said third and fourth transistors and said switching means; and said common output impedance is coupled between said collectors of said first and third transistors and said collectors of said second and fourth transistors; and further including an amplifier input terminal coupled to at least one of said bases of said fi rst and third transistors and said bases of third and fourth transistors;

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  • Theoretical Computer Science (AREA)
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US550010A 1965-06-24 1966-05-13 Variable gain amplifier and circuits using same Expired - Lifetime US3482180A (en)

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BE (1) BE682909A (enrdf_load_stackoverflow)
CH (1) CH462252A (enrdf_load_stackoverflow)
DE (1) DE1462684A1 (enrdf_load_stackoverflow)
GB (1) GB1138640A (enrdf_load_stackoverflow)
NL (1) NL6508145A (enrdf_load_stackoverflow)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4827664A (enrdf_load_stackoverflow) * 1971-08-09 1973-04-12
US3909719A (en) * 1972-12-29 1975-09-30 Int Standard Electric Corp Balanced PCM encoder
US11791785B2 (en) 2019-12-23 2023-10-17 Imec Vzw Sign switching circuitry

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3168709A (en) * 1960-12-14 1965-02-02 Honeywell Inc Stabilized transistor difference amplifier
US3381142A (en) * 1965-02-15 1968-04-30 Sperry Rand Corp Voltage comparison and gating circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3168709A (en) * 1960-12-14 1965-02-02 Honeywell Inc Stabilized transistor difference amplifier
US3381142A (en) * 1965-02-15 1968-04-30 Sperry Rand Corp Voltage comparison and gating circuit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4827664A (enrdf_load_stackoverflow) * 1971-08-09 1973-04-12
US3909719A (en) * 1972-12-29 1975-09-30 Int Standard Electric Corp Balanced PCM encoder
US11791785B2 (en) 2019-12-23 2023-10-17 Imec Vzw Sign switching circuitry

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GB1138640A (en) 1969-01-01
CH462252A (de) 1968-09-15
DE1462684A1 (de) 1968-11-21
NL6508145A (enrdf_load_stackoverflow) 1966-12-27
BE682909A (enrdf_load_stackoverflow) 1966-12-22

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