US3423603A

US3423603A - Address selection switch for coincidence memory

Info

Publication number: US3423603A
Application number: US503334A
Authority: US
Inventors: Joseph Reese Brown Jr
Original assignee: Burroughs Corp
Current assignee: Unisys Corp
Priority date: 1965-10-23
Filing date: 1965-10-23
Publication date: 1969-01-21
Anticipated expiration: 1986-01-21
Also published as: FR1517783A; DE1499604B2; DE1499604A1; GB1141387A

Description

Jan. 21, 1969 J. R. BROWN, JR

ADDRESS SELECTION SWITCH FOR COINCIDENCE MEMORY Filed Oct. 23. 1965 Mil 70E) Vii/VF I NVENTOR.

United States Patent 2 Claims ABSTRACT OF THE DISCLOSURE There is described a gating circuit for selectively connecting a reactive load directly to ground reference potential through substantially zero impedance or connecting the load to a fixed potential through a very low impedance. The solid state switching arrangement is controlled from a single gating pulse input.

This invention relates to memory circuits and, more particularly, is concerned with an address selection switch with bias restoration for addressing a memory circuit.

Addressable memories such as a magnetic core memory or a thin film memory are well known in which drive currents are provided on input lines to select a particular stored bit or set of bits. The input lines in turn are selectively driven from address information derived from a register through a drive matrix. Typically, the drive matrix includes a transformer for each drive line to the coincident memory. Switching circuits responsive to information derived from the address register permit a selected one of the transformers in the matrix to be connected across a current source. Two switches are involved in selecting one transformer, one switch connecting a row in the matrix to a current pulse source and the other switch connecting a column in the matrix to a reference potential such as ground. The current pulse is passed through the particular transformer in which the switch to the ground reference potential is closed.

In prior art arrangements, when the memory drive operation is completed, the switch to the reference potential is opened and the common line to the transformers controlled by the switch is permitted to return to some standby bias potential. This is usually accomplished by connecting the line through a large resistance to the standby potential source. However, because of stray capacitance, particularly in the transformers, when the line returns to the initial potential, the stray capacitance must be charged up through this large resistance. This time delay puts a limitation on the number of memory address cycles which can be performed in a given time interval.

The present invention is directed to a switching arrangement particularly suited to use in a memory drive matrix which permits rapid recovery of an address line to an initial bias level following a memory select operation. This is accomplished, in brief, by utilizing two switching circuits in effect, one of which is operative to connect an address selection line to a reference potential through a low impedance, and the other of which connects the same line to an initial bias potential through a low impedance path. By restoring the bias potential through a low impedance path, the charge time for the stray capacitance is substantially decreased, permitting higher speed addressing operation of the memory system.

For a more complete understanding of the invention, reference should be made to the accompanying drawings, wherein:

FIG. 1 is a schematic block diagram of a memory system incorporating the features of the present invention; and

Patented Jan. 21 1 969 FIG. 2 is a schematic diagram of the preferred embodiment of the switching circuit.

Referring to FIG. 1 in detail, the numeral 10 indicates a core memory plane in which magnetic cores are arranged in columns and rows. The core memory plane is of the conventional type in which horizontal drive lines respectively couple each of the cores in the respective rows, and a corresponding plurality of vertical drive windings couple each of the cores in the respective columns. One of the horizontal drive lines is indicated at 12. Other horizontal drive lines are indicated at 14, 16 and 18, while vertical drive lines are indicated at 20, 22, 24 and 26. In a typical configuration, of course, the number of drive lines would be much larger, the four horizontal and vertical drive lines being shown by way of example only.

Each input drive line to the memory plane 10 is connected across the secondary of a drive transformer. Thus the input line 12 is connected across the secondary of a transformer 30, the drive line 14 is connected across the secondary of a transformer 32, while the drive lines 16 and 18 are connected across the secondaries of transformers 34 and 36.

Each memory cycle requires a Read pulse and a Write pulse in sequence to be applied simultaneously to one row and one column, the coincidence of a pulse on both a column and a row line at one core being sufiicient to switch flux in that core.

Considering only the row drive lines 12-18 for the moment since the column drive is identical in circuitry, the center taps of the primaries of the transformers 30 and 34 are connected through a common lead to a gate 38. A signal applied to the gate 38 completes a low impedance connection to ground. Similarly, the center taps on the primaries of the transformers 32 and 36 are connected to a gate 40 which provides a low impedance current path to ground. When the

gates

38 and 40 are open, the common leads to the center taps of the primaries of the transformers are held at a positive potential through resistor 42 and resistor 44, respectively. A current path through a respective one of the drive transformers is completed by selecting a first pair of

gates

46 and 48 or a second pair of gates 50 and 52. The

gates

46 and 48 provide low impedance current paths between the Write pulse source and the Read pulse source 56 to respective ends of the primary windings of the transformers 34 and 36 through diodes 58 and 60 and diodes 62 and 64. Similarly, gates 50 and 52 provide low impedance paths from the Write source 54 and Read source 56 to the primaries of the transformers 30 and 32 through diodes 66 and 68 and diodes 70 and 72.

In operation, by selectively operating the gate 40 and the

gates

46 and 48, for example, Read and Write pulses are applied successively to the primary of the transformer 36. By selectively operating the gate 38 and the gates 50 and 52, pulses similarly can be applied to the primary of the drive transformer 30. This address selection and drive circuit is well known in the coincidence core memory art.

In a typical circuit operation, the resistors 42 and 44 have to be fairly large to limit the current and provide the proper voltage swing on the lines to the transformers. The resistors provide a positive bias on the control lines to the transformers on all of the lines except on the line on which the selected gate provides a low impedance path to ground. The difiiculty with such a circuit arrangement is that when the pulse to the gate is terminated, and the gate opens, the common line going to each of the transformers from the gate can be restored to the initial bias level only by recharging any stray capacitance through the relatively large resistor. Stray capacitance is provided to ground through all of the transformers, and in a typical drive array, there may be as many as a hundred such pulse transformers. Thus an RC time constant exists which presents a substantial delay time in the restoration of the bias On all of the transformer primaries. This delay time in turn limits the overall time for a memory cycle to take place. Where memory cycle times of less than a microsecond are of interest, the time delay in restoring the bias level on the selected transformers during a memory cycle becomes prohibitively large.

The present invention is directed to a gating circuit arrangement, shown in detail in FIG. 2, which may be used in place of the

conventional gating circuits

38 and 40 of FIG. 1. The unique gating circuit permits the bias level to be restored in a much shorter time than is possible where the stray capacitance must be recharged through the bias resistor. Referring to FIG. 2 in detail, the gating circuit includes a pair of

NPN transistors

80 and 82 with their base-emitter circuits connected in series between a positive potential and ground through a current limiting resistor 84. The output to the transformers is derived from the collector of the transistor 82. The control input pulse is applied to the base of a transistor 86. Normally the input is at substantially ground potential and transistor 86 is turned otf. When the transistor 86 is turned off, the transistor 82 is also turned off through the resistor 88 connecting the base of the transistor 82 to a negative potential. When the transistor 86 is turned off, its collector rises towards the positive potential to which the collector of the transistor 86 is connected through a load resistor 90. The collector of the transistor 86 is connected through constant voltage dropping diodes 92 to the base of the transistor 80, turning on the transistor 80 when the transistor 86 is turned off. With the transistor 80 turned on, the output to the transformers is clamped to the positive potential applied to the collector of the transistor 80.

When an input pulse is applied to the gate, the base of the transistor 86 is driven positive, turning on the transistor 86. As a result, the collector potential drops, turning off the transistor 80. At the same time, the transistor 82 is turned on, clamping the output to the transformers to substantially ground potential.

From the description of the circuit of FIG. 2, it will be seen that the gating circuit clamps the output to the transformers at either substantially ground or at some positive potential. The charging and discharging of stray capacitance such as indicated by the dotted line at 94 is through a relatively small resistor 84 which may be made quite small or may be left out altogether. The only purpose of the resistor 84 is to ensure that the transistors are not subjected to an overload current in the event that there is a slight overlap in the turn oil? of one transistor and turn on of the other transistor.

From the above description, it will be recognized that an improved drive circuit for a coincidence memory is provided which incorporates an address selection switch which acts to restore the selection line to a particular group of drive transformers to a positive bias potential through a relatively low impedance path. This permits restoration of the bias potential at a much faster rate in spite of the large amount of stray capacitance provided by the large number of transformers connected across the output.

I claim:

1. Apparatus for rapidly switching one end of a resistive load having a reactive component in response to changes in level of an input signal selectively to a first potential or to the same reference potential to which the other end of the load is connected, comprising first and second transistors each having base, emitter and collector electrodes, the first transistor connecting one end of the load to the first potential through the emitter and collector and the second transistor connecting said one end of the load to the reference potential through the emitter and collector, first and second resistors and means providing substantially constant voltage drop connected between the resistors in series across a potential source, the base of the first transistor being connected to the junction of the first resistor and said voltage dropping means, the potential at said junction normally biasing the first transistor into a conductive state, a third resistor connecting the base of the second transistor to a potential such that the second transistor is normally biased off, and switch means for selectively connecting or disconnecting the junction between the second resistor and said voltage dropping means to the base of the second transistor to turn the second transistor on and turn off the first transistor.

2. Apparatus as defined in claim 1 wherein said switch means includes a third transistor having its emitter and collector connected between the base of the second transistor and said junction between the second resistor and the voltage dropping means, and means coupled to the base of the third transistor for biasing the third transistor on or oil, the voltage dropping means including at least one diode connected in a forward biased condition.

References Cited UNITED STATES PATENTS 3,124,758 3/ 1964 Bellamy et al 307-885 3,183,366 5/1965 Brode 307-885 3,271,590 9/1966 Sturman 307-885 3,287,577 11/1966 Hang et al 307-885 OTHER REFERENCES Epsco Bulletin TDC 110, Power Amplifier, November 1958.

JOHN S. HEYMAN, Primary Examiner.

B. P. DAVIS, Assistant Examiner.

US. (:1. X.R.