US3384793A - Semiconductor device with novel isolated diffused region arrangement - Google Patents

Semiconductor device with novel isolated diffused region arrangement Download PDF

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Publication number
US3384793A
US3384793A US532606A US53260666A US3384793A US 3384793 A US3384793 A US 3384793A US 532606 A US532606 A US 532606A US 53260666 A US53260666 A US 53260666A US 3384793 A US3384793 A US 3384793A
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United States
Prior art keywords
region
diffused region
diffused
substrate
junction
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Expired - Lifetime
Application number
US532606A
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English (en)
Inventor
Moriyama Kyoji
Shoda Koichiro
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
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Matsushita Electronics Corp
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Publication date
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor

Definitions

  • FIG. 3 is a plan view of a semiconductor device according to the present invention.
  • the sample is heated in a water vapour saturated oxygen gas atmosphere to 1200 C. for 20 minutes to form a fresh SiO film 11 on the entire surface of the substrate 1, and further openings 12 and 13 are formed respectively at the top surface of the central portion surrounded by the groove 10 and at the bottom surface of the groove 10 by removing portions of the SiO film 11, to which openings are respectively exposed the central N type diffused region 2 and the P type diffused region 5.
  • openings 12 and 13 are formed respectively at the top surface of the central portion surrounded by the groove 10 and at the bottom surface of the groove 10 by removing portions of the SiO film 11, to which openings are respectively exposed the central N type diffused region 2 and the P type diffused region 5.
  • ohmic contacts to the central N type diffused region 2 and the P type diffused region 5 are formed through the openings -12 and 13, respectively, as shown in FIG.
  • the capacity of the condenser constituted by the substrate 1 and the terminal portions 15 and 16' of the metal film 15 and 16 existing thereover since the capacities associated with the first PN junction 8' and the second P-N junction 9' are inserted in series therebetween, the capacity of said condenser is smaller than that of a conventional device, and hence the entire capacities between the base and the collector and between the base and the emitter become smaller, resulting in a fair improvement of high frequency characteristics.

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  • Bipolar Transistors (AREA)
US532606A 1965-03-10 1966-03-08 Semiconductor device with novel isolated diffused region arrangement Expired - Lifetime US3384793A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1414365 1965-03-10

Publications (1)

Publication Number Publication Date
US3384793A true US3384793A (en) 1968-05-21

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ID=11852912

Family Applications (1)

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US532606A Expired - Lifetime US3384793A (en) 1965-03-10 1966-03-08 Semiconductor device with novel isolated diffused region arrangement

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Country Link
US (1) US3384793A (https=)
GB (1) GB1143633A (https=)
NL (1) NL147583B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4316208A (en) * 1977-06-17 1982-02-16 Matsushita Electric Industrial Company, Limited Light-emitting semiconductor device and method of fabricating same

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3041213A (en) * 1958-11-17 1962-06-26 Texas Instruments Inc Diffused junction semiconductor device and method of making
US3210225A (en) * 1961-08-18 1965-10-05 Texas Instruments Inc Method of making transistor
US3275845A (en) * 1962-12-27 1966-09-27 Motorola Inc Field switching device employing punchthrough phenomenon
US3304595A (en) * 1962-11-26 1967-02-21 Nippon Electric Co Method of making a conductive connection to a semiconductor device electrode
US3311963A (en) * 1963-05-16 1967-04-04 Hitachi Ltd Production of semiconductor elements by the diffusion process

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3041213A (en) * 1958-11-17 1962-06-26 Texas Instruments Inc Diffused junction semiconductor device and method of making
US3210225A (en) * 1961-08-18 1965-10-05 Texas Instruments Inc Method of making transistor
US3304595A (en) * 1962-11-26 1967-02-21 Nippon Electric Co Method of making a conductive connection to a semiconductor device electrode
US3275845A (en) * 1962-12-27 1966-09-27 Motorola Inc Field switching device employing punchthrough phenomenon
US3311963A (en) * 1963-05-16 1967-04-04 Hitachi Ltd Production of semiconductor elements by the diffusion process

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4316208A (en) * 1977-06-17 1982-02-16 Matsushita Electric Industrial Company, Limited Light-emitting semiconductor device and method of fabricating same

Also Published As

Publication number Publication date
GB1143633A (https=) 1900-01-01
DE1564312B2 (de) 1972-10-26
NL6603139A (https=) 1966-09-12
DE1564312A1 (de) 1969-09-04
NL147583B (nl) 1975-10-15

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