US3351745A

US3351745A - Barlow etal totaiiisator equipment

Info

Publication number: US3351745A
Authority: US
Publication date: 1967-11-07
Anticipated expiration: 1984-11-07

Description

Nov. 7,1967

9 Sheets-Sheet 1 Filed June 27, 1963 MIME/V7013 JOHN CHARLTON HARLOW KENNETH WILLIAM COCKSEDGE A TERA/5 N 7, 1967 J. c. BARLOW ETAL 3, ,7

TOTALISATOR EQUIPMENT 9 Sheets-Sheet 2 Filed June 27, 1963 TOTALISATOR EQUIPMENT Filed June 27, 1965 9 Sheets-Sheet 5 T I T 775 776 7/7 7/5 775 T/M/ FIG? m 2 7/37 7/4 All 14/2 14/3 AM L l I J L K L w/z wrz i 5 1 5/ JOHN CHARLTON 'IBARLOW P32 [-03, KENNETH WILLIAM COCKSEDGE W I ATTORNEYS Nov. 7, 1967 J. c. BARLOW ETAL 3,351,745

TOTALISATOR EQUIPMENT Filed June 27, 1963 9 Sheets-Sheet 5 A @75/7 v A74 CW3 6 W6 I I //Vl/E/V7'0/i JOHN CHARLTON BARLOW CW2 KENNETH WILLIAM cocxsaoss A TTORA/E )5 Nov. 7, 1967 J. C. BARLOW ETAL TOTALISATOR EQUIPMENT I Filed June 27, 1963 9 Sheets-Sheet 6 //Yl /Y7'0r5 JOHN CHARLTON HARLOW KENNETH WILLIAM COCKSEDGE l J w M W ATFORMEKS NOVP7, 1957 J. c. BARLOW ETAL 3,351,745

TOTALISATOR EQUIPMENT 9 Sheets-Sheet 7 Filed June 27, 1963 i /B2 C80 E HYDE/V7035 JOHN CHARLTON BARLOW KENNETH WILLIAM COCKSEDGE Nov. 7, 1967 File d June 27, 1963 J. c. BARLOW ETAL 3,351,745

, ToTALisAToR EQUIPMENT 9 SheetsShe et 9 F/GJO A /3// AIM/2 4/5 4 T T o PAH Pm I

JOHN CHARLTON BARLOW KENNETH MLUAH GOCKSEDGE M Arman/e 5 INVEA/TORS.

United States Patent 3,351,745 TOTALISATOR EQUIPMENT John Charlton Barlow and Kenneth William Cocksedge, London, England, asssignors to Bell Punch Company Limited, London, England, a British company Filed June 27, 1963, Ser. No. 291,113 Claims priority, application Great Britain, June 28, 1962, 24,822/ 62 5 Claims. (Cl. 235-92) This invention relates to totalisator equipment and it is an object of the invention to provide totalisator equip ment which is capable of operating at high speeds and which is so designed that the number of ticket-issuing machines can be increased without impairing the efliciency of the equipment.

In a known totalisator equipment there are a number of ticket-issuing machines each having a number of runner keys and a number of pool keys. There is also a central control station which has a counter on which all the bets in each pool are recorded. In addition, there is a counter for all the bets placed on each runner in each pool. The central station also includes a control counter which renders each ticket-issuing machine capable of recording a bet in succession. When a runner key and a pool key have been operated in a ticket-issuing machine a call contact is closed in that machine and when the control counter renders that machine operative the closed call contact enables that machine to address the recording equipment in the central station and thus to record a bet.

In a totalisator equipment according to the invention the counters are electronic, that is to say, they include multi-cathode gas-filled counting tubes or ring counters consisting of gas-filled tubes, vacuum tubes or transistors. Such counters are capable of very high speeds of operation and the whole equipment is designed to make the most effective use of these high speeds. On the other hand, it is essential in any totalisator equipment that there should be very little possibility of any incorrect recording of bets and accordingly the equipment is designed so far as possible to fail safe.

From one aspect the invention comprises in a totalisator system including a control station, a plurality of ticket-issuing machines each having a plurality of selector switches, and means for rendering the ticket-issuing machines operative one at a time, wherein the actuation of a switch at an operative ticket-issuing machine connects a current transmitter to a current receiver in the control station through a conductor in a multi-core cable, and wherein the current available from said current transmitter is lessthan twice the response current of said current receiver.

Preferably the current transmitter and the current receiver are, or include, transistors and in this case the collector of the transistor constituting, or forming part of, the current transmitter may be connected through the actuated switch to the emitter of the transistor constituting, or forming part of, the current receiver.

Each ticket machine will normally include a plurality of selector switches for selecting the pool in which a bet is to be made. In this case the actuation of a pool selection switch in an operative ticket-issuing machine preferably connects the collector of a transistor associated with that ticket-issuing machine and constituting, or forming part of, a pool current transmitter to the emitter of a transistor associated with the selected pool and constituting, or forming part of, a pool current receiver. The pool current receiver preferably controls a bi-stable device also associated with the selected pool, the arrangement being such that when any pool selection switch is actuated the bi-stable device associated with the selected pool is set.

Patented Nov. 7, 1967 Once the appropriate pool has been selected by setting of the appropriate bi-stable device the arrangement is such that the required runner may be selected by the actuation of a runner selection switch in the operative ticket-issuing machine. The actuation of a runner selection switch preferably connects the collector of a further transistor constituting, or forming part of, a runner transmitter associated with that ticket-issuing machine to the emitter of a transistor associated with the selected runner and consituting, or forming part of, a runner receiver. The runner receiver controls a further bi-stable device associated with the selected runner, the arrangement being such that when any runner selection switch is actuated the bi-stable device associated with the selected runner is set. Further the arrangement is such that the setting of the bi-stable device associated with the selected runner causes a pulse generator to apply a pulse to the input of a pool counter and also to the input of a runner counter in accordance with the settings of the pool selection switch and the runner selection switch in the operative ticketissuing machine.

From another aspect the invention consists in a totalisator system including a plurality of ticket-issuing machines at least one of which accepts multiple unit stakes, wherein each bet made at said multiple unit stake ticketissuing machine is recorded in selected ones of a plurality of electronic counters at a central control station by the transmission thereto of a plurality of pulses from a multiunit stake electrical pulse generator also located at said central station, wherein the selection of the electronic counters is made by the actuation of switches at said ticket-issuing machine, wherein the actuation of said switches establishes an electric current path between the pulse generator and the selected counters, wherein said pulse generator is caused to generate one pulse in response to the completion of the establishment of the said path, and wherein said pulse generator is caused to generate further pulses each in response to an increase in the registration of the selected counters until a number of pulses equal to the number of units in the stake has been recorded in said counters.

It has already been stated that in normal totalisator equipments there is a total counter anda counter for each runner in each pool. Accordingly the selected one of the plurality of electronic counters referred to above will normally be the total counter for the selected pool and the runner counter in that pool for the selected runner. According to the invention the multiple-unit-stake electrical pulse generator does not produce a further pulse until it has been ascertained that both the pool total counter and the runner counter have increased their registration.

From another aspect, the invention consists in a totalisator system, wherein each bet is recorded on selected ones of a plurality of electronic counters at a central station by the transmission thereto of a pulse from an electrical pulse generator also located at said central station, wherein the selection of the electronic counters is made by the actuation of switches at one of a plurality of ticket-issuing machines which are rendered operative in sequence by means of a control counter located at said central station, wherein the actuation of said switches es-' tablishes an electric current path between the pulse generator and the selected counters which path does not pass through said switches, and wherein means for issuing a ticket at said one ticket-issuing machine are rendered operative in response to the transmission to the selected counters of a pulse, or of a predetermined number of pulses from the generator.

As mentioned above, the selected counters will normally be a pool total counter and a runnercounter in the. same pool and the arrangement should be such that the means for issuing the ticket are only rendered operative when both a pool counter and a runner counter have had pulses transmitted to them. When one or more of the ticket-issuing machines are arranged to accept multipleunit stakes, the arrangement must be such that these machines are not rendered operative to issue a ticket until the pool and runner counters have received the required number of pulses.

It will be appreciated that in most totalisator systems the central control station must be connected to the ticket-issuing machines by long lengths of cable since the ticket-issuing machines are normally distributed at various points around the race track. Accordingly in any system in which sensitive counters are utilised there is a danger that counters may respond to electrical impulses transmitted over the cables when such pulses are not intended for that counter. Accordingly in a totalisator equipment according to the present invention care has been taken to ensure that the danger of such incorrect recording of bets is kept to an absolute minimum. It will also be appreciated that the measures utilised for preventing the occurrence of such incorrect bets are equivalent to the prevention of cross-talk in other forms of communication system so that these measures have a wider application and are not limited to use in totalisator equipment.

Accordingly from yet another aspect the invention consists in a system for the transmission of information from a first address at one station to one of a plurality of second addresses, wherein the second address to which the information is transmitted is selected by a routing device at a further station remote from said one station and connected thereto by means of a multi-core cable, wherein a current transmitter at the first address is connected to a current receiver at the selected second address through the routing device and at least one conductor in said cable, and wherein means are provided to limit the potential at either or both ends of said conductor.

In a totalisator equipment the first station will be the central control station and the further station will be a ticket-issuing machine. The first address may, for example, be a central pulse generator and the second address may be a runner or pool counter. In a practical system the current transmitter and the current receiver are preferably transistors.

Accordingly the invention also consists in a system for the transmission of information from a first address at one station to one of a plurality of second addresses, wherein the' second address to which the information is transmitted is selected by a routing device at a further station remote from said one station and connected thereto by means of a multi-core cable, wherein the collector of a first transistor at the first address is connected to the routing device, wherein the emitter of a second transistor at each second address is connected to the routing device by a conductor in said cable, and wherein the base electrodes of all said second transistors are maintained at the same fixed potential, said fixed potential being substantially equal to the potential of any unconnected conductors in said cable. This fixed potential will normally be earth potential and is preferably fixed by means of a single earth connection in order to prevent earth currents.

To reduce even further any risk of cross-talk, it is proposed that a special cable should be used between the central control station and the ticket-issuing machines. This special cable consists of a central earth surrounded by a plurality of screened individual conductors, the whole being enclosed in an outer screening layer.

It has already been stated that in a totalisator system according to the present invention an electric current path is set up between a pulse generator and a number of electronic counters, for example, a pool total counter and a runner counter. It is required that the pool total counter and the runner counter be fed in parallel, but in order to ensure that the bet is registered in both the pool total counter and in the runner counter in that Cir 5 runner counter in that pool have increased their registration.

The preferred way of establishing the current paths in a totalisator according to the invention is by means of AND gates and the system used for establishing these paths may be applied to communication systems other than totalisator equipments. The term AND gate is used herein to define a coincidence circuit which provides an output when both or all of its inputs are energised. In the description of one embodiment of the invention which follows hereinafter, each AND gate provides a negative output when both or all of its inputs are made negative, and accordingly in the particular description the term energised is intended to signify that an input has been made negative. On the other hand, it is to be understood that such gates operate equally well to provide a positive output when both or all of their inputs are made positive and the invention is not limited to the use of AND gates with negative outputs.

In order to reduce the risk of wrong recordal of bets a system according to the invention is arranged in such a way that it is impossible for, for example, more than one runner counter to be connected to the central pulse generator at the same time and again equivalent requirements may be met in systems other than totalisator equip- 0 ments.

Accordingly from yet another aspect the invention consists in a system for energising one input of a selected one of a plurality of AND gates, wherein one input of each of the AND gates is connected to the collector of a p-n-p type transistor and through a resistor to the negative terminal of a source of electric current, wherein the emitter of each of said transistors is connected together with the emitter of a further transistor whose collector is also connected through a resistor to said nega- 4-0 tive terminal through a common resistor to the positive terminal of said current source, wherein the base electrodes of said transistors and said further transistor are normally held at such potentials that ony the further transistor is conducting, wherein means are provided for changing the potential of the base electrode of each of said transistors so that it conducts in place of said further transistor, and wherein the arrangement is such that when one of said transistors is rendered conductive the one input of the AND gate connected to its collector will 0 be energised whereas, if more than one of said transistors are rendered conductive at the same time, the resulting change of potential of each of their collectors will be insuflicient to energise the AND gate connected thereto. It is to be understood that the circuit arrangement defined in the preceding paragraph is suitable for use with AND gates the inputs of which are energised by means of negative potentials. However a similar circuit arrangement can be designed for operation with AND gates requiring positive inputs. Various modifications may be made to give the required results, but one possibility is to use n-p-n type transistors in place of p-n-p type.

A method of performing the invention will now be described with reference to the accompanying diagrammatic drawings in which:

FIGURE 1 is a simplified circuit diagram illustrating the principle of current sharing which is extensively used in a totalisator system according to the invention;

FIGURE 2 is a simplified circuit diagram illustrating the method used in a totalisator system according to the invention for passing information by cable from the central equipment of the totalisator to the ticket-issuing machines and vice versa;

FIGURES 3 and 3A together constitute a block diagram of the totalizer system, FIGURE 3A fitting to the right of FIGURE 3;

FIGURE 4 is a simplified circuit diagram of the unit A1 used in the totalisator system illustrated in FIGURES 3 and 3A;

FIGURE 5 is a simplified circuit diagram of the unit L used in the totalisator system illustrated in FIGURES 3 and 3A;

FIGURE 6 is a simplified circuit diagram of the unit CW used in the totalisator system illustrated in FIG- URES 3 and 3A;

FIGURE 7 is a simplified circuit diagram of the unit C1 used in the totalisator system illustrated in FIGURES 3 and 3A;

FIGURE 8 is a simplified circuit diagram of the unit 1B used in the totalisator system illustrated in FIGURES 3 and 3A;

FIGURE 9 is a simplified circuit diagram of the unit K used in the totalisator system illustrated in FIGURES 3 and 3A; and

FIGURE 10 is a simplified circuit diagram of the unit G used in the totalisator system illustrated in FIGURES 3 and 3A.

It is to be understood that the various units A1, A2, A3 and so on are all similar to the unit A1 illustrated in FIGURE 4 and the remaining units may be derived from FIGURE 4 by appropriate changes in the reference numerals used for the terminals. Similarly it is to be understood that the unit CP is similar to the unit CW and again may be derived therefrom by appropriate changes in the reference numerals used for the terminals. Similar considerations apply to the units C1, C2 and C3. Further the unit 5B is similar to the unit 13 illustrated in FIGURE 8 except that it includes a 6-stage ring counter in place of the 2-stage ring counter illustrated.

Before describing the complete layout of a totalisator system according to the invention, a brief description will be given of the principle of current sharing and of the methods used for passing information between the central equipment of the totalisator and the ticket-issuing machines.

A simplified circuit diagram illustrating the principle of current sharing is shown in FIGURE 1 and it will be seen that the drawing is divided into three sections, P1, P2 and P3. These divisions are intended to illustrate separate portions of the equipment which may be located either in close proximity or at considerable distances from each other.

References hereinafter to positive and negative potentials are to be understood as defining potentials which are respectively positive or negative with respect to a fixed potential of 0 volt.

The circuit elements illustrated in portion P1 comprise a p-n-p transistor T1 the base electrode of which is connected to a terminal M1 and the emitter of which is connected to a line S1. The collector of this transistor is connected to a terminal M6 and through a resistor R2 to a line 82 which is connected to a source of negative potential. The line S1 is connected through a resistor R1 to a source of positive potential. The potential of the terminal M1 will be assumed to be fixed at 0 volt. Since the transistor T1 is a p-n-p type transistor, and since its emitter is positive with respect to its base electrode this transistor will be normally conductive and accordingly there will be a voltage drop across each of the resistors R1 and R2. As a result of the voltage drop across the resistor R2, the terminal M6 will be at a potential which is less negative than that of the line S2.

The circuit elements illustrated in the portion P2 comprise a p-n-p type transistor T2, the base electrode of which is connected to a terminal M2 and the emitter of which is connected to the line S1. The collector of this transistor is connected to a terminal M7 and through a resistor R3 to the line S2.

The portion of the equipment P3 includes a p-n-p type transistor T3, the base electrode of which is connected to a terminal M3 and the emitter of which is connected to d the line S1. The collector of this transistor is connected to a terminal M8 and through a resistor R4- to the line S2.

If the terminals M2 and M3 are positive, the transistors T2 and T3 will be non-conductive and current will flow from the positive voltage source through resistor R1 to the emitter of the transistor T1 as explained above. The majority of this current will flow through the resistor R2 to the negative voltage source. However, should the base electrode of the transistor T2 or the transistor T3 be made negative, then current will cease to flow to the emitter of transistor T1 and will flow into the transistor whose base electrode has been made negative. In each case, the amount of current flowing is determined by the potential difference between the positive and negative supply terminals, the resistor values and the base electrode potential of the conducting transistor. Thus if, for example, the terminal M2 is made negative, the transistor T2 will conduct in the place of the transistor T1. As a result, current will cease to flow through the resistor R2 and will commence to flow through the resistor R3. Thus the potential of the terminal M6 will become more negative and the potential of the terminal M7 will become less negative.

A simplified circuit diagram illustrating the method used for passing information by cable from the central equipment of the totalisator to the ticket-issuing machines and back is illustrated in FIGURE 2, and it will be seen that the drawing is divided into four sections P4, P5, P6 and P7. The portions P4, P5 and P7 will be assumed to be located in the central equipment, but the portion P6 will be assumed to be located at a ticket-issuing machine.

The circuit elements illustrated in portion P4 comprise a pnp transistor T4, the base electrode of which is connected to a terminal M9 and the emitter of which is connected to a line 83. The collector of this transistor is connected to a terminal M12 and through a resistor R6 to a line S4. The line S3 is connected through a resistor R5 to a positive potential and the line S4 is connected to a negative potential. The terminal M9 is held at a positive potential which is lower than the positive potential to which the line S3 is connected through the resistor R5.

The circuit elements illustrated in portion P5 comprises a p-n-p type transistor T5, the base electrode of which is connected to a terminal M10 and the emitter of which is connected to the line S3. The collector of this transistor is connected to a line S5.

The only circuit element is the position P6 is a switch V which makes or breaks the connection between the line and a line S6.

The circuit elements illustrated in the portion P7 comprise a transistor T6, the base electrode of which is connected to a terminal M11 and the emitter of which is connected to the line So. The collector of this transistor is connected to a terminal M13 and through a resistor R7 to the line S4. The terminal M11 is maintained at 0 volt.

It will be assumed that the terminal M10 can be set at two positive potentials, one of which is higher than the potential of the terminal M9 and the other of which is lower than the potential of terminal M9. When the terminal M10 is set to the higher positive potential, current will flow into the transistor T4. Thus there will be voltage drops in the resistors R5 and R6 and the potential of the terminal M12 will be less negative than the line S4. However, when the terminal Mltl is set to the lower positive potential, current will flow into the transistor T5 instead of into the transistor T4. Provided the contact V is closed, the majority of the current flowing into the transistor T5 will flow along the lines S5 and S6 into the transistor T6. Again the majority of this current will flow through the resistor R7 to the line S4. Consequently, when the contact V is closed a change of potential on the terminal M10 will cause a change in the current flowing through the resistor R7 and consequently cause a change in the potential of the terminal M13, thus passing information from the portions P5 and P6 to the portion P7. It is to be understood that there will normally be a plurality of portions P7 and that contacts or switches in the ticket-issuing machine P6 operate to connect the line S to one of a number of different lines S6. Information concernnig the switch that has been closed will be available at the central equipment by virtue of the decreased negative potential on one particular terminal M13.

FIGURES 4 to 11 of the drawings which illustrate various parts of the totalisator system represented by the block diagram of FIGURE 3 have been simplified by the omission of power supplies and of all components which are not essential to an understanding of the invention. Many parts of the circuit operate in the same manner as has been described with reference to FIGURES 1 and 2 of the drawings, and in such cases a clear understanding of the operation of the circuit may be obtained by reference to these figures and the description relating thereto.

Further circuit elements which are used extensively in the totalisator system to be described are the logical elements known as AND and OR gate circuits. The operation of these elements is well-known and need not be described in detail. In each case the diode rectifiers which constitute, or form part of, each gate are illustrated in the drawing, and each gate is referred to in the description by the references used for its rectifiers.

Also shown in FIGURES 4 to 11 of the drawings are a number of bi-stable and mono-stable devices. Each of these devices includes two transistors, only one of which is conductive at any one time. In the drawings each of these devices is shown as a pair of transistors enclosed in a rectangular box divided into two halves. The half of the box containing the transistor which is conductive in the unset state of the device is indicated by a diagonal line in the case of a bi-stable device, and by a pair of crossed diagonal lines in the case of a mono-stable device. Where two inputs are shown for a bi-stable device the energisation of one of these inputs will set the device, and the energisation of the other input will unset the device. In many cases, however, only a single input is shown and in these cases the application of a negative potential to the input will set the device and the application of a posi tive potential to the input will unset the device.

Also shown in the drawings are a number of ring counters. These counters may be of any convenient type but are shown in the drawings as including one gas-filled trigger tube for each stage of the counter. Each counter is stepped by the application of pulses to an input terminal, and this input terminal is shown as being connected through individual capacitors to the trigger electrodes of all the trigger tubes. This is the normal arrangement in a pulse-plus-bias type of counter, and such a counter may advantageously be used. Outputs are shown as being taken from the cathodes of the trigger tubes, but it is to be understood that in practice the output would probably be taken from a tapping on a cathode resistor.

The totalisator system of which a block diagram is illustrated in FIGURE 3 of the drawins includes a number of ticket-issuing machines of which only three are illustrated. These three ticket-issuing machines are indicated by the references TIMI, TIM2, and TIM3. The system to be described is designed for a Place pool, a Win pool and a number of Runners, but in order to simplify the drawing as far as possible, the system illustrated has been limited to three runners. It will be under stood that a system according to the invention may be designed with any number of ticket-issuing machines and that there is no limitation on the number of runners. Further additional pools other than the Win pool and the Place pool may be provided. This system can equally well be designed as a Forecast equipment.

The majority of the equipment illustrated in the drawings is located at a central station and long lines run from the central station to the ticket-issuing machines. These long lines consist of special cables with individually screened conductors.

Counters with visual indicators are provided for the pools and runners and it is to be understood that these counters control lamp boxes or other forms of public indicator which form no part of the present invention and accordingly are not illustrated. The counter for the Win Total pool is indicated by the reference WT, the counter for the Place Total pool is indicated by the reference PT, and the counters registering the Win and place bets for the various runners are indicated by the references W1, P1, W2, P2, and W3 and P3 respectively.

Associated with each ticket-issuing machine is a set of equipment which is preferably constructed as a single unit. The sets of equipment for the ticket-issuing machines TIMI, TIM2 and TIM3 are indicated by the references A1, A2 and A3 respectively. As in known totalisator systems the various ticket-issuing machines are rendered operative in sequence and this sequential operation is controlled by a control counter G.

In the system being described some of the ticket-issuing machines are designed to accept bets of a single basic amount; for example, 2/d., while other ticket-issuing machines are designed to accept bets in multiples of this amount. In the particular embodiment illustrated ticketissuing machines TIMI and TIM2 are arranged to accept bets of the basic amount and ticket-issuing machine TIM3 is designed to accept bets of five times this amount. For this purpose a single bet is recorded each time a ticket is issued by TIM1 or TIM2, whereas five bets are recorded each time a ticket is issued by TIM3. The equipment which controls the number of bets entered in the equipment is contained in a single-bet unit 18 and a five-bet unit 5B.

The totalisator illustrated further includes control equipment associated with the Win and Place pools and with the various runners. This equipment is designated by the references CW, CP, C1, C2 and C3. The equipment further includes a unit K which collects the information that a bet has been recorded in the counters and passes it to a unit L which will be referred to as the reservoir unit.

When a pool key and a runner key have been actuated in any ticket-issuing machine a call contact will be closed and as a result the potential of a terminal (T11 in the case of TIMI, T21 in TIM2 and so on) will be made less positive. This terminal is connected by means of a line (C1 in the case of TIMI, C2 in the case of TIM2, and so on) to the A unit associated with the calling ticket-issuing machine. In the case of TIMI this unit is A1 and the line C1 is connected to a terminal A11. The terminal A11 is connected to one input of a bi-stable device TlA, T2A (FIGURE 4) which is set by the change of potential on the line C1. As a result this bi-stable device energises (i.e. applies a negative potential to) one input of an AND gate, D4A, DSA, D7A, another input of which is energised by the output of a second bi-stable device TSA, T4A, the function of which will be described hereinafter. The third input of this AND gate is connected to a terminal A15 which is in turn connected through the line H1 to the terminal G1 of the control counter G.

The control counter G is shown with six output terminals G1 to G6 which it energises (i.e. makes negative) in sequence, and these output terminals are connected through H lines to corresponding ticket-issuing machines. When the control counter G energises its output terminal G1, all the inputs of the AND gate in the unit A1 are energised and a negative potential appears at its output. This negative potential is applied to the base electrodes of four transistors T8A, T9A, T11A, TIGA through an emitter following T7A. The emitter of the first of these transistors TSA is connected to a terminal A19, the emitter of the second transistor T9A is connected to a terminal A18, the emitter of the third transistor TllA is connected to a terminal A17, and the emitter of the fourth transistor T10A is connected to a terminal A16.

The terminal A19 is connected by a line I common to all the A units to a terminal L5 in the reservoir unit L. The terminal L5 is connected to the emitter of a normal- 1y conducting transistor T11M (FIGURE 5) which may be considered to be similar to the transistor T4 illustrated in FIGURE 2. The operation of this part of the system is similar to that described with reference to FIG- URE 2 and the line I may be considered to be equivalent to the line S3 in FIGURE 2. Further the transistor TBA in the unit A1 may be considered to be equivalent to the transistor T5 in FIGURE 2. The energisation of all the inputs of the AND gate D4A, DSA, D7A in the unit A1 causes the base electrode of the transistor T8A in that unit to be made less positive than that of the transistor T11M in the unit L whose emitter is connected to the terminal L5. Thus the transistor TSA in the unit A1 passes current which was previously flowing through the transistor T11M in the unit L. The collector of the transistor T11M in the unit L is connected to a terminal L6 which may be considered to be equivalent to the terminal M12 in FIGURE 2 and thus the potential of this terminal is made more negative by the change in current flow. The terminal L6 is connected to a terminal G7 in the control counter G and the increased negative potential on the terminal G7 causes the control counter to stop with the output terminal G1 energised.

In the unit A1 the collector of the transistor T8A is connected to a terminal A12 and thence to a line X1. Accordingly this line may be considered to be equivalent to the line S5 in FIGURE 2. The line X1 is connected to a terminal T12 in the ticket-issuing machine TIM1 and is thence connected to a terminal T18 or T19 in accordance with whether a Win Pool key or a Place Pool key in the ticket-issuing machine has been operated. For the purpose of the present explanation it will be assumed that the Win Pool key has been operated with the result that the terminal T12 is connected to a terminal T19. The terminal T19 is connected through a line W, which may e considered to be equivalent to the line S6 in FIGURE 2, to a terminal CW1 of the unit CW. In this unit the terminal CW1 is connected to the emitter of a transistor T13 (FIGURE 6) in the same way as the line S6 is connected to the emitter of the transistor T6 in the circuit illustrated in FIGURE 2. The base electrode of this transistor TlB is held at volt so that the circuit operates in the same way as described with reference to FIGURE 2. Accordingly, as explained with reference to the terminal M13 in FIGURE 2, the collector of the transistor TllB in the unit CW will become less negative and this change of potential is used to set a bi-sta'ole device T313, T413 in the unit CW. When this bi-stabie device is set, it applies a negative potential through an emitter follower T513 to the base electrode of a transistor TdB whose emitter is connected to a terminal CW3. The terminal CW3 is connected through a line Q to a terminal L15 in the reservoir unit L. The emitter of a transistor T 1M (FIGURE is connected to the terminal L15 and this transistor may be considered to be equivalent to the transistor T1 in FIGURE 1, while the transistor T63 (FIG- URE 6) whose emitter is connected to the terminal CW3 may be considered to be equivalent to the transistor T2 in FIGURE 1. Accordingly current ceases to flow through the transistor TlM in the unit L and its collector electrode becomes more negative. Also connected to the line Q is a terminal CR3 in the unit CP. This terminal is connected to the emitter of a transistor T6B which is equivalent to the transistor T3 in FIGURE 1. It is to be understood that, if the Place Pool key in the ticket-issuing machine is actuated instead of the Win Pool key, the transistor T613 in the unit CP will take the current from the transistor T1M in the reservoir unit L in place of the transistor T6B in the unit CW.

The negative change of potential caused by the transistor T1M in the reservoir unit ceasing to conduct is converted to a positive change by means of a further transistor T2M and this positive change is applied to the base electrode of a transistor TSM whose emitter is connected to a terminal L41). This terminal is connected through a line K to the terminal A18 in the unit A1 (FIG- URE 4). As already stated, the emitter of the transistor T9A in the unit A1 is connected to the terminal A18 and the raising of the potential on the base: electrode of the transistor T3M in the unit L causes the transistor T9A in the unit A1 to become conductive in place of the transister T3M in the unit L. It is to be noted that the line K is also connected to a terminal AZfi in unit A2 and a terminal A38 in unit A3 and is thus connected to the emitter of a transistor in each of these units. However, neither of these transistors becomes conductive since its base electrode has not been primed by the operation of the AND gate in that unit.

The collector of the said transistor T A in the unit A1 is connected to a terminal A13 and thence through a line Y1, which may be regarded as being equivalent to the line S5 in FIGURE 2, to a terminal T13 in the ticketissuing machine TIM1. The terminal T13 is connected to one of the terminals T15, T16 or T17 in accordance with the Runner key that has been actuated in that ticketissuing machine. For the purpose of the present example it will be assumed that terminal T13 is connected to the terminal T17 by the closure of the Runner 1 key. The terminal T17 is connected through a line 1, which is equivalent to the line So in FIGURE 2, to a terminal C11 of the unit C1. The terminal C11 is connected to the emitter electrode of a transistor TIC (FIGURE 7) which is equivalent to the transistor T6 in FIGURE 2, and the collector electrode of which is connected to one input of a bi-stable device T2C, TdC in a manner similar to that described above with reference to the unit CW. Accordingly this bi-stable device is set as a result applies a negative potential to the base electrodes of four transistors, T6C, T7C, TSC and T 9C through an emitter follower TSC. The emitter of the transistor TSC is connected to a terminal C14, the emitter of the transistor T9C is connected to a terminal C15, the emitter of the transistor T6C is connected to a terminal C16, and the emitter of the transistor T7C is connected to a terminal C17.

The terminal C16 is connected to a terminal 1B5 in the unit 113 and this terminal is connected to the emitter of a transistor T6D (FIGURE 8) which is normally conductive and the collector electrode of which is connected to one input of an AND" gate 136D, D7D. When the negative potential is applied to the base electrode of the transistor T6C in unit C1 whose emitter is connected to the terminal C16, this transistor becomes conductive in place of the transistor TeD whose emitter electrode is connected to the terminal 1B5. It is to be noted that terminals C26 and C36 are also connected to the terminal and that the emitters of two further transistors TC are connected in parallel with the emitters of the transistors referred to in the units C1 and 1B. Thus all four transistors operate according to the current-sharing principle described with reference to FIGURE 1 and the transistor T6C that takes the current from the normally conducting transistor T6D in the unit 1B depends on the Runner Key that has been depressed in the operative ticket-issuing machine. In any case the said one input of the AND gate DGD, D7D in the unit 1B is energised. It is to be noted that the terminals C17, C27 and C37 are connected to a terminal 535 in the unit 5B and one input of an AND gate in this unit is also energised.

It will be recalled that the emitter of the fourth transistor T10A in the unit A1 is connected to the terminal A16 and this terminal is connected through a line B1 to a terminal L1 in the reservoir unit L. The terminal L1 is connected to the emitter of a transistor T7L whose coilector is connected to a terminal L13. Further the terminal L13 is connected to a terminal 1B1 in the unit 1B and this terminal constitutes a second input of the AND gate referred to above. When the negative potential is ap plied to the base electrode of the transistor T10A in the unit A1, this transistor conducts and takes current from the transistor T7L whose emitter is connected to the terminal L1. Accordingly the terminal L13 is made more negative and both inputs of the AND gate D6D, D7D in the unit 1B are energised. Similarly, the second input of the AND gate D6D, D7D in the unit 58 is connected to a terminal B1 and thence to a terminal L in the reservoir unit L. This terminal is connected to the collector of a transistor TSL whose emitter is connected to a terminal L2 which leads through a line B5 to a terminal A36 on unit A3. The terminal A36 is the equivalent of the terminal A16 in the unit A1 and it will thus be seen that the second input of the AND gate D6D, D7D in the unit 5B is energised if a bet is being recorded from TIM3, but that the second input of the AND gate in unit 1B is energised if a bet is being recorded from TIMI or TIM2. The unit 1B includes a 2-stage ring counter NlE, N2E and is designed to cause the equipment to register a single bet, whereas the unit 5B includes a 6- stage ring counter NlE N6E and is designed to cause the equipment to register five bets. In the present example only a single bet is to be registered and accordingly the unit 1B is operative and the unit 5B is non-operative.

The output of the AND gate D6D, D7D in the unit B1 is coupled to the input of the 2-stage ring counter N1E, N2E through a pulse forming-circuit PF, an OR gate D9D, D10D and a pulse amplifier PA. The pulseforming and amplifying circuits may be of any type suitable for producing a drive pulse of the appropriate shape and amplitude for the ring counter NlE, N2E. Similarly the ring counter itself may be of any known kind, but it may be remarked that a counter using cold-cathode gas-filled trigger tubes with a pulse-plus-bias form of drive, is particularly convenient.

Initially the counter NlE, N2E registers 0, but the energisation of its input by the pulse from PA causes it to step from O to 1. When the counter steps from O to 1, it applies a voltage step to the base electrode of a transistor T4E which is normally conductive, and the collector of which is connected to the base electrode of a transistor T3E. The voltage step applied to the base electrode of the transistor T4E cuts off this transistor and thus applies a negative potential to the base electrode of the transistor T3E. The emitter of the transistor T3E is connected to the emitter of a normally conducting transistor TlD, and these two transistors operate in a manner similar to that described with reference to the transistors T1 and T2 in FIGURE 1. Thus when the negative potential is applied to the base electrode of the transistor T3E, the current through the transistor T1D is reduced, and the collector electrode becomes more negative. The negative-going voltage step on the collector of the transistor T1D is applied through a capacitor C3D to the input of a mono-stable device T3D, T4D in the unit 18 which is accordingly set. The monostable device T3D, T4D applies a positive pulse to a terminal 1B6. This terminal is connected to terminals CW4 and CP4 in the units CW and CP respectively. The resulting positive change of potential of the terminals CW4 and CP4 is applied in each of the units CW and CP through an OR gate B8B, B9B to the base electrode of a transistor T10B the collector of which is connected to one input of an AND gate DltlB, D7B. Thus one input of the AND gate is energised in each of the units CW and CP, but the other input of each of these AND gates D10B, D7B, is connected to the collector of a transistor T7B the base electrode of which is connected through a diode D4B to the collector of the transistor T6B. As only the transistor T6B in the unit CW is conductive, as explained above, only the AND gate in the unit CW will have both its inputs energised. As a result a negative potential will be applied from the output of the AND gate through a diode D5B to the base electrode of a transistor T88 and a pulse will be applied to the terminal CW2 through a capacitor ClB. This pulse is conveyed to the input WTl of the counter WT and accordingly one bet will be recorded by this counter. As the counter steps from one number to the next, it will generate a pulse on a terminal WTZ and this pulse is passed to a terminal K1 of the unit K.

In addition to applying a pulse to the terminal CW2 the AND gate D108, D7B in the unit CW also causes a positive pulse to be applied from the collector of the transistor T8B to the base electrode of a normally conductive transistor T9B whose emitter is connected to a terminal CW6. The terminal CW6 is connected to the terminals C14, C24 and C34 in the units C1, C2 and C3 respectively. As already explained, the emitter of the first transistor T in the unit C1 is connected to the terminal C14 and this transistor has been primed by the setting of the bi-stable device T2C, T4C in this unit. The collector of this transistor TSC is connected through a capacitor C1C to a terminal C13 which is connected to the input terminal W11 of the counter W1. With the transistor T9B in the unit CW has the positive pulse applied to tis base electrode, the primed transistor T80 in the unit C1 conducts for the duration of the pulse and the input of the counter W1 is energised so that one bet is recorded in this indicator. As the counter W1 steps from one number to the next, it will generate a negative pulse on the output terminal W12 and this pulse is applied to a terminal K3 of the unit K.

The unit K functions as a combination of AND gates and OR gates and supplies an output on the terminal K9 when the terminal K1 is energised at the same time as one of the terminals K3, K5 or K7 or when the terminal K2 is energised at the same time as any of the terminals K4, K6 or K8. The unit K which is illustrated diagrammatically in FIGURE 9 consists essentially of two similar parts, one part dealing with Win bets and the other part dealing with Place bets, and the part dealing with Win bets is illustrated in the upper half of the FIGURE 9 and the part dealing with Place bets is illustrated in the lower half. Similar reference numerals have been used for similar components in the two parts, those components which deal with Place bets being distinguished by being primed. As the two parts are virtually dentical, only the part dealing with Win bets will be described in detail.

The terminals K3, K5 and K7 are respectively connected to the base electrodes of three transistors T17, T18 and T19, and the emitters of these three transistors are connected to a common resistor (not shown) together with the emitter of a further transistor T2K. The transistor TZK is normally conductive, and these four transistors operate on the current-sharing principle as described with reference to FIGURE 1 of the drawings. Thus when a negative pulse is applied to any of the terminals K3, K5 or K7, the respective transistor T17, T18 or T19 conducts in place of the transistor T2K, and the collector of the transistor TZK becomes more negative. This negative charge of potential is applied to the input of a bi-stable device including two transistors T4K and TSK in which the transistor TSK is normally conductive. The application of the negative potential to the input of this bi-stable device makes the transistor T4K conduct in place of the transistor TSK, and the collector of the transistor TSK becomes more negative. The collector of the transistor TSK is connected to the anode of a diode D2K forming an AND gate with a further diode D1K. Thus when the bi-stable device T4K, T 5K is set, one input of the AND gate D2K, DIK is energised.

The terminal K1 is connected to the base electrode of a transistor T23 the emitter of which is connected together with the emitter of a further transistor T1K to a common resistor (not shown). Thus these two transistors operate on the current-sharing principle and when a negative pulse is applied to the terminal K1, the transistor T23 conducts in place of the normally conductive transistor TlK. Accordingly, the collector of the transistor TlK becomes more negative, and this negative change of potential is applied to the input of a bi-stable device T8K, T9K, in which the transistor T9K is normally conductive. The negative potential sets the bi-stable device and thus makes the transistor TSK conduct in place of the transistor T9K. Thus the collector of the transistor T9K becomes more negative, and as this collector is connected to the anode of the diode D1K, both inputs of the AND gate DZK, DlK are energised and a negative potential appears at the output of this AND gate.

The negative potential at the output of the AND gate is applied to the input of a pulse-forming circuit PFK, and the resulting pulse is amplified in a pulse amplifier PAK. The positive-going amplified output pulse is applied to one input of an OR gate D4K, D4K' and this pulse appears on the output terminal K9.

It will be appreciated that an output pulse will also appear on the terminal K9 when any of the terminals K4, K6 or K8 are energised at the same time as the input terminal K2.

In addition to being applied to the input of the OR gate D4K, D4K', the amplified output pulse from the amplifier PAK is also applied through a capacitor CIK to the input of the bi-stable device T4K, TSK. It will be recalled that this bi-stable device was set by means of a negative pulse and accordingly it is unset by the application of this positive pulse. Similarly the bi-stable device T8K, T9K, is unset by the application of the positive pulse from PAK to its input through the capacitor CZK.

In the example being described inputs have been supplied to the terminals K1 and K3 and accordingly the output K9 is energised. It will be appreciated that the counters WT and W1 may not step at precisely the same instant and this is the reason why the bi-stable devices are provided at the inputs of the AND gates. Thus when the selected pool total and runnner indicator counter register a bet, two pulses are fed into unit K. Only when the AND gate D1, D2 has received two pulses is terminal K9 energised.

The terminal K9 is connected to a terminal L14 of the reservoir unit L and the terminal L14 is connected through transistors TIL, TSL, T3L, which are required for correct phasing and pulse shaping to one input of each of two AND gates DZL, D3L, and D1L, D4L. The other input of a first one of these AND gates D2L, D3L, is connected to the terminal L13 and the other input of the second of these AND gates DlL, D4L, is connected to the terminal L10. It will be recalled that, because the ticket-issuing machine TIMI deals with single bets, the terminal L13 is energised whereas the terminal L10 is not. Accordingly both inputs of the first AND gate D2L, D3L are energised and a negative potential is applied to the base electrode of a transistor T4L Whose emitter is connected to a terminal L12. This transistor may be considered to be equivalent to the transistor T2 illustrated in FIGURE 1. The terminal L12 is connected to a terminal 1B2 in the unit 113 and the terminal 1B2 is connected to the emitter of a transistor T17D which may be considered to be equivalent to the transistor T1 illustrated in FIGURE 1. Thus the transistor T4L whose emitter is connected to the terminal L12 draws current in place of the transistor T17D and the collector electrode of this latter transistor becomes more negative as explained with reference to terminal M6 in FIGURE 1. This negativegoing change of potential is applied through a capacitor C8D to the second input of the OR gate D9D, D10D, so that a further pulse is applied through the amplifier PA to the input of the 2-stage ring counter NIE, NZE, which is accordingly stepped from 1 to 0. As the counter steps from 1 to 0, it applies a positive potential to a transistor TZE which became conductive when the ring counter stepped from to l. The resulting negative potential on the collector of T2E is applied to the base electrode of a transistor TIE the emitter of which is connected to a terminal 1B3. This terminal is connected to a terminal L11 in the reservoir unit L and the terminal L11 is connected to the emitter of a transistor T9M which may be considered to be equivalent to the transistor T1 illustrated in FIGURE 1. Accordingly current is caused to flow through the transistor TIE whose emitter is connected to the terminal 1B3 instead of through the transistor T9M whose emitter is connected to the terminal L11. The collector of the transistor T9M is connected to one input of an AND gate D8M, D7M, the other input of which is connected to the collector of a further transistor TlllM whose emitter is connected to a terminal L8. The terminal L8 is connected to a terminal 5133 in the unit 5B, which terminal is equivalent to the terminal 133 connected to the transistor T9M. Since, in the present case, the ring counter in the unit 5B is on O, the transistor T10M is nonconductive and its collector is thus negative. Thus, when the collector electrode of the transistor T9M becomes more negative, both inputs of the AND gate are energised and its output becomes more negative. This change of potential is converted to a positive-going change by means of a further transistor TSM whose base electrode is connected to the output of the AND gate through a capacitor C3M. This positive-going change is applied through an emitter follower TSM to the base electrode of a normally conductive transistor T4M whose emitter is connected to a terminal L3. This terminal is connected through a line L to the terminals A17, A27 and A37 in the units A1, A2 and A3 respectively. It. will be recalled that the emitter of the transistor T11A in the unit A1 is connected to the terminal A17 and hence, since this transistor has been primed by the AND gate in the unit A1, it will draw current in place of the transistor T4M whose emitter is connected to the terminal L3. The collector electrode of the transistor T11A in the unit A1 is connected through a capacitor C6A to the emitter of the transistors T 3A and T4A which constitute the second bistable device in this unit. Consequently when this transistor T11A becomes conductive the said second bi-stable device T3A, T4A, is set and applies a negative potential to the base electrode of a transistor TSA the collector of which is connected to a terminal A14 which is connected through a line Z1 to a terminal T14 of the ticketissuing machine T1M1. The application of the negative potential to the base electrode of the transistor TSA makes this transistor conductive so that it draws current which operates a relay which is connected to the terminal T14 and releases the mechanism for the issue of a ticket.

The setting of the second bi-stable device T3A, T6A, in the unit A1 also removes one of the inputs from the AND gate D6A, DSA, in this unit. As a result the negative potential is removed from the base electrodes of the four transistors TSA, T9A, T10A and T11A, in this unit and they all cease to conduct.

When the transistor T8A in the unit A1 ceases to conduct, the transistor T11M in the unit L whose collector is connected to the terminal L6 recommences to conduct and thus removes the inhibition from the control counter G which accordingly recommences to cycle. In addition current will cease to flow through the line X1 to the terminal CW1 of the unit CW. Accordingly the bi-stable device T3B, T4B, in the unit CW will be unset and the transistor T6B whose emitter electrode is connected to the terminal CW3 will cease to conduct thus allowing the transistor TIM whose emitter is connected to the terminal L15 to pass current again. Further the AND gate TSB, T6B, in the unit CW will be closed.

When the negative potential is removed from the base electrode of the transistor T9A in the unit A1, current ceases to flow through the line Y1 to the input terminal C11 of the unit C1. Accordingly the bi-stable device T2C, T4C, in this unit is unset and the base potentials of the four transistors T6C, T7C, T8C, T9C, in this unit return to their normal values.

When the transistor T11A in the unit A1 ceases to conduct,: the transistor T4M in the unit L whose emitter 15 is connected to the terminal L3 will recommence to conduct.

When the transistor T10A in the unit A1 ceases to conduct, the transistor T7L in the unit L whose emitter is connected to the terminal L1 will recommence to conduct and accordingly the second input of the first AND gate D2L, D3L in this unit will be de-energised. Thus the negative potential is removed from the base electrode of the transistor T4L whose emitter is connected to the terminal L12 and accordingly current again flows through the transistor T1F whose emitter is connected to the terminal 1B2.

When the negative potential is removed from the third transistor T6C in the unit C1, the current previously drawn by this transistor returns to the transistor T61) whose emitter is connected to the terminal IE5 and the AND gate D6D, D7D in the unit 1B is closed. Similarly when the negative potential is removed from the fourth transistor T7C in the unit C1, the one energised input of the AND gate D6D, D7D in the unit 5B is de-energised. When the actuated keys in the ticket-issuing machine TIMI are released, the potential on the line C1 reverts to its normal value and as a result the first bistable device T1A, T2A in the unit A1 is unset. The emitters of the transistors TIA, T2A are connected to the base electrode of the transistor T3A through a resistor R7A so that unsetting of the first bi-stable device causes the second bi-stable device T3A, T4-A to be unset also.

Thus all the elements of the equipment are returned to their initial state and are ready to respond to the next call from a ticket-issuing machine.

As has previously been pointed out, if the calling ticket-issuing machine is TIM3, the equipment will operate to record five bets and the unit 5B will be operative in place of the unit 18. The unit 5B includes a 6-stage ring counter NIE N6E in place of the Z-stage counter N 1E, NEE but is otherwise identical with the unit 1B illustrated in FIGURE 8. As the counter NlE N6E steps from to 1 it sets a mono-stable device T3D, T4D which applies a positive pulse to a terminal 5136. The terminal B6 is connected to the terminals CW5 and CPS and each of these terminals is coupled through the OR gate D813, D913 to the base electrode of the transistor T10B and thus energises one input of the AND gate D7B, D10B. Thus the registration of the first bet from TIM3 proceeds in the same manner as described with reference to the registration of a bet from TIMI. However, the AND gate D1L, D4L in the unit L will be operative in place of the AND gate D2L, D3L since the terminal L2 will be energised whereas the terminal L13 will not be energised. The pulse from the terminal K9 Will energise the second input of the AND gate DlL, D4L and a negative potential will be applied from the output of this AND gate to the base electrode of a transistor T6L whose emitter is connected to a terminal L9. This terminal is connected to a terminal 5B2 in the unit 5B and thus to the emitter electrode of a transistor T17D whose collector is coupled to the input of the 6-stage ring counter. Thus the counter is stepped from 1 to 2 and a further pulse is applied to the terminal 5B6. This causes another bet to be registered and the registration of the bet causes the counter to step from 2 to 3. This process continues and a total of five bets are recorded as the counter steps up to 5. When the counter is stepped from 5 to 0, a negative potential is applied from the collector of a transistor T2E to the base electrode of a transistor TIE the emitter of which is connected to a terminal 5B3. It is to be noted that no pulse is applied to the terminal 5B6 when the counter steps from 5 to O and thus no bet is recorded at this stage. The terminal 5B3 is connected to the terminal L8 and the application of the negative potential to the transistor TIE takes current away from the transistor T10M whose emitter is connected to the terminal L8 and whose collector is con 15 nected to one input of the AND gate D7M, D3M. Since the 2-stage ring counter in the unit 113 has remained at 0 throughout the registration of the bets from TIME, the second input of the AND gate D7M, D8M is continuously energised, and a negative potential appears at the output of the AND gate when the collector of the transistor becomes more negative as current is taken away from it by the transistor TIE. The output of the AND gate is coupled to the transistor T4M whose emitter is connected to the terminal L3 as already described and the remaining sequence of events is the same as when the Z-Stage ring counter in the unit IB stepped from 1 to 0.

FIGURE 10 illustrates one form of control counter which may be used in the totalisator system as illustrated in FIGURE 3. The control counter illustrated includes a 6-stage ring counter NIH N6H. Each stage of the ring counter may include a cold-cathode gas-filled trigger tube and the drive may be of the pulse-plus-bias type as in the case of the counter NIE, N2E in the unit 1B. The cathode of each trigger tube is connected to the base of a respective transistor TlH to T6H and the collector of each of these transistors is connected to an output terminal G1 to G6. The cathode of the conducting trigger tube is more positive than the cathodes of the remaining trigger tubes and this positive potential is used to make the transistor associated with the conducting trigger tube non-conductive, whereas the transistors associated with the non-conductive trigger tubes are all themselves conductive. Thus the output terminal connected to the collector of the transistor associated with the conducting trigger tube is more negative than the remaining output terminals and is thus regarded as energised. As will be recalled, the output terminals G1 to G6 are connected to terminals A15 to A65 in the units A1 to A6 and the negative potentials appearing successively on the terminals G1 to G6 energise AND gates in the units A1 to A6 successively.

The ring counter NIH N6H is driven by means of a multivibrator circuit T46, TSG through a pulseforming circuit PFH and a pulse amplifier PAH. The multivibrator T4G, TSG is normally free-running but may be stopped by the application of a positive potential to the base electrode of the transistor T4G from the emitter of a further transistor T3G. The base electrode of the transistor T36 is connected to an OR gate DIG, DZG, D6G. The cathodes of the rectifiers DIG, D2G and D3G are connected to terminals G8, G9 and G10 and accordingly the multivibrator is stopped whenever a negative potential is applied to any of these three terminals. Further the cathode of the rectifier D6G is connected to the output of a mono-stable device TIG, T2G. In the unset state of this device the transistor D2G is conductive and accordingly it does not normally apply a negative potential to the rectifier D6G. However, the mono-stable device may be set by the application of a negative potential to the terminal G7 so that the transistor T1G conducts in place of the transistor T2G and the collector of the latter transistor becomes more negative.

It will be recalled that the terminal G7 is connected to the terminal L6 in the unit L and that this latter terminal is connected to the collector of a transistor T11M which is normally conductive, but which ceases to conduct when all the inputs of an AND gate D4A, DSA, D7A in an A unit have been energised. When the current is withdrawn from the transistor TIIM, its collector becomes more negative and hence the mono-stable device TlG, T2G is set and the multivibrator T4G, TSG is stopped. The mono-stable device TIG, T2G is included between the terminal G7 and the OR gate to ensure positive stopping of the control counter when the call contact has been closed in a ticket-issuing machine. In the absence of the mono-stable device TIG, T2G it would be possible for the terminal G7 to energise the OR gate just as the control counter was moving from the calling I ticlgebissuing machine if the pool and runner keys 1 7 happened to be operated at a particular time. The inclusion of the mono-stable device prevents the possibility of a fault occurring through such operation.

When a ticket has been issued it has already been stated that the transistor T11M recovers its current from the transistor TSA, and when this happens the mono-stable device TlG, TZG is unset and one of the negative inputs to the OR gate is removed. However, the control counter cannot recommence to cycle until negative potentials have also been removed from the terminals G8, G9 and G10.

The terminal G8 is connected to the terminal L7 in the unit L and this terminal is connected to the collector of the transistor T3M. It will be recalled that current was taken away from the transistor TSM by the transistor T9A after the bi-stable device T3B, T4B had been s.t. Thus the collector of the transistor T3M remains negative and thus prevents recommencement of the cycling of the control counter until the bi-stable device T3B, T43 in the unit CW (or in the unit CP in the case of a place bet) is unset. Thus an inhibition is placed on the control counter until the units CW and CP are ready to respond to a further bet.

The terminal G9 is connected to a terminal 184 in the unit 1B and the terminal IE4 is connected to the collector of the transistor T61). The emitter of the transistor T6D is connected to the terminal 1B5 and it will be recalled that this terminal is connected to the terminals C16, C26 and C36 so that the transistor T6D is rendered non-conductive when the bi-stable device T2C, T4C in any of the units C1, C2 or C3 is set. Thus a further inhibition remains efiective on the control counter until the bi-stable devices in all the units C1, C2 and C3 are unset and these units are ready to respond to a further bet.

The terminal G10 is connected to a terminal B4 in the unit 5B and provides a similar inhibition in the case of a multi-stake bet. This inhibition operates in the same manner as that described with reference to the terminal G9 when the ticket-issuing machine TIMBhas been in operation in place of the ticket-issuing machine TIMI or TIMZ. It will be seen from the above that the control counter G cannot restart until it is certain that there is no bi-stable device still set in any of the units CW, CP, C1, C2 or C3.

In addition to the apparatus already described a number of fault-indicating circuits will be provided in a practical equipment. These will not be described in detail since they are unnecessary to an understanding of the invention, but a brief summary of them will now be given.

If the control counter G is arrested for a longer period than is necessary for the registration of a bet, a monostable circuit is set and a fault indication is provided. For this purpose the control counter G includes six diodes D2H to D7H, the cathode of each of which is connected to a respective one of the terminals G1 to G6. The anodes of all these diodes are connected in common to the base electrode of a transistor T9H and this transistor will be conductive when any of the trigger tubes NIH to NGH is conductive. The emitter of this transistor is connected to a terminal G11 and this terminal is used to control the mono-stable circuit. So long as the transistor T9H is conductive a capacitor is charged and the mono-stable device is set as soon as the voltage across the capacitor reaches a predetermined level.

A further fault indication is provided When the call contact in any of the ticket-issuing machines has been closed for a period longer than necessary. This fault indication may be given by means of a thermal-delay switch which is energised when the call contacts are closed and which itself closes to energise a fault indicator after a delay of about eight seconds.

Each of the units A1, A2, A3, and so on, is provided with a number of lamps which are normally lit. One lamp is connected to the first bi-stable device TlA, T2A and this is extinguished when the bi-stable device is set by closure of the call contacts. The second lamp is connected to the second bistable device T3A, T4A and is extinguished when this bi-stable device is set. The third lamp in each unit is extinguished when that unit is rendered operative by the control counter G. Thus the third lamp will be extinguished throughout the period when the unit is operative. The first lamp will be extinguished while the call line C is negative and the second lamp will be extinguished only for the period between the time when the second bi-stable device TZA, T4A is set after the counters have increased their registration and the time when the second bi-stable device is unset by the upsetting of the first bi-stable device.

Each of the units CW, CP, C1, C2 and C3 is provided with a lamp which is extinguished While the bi-stable device T3B, T413 or TZC, T 4C in that unit is set.

The counter NlE, NZE in the unit 1B and the counter NIE NdE in unit 53 are provided with lamps which indicate the digit registered by each counter.

The unit K is provided with four lamps which are nor mally lit and each of which is extinguished when one of the memory circuits T4K, TSK; TeK, T9K; T41C', TSIC; or TSIC, T91C, is energised.

Referring again to FIGURE 2 it has already been stated that in practice there are a plurality of portions P7. Thus it can now be seen that the lines 1, 2 and 3 which run between the ticket-issuing machines and the units C1, C2 and C3 may be regarded as equivalent to three lines S6 and the units C1, C2 and C3 may be regarded as three portions P7.

The lines 1, 2 and 3 may run in a single cable and it is necessary that the cross-talk between lines be kept to a minimum. This has been achieved in the following ways:

The lines are held as near 0 volt as possible and terminated with about five ohms impedance by the transistor receivers in the CW, CP, C1, C2 and C3 units. The bases of these transistors are connected to 0 volt. The emitter of a conducting generator transistor in an A1, A2, .or A3 unit is held about 3 volts positive to allow for the voltage drop in the line.

The cross-talk due to electrostatically induced potential differences between lines has been practically eliminated by individually screening each line in the cable (S5 and S6 FIGURE 2). To avoid earth currents the screening is connected to the electronic 0 volt only.

It is well-known that the induced voltage is dependent on the rate of rise or fall of the current and accordingly in order to reduce the rate of change of the current through any of the lines a capacitor may be connected between the collector of the transmitter T5 and 0 volt.

The transistor receiver (T6 FIGURE 2) causes a bistable to switch and the coupling between the transistor receiver and the bi-stable has been designed so that at least three quarters of the metered current in the line must be received by the transistor receiver before it can set the bi-stable. Further the current must fall to one quarter of the metered current before the bi-stable is unset. Thus these circuits are designed to be insensitive to transient interference however it may be induced. This circuit otters a further advantage in that in the case of a short circuit between lines, insufiicient current would be received by the transistor receivers to switch the bi-stable units. An indicator lamp however could be lit to indicate the fault.

What we claim as our invention and desire to secure by Letters Patent of the United States is:

1. A totalisator system comprising a control station, a plurality of ticket-issuing machines each having a plurality of selector switches, means for rendering the ticket-issuing machines operative one at a time, a current transmitter in the control station, said transmitter being capable of delivering a predetermined maximum amount of electric current, a plurality of current receivers in the control station, the response current of each receiver being greater than one half of the said predetermined current, and a plurality of conductors in a multi-core cable for selectively connecting said current transmitter to said current receivers through said selector switches.

2. A totalisator system as claimed in claim 1, wherein the current transmitter and the current receivers are transistors.

3. A totalisator system comprising a control station, a plurality of ticket-issuing machines each having a plurality of selector switches, means for rendering the ticketissuing machines operative one at a time, a transmitter transistor in the control station, a plurality of receiver transistors in the control station, a plurality of conductors in a multi-core cable for connecting the collector of said transmitter transistor to the emitter of a selected one of said receiver transistors through an actuated one of said selector switches in the operative ticket-issuing machine, and means for maintaining the potential of the base electrodes of all said current receivers at a fixed potential substantially equal to the potential of any unconnected conductors in said multi-core cable.

4. A totalisator system as claimed in claim 3, wherein said multi-core cable includes a central earth conductor which determines said fixed potential, and wherein all the conductors, apart from the central earth conductor, in said multi-core cable are individually screened.

5. A totalisator system comprising a control station, a plurality of ticket-issuing machines each having a plurality of pool selector switches and a plurality of runner selector switches, and a plurality of conductors in a multicore cable extending between said control station and said ticket-issuing machines, said control station including sequencing means for rendering the ticket-issuing machines operative one at a time, a pool current transmitter transistor capable of delivering a first predetermined maximum current, a plurality of pool current receiver transistors, a plurality of pool bistable devices each controlled by a separate one of said pool current receiver transistors and adapted to be shifted from one state to another state when the pool current receiver transistor controlling that pool bistable device receives more than half of said first predetermined maximum current, means responsive to the actuation of a'pool selector switch and a runner selector switch in the ticket-issuing machine selected by said sequencing means for establishing a current path from the collector of the pool current transmitter transistor to the emitter of one of the pool current receiver transistors through conductors in said cable and through the actuated pool selector switch in said selected ticket-issuing machine, a runner current transmitter transistor capable of delivering a second predetermined maximum current, a plurality of runner current receiver transistors, a plurality of runner bistable devices each controlled by a separate one of said runner current receiver transistors and adapted to be shifted from one state to another when the runner current receiver transistor controlling that runner bistable device receives more than half of said second predetermined maximum current, means responsive to the setting of any one of said pool bistable devices for establishing a current path from the collector of said runner current transmitter transistor to the emitter of one of the runner current receiver transistors through conductors in said cable and through the actuated runner selector switch in the selected ticket-issuing machine, a pulse generator, a plurality of pool counters, a plurality of runner counters, and means responsive to the setting of any one of the runner bistable devices for causing the pulse generator to apply a pulse to the input of the one of said pool counters selected by the actuated pool selector switch and also to the input of the one of said runner counters selected by the actuated runner selector switch.

References Cited UNITED STATES PATENTS 2,627,039 1/1953 MacWilliams. 2,951,125 8/ 1960 Andrews. 2,987,250 6/1961 Faulkner 235-92 DARYL W. COOK, Acting Primary Examiner.

JOHN F. MILLER, Examiner.

G. I. MAIER, Assistant Examiner.

Claims

1. A TOTALISATOR SYSTEM COMPRISING A CONTROL STATION, A PLURALITY OF TICKET-ISSUING MACHINES EACH HAVING A PLURALITY OF SELECTOR SWITCHES, MEANS FOR RENDERING THE TICKET-ISSUING MACHINES OPERATIVE ONE AT A TIME, A CURRENT TRANSMITTER IN THE CONTROL STATION, SAID TRANSMITTER BEING CAPABLE OF DELIVERING A PREDETERMINED MAXIMUM AMOUNT OF ELECTRIC CURRENT, A PLURALITY OF CURRENT RECEIVERS IN THE CONTROL STATION, THE RESPONSE CURRENT OF SAID RECEIVER BEING GREATER THAN ONE HALF OF THE SAID PREDETERMINED CURRENT, AND A PLURALITY OF CONDUCTORS IN A MULTI-CORE CABLE FOR SELECTIVELY CONNECTING SAID CURRENT TRANSMITTER TO SAID CURRENT RECEIVERS THROUGH SAID SELECTOR SWITCHES.