US3284716A - Voltage comparison circuit - Google Patents

Description

Nov. 8, 1966 J. Ll CHOPIN VOLTAGE COMPARISON CIRCUIT Filed June 10. 1965 '7 Sheets-Sheet l Nov. 8, 1966 4.1.. cHoPlN 3,284,716

VOLTAGE COMPARISON CIRCUIT Filed June l0, 1963 7 Sheets-Sheet 2 FIG. 4

Nov. 8, 1966 J. L. cHoPlN 3,284,716?

VOLTAGE COMPARISON CIRCUIT Filed June 1o, 196s v sheets-sheet s +5vLe Lu L1 L2 L3 L4 L5 L5 L7 L5 Le L0 Nov. s, 1966 Filed June l0, 1963 J. L. CHOPIN VOLTAGE COMPARISON CIRCUIT 7 Sheets-Sheet 4 Nov. 8, 1966 Filed June l0, 1963 J. L. CHOPIN VOLTAGE COMPARISON CIRCUIT '7 Sheets-Sheet 5 sd, M r405 sd 2 A04 Sd20 g 408 FIG. 8

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NOV- 8, 1966 J. L. cHoPlN VOLTAGE COMPARISON 'CIRCUIT 'T Sheets-Sheet 6 Filed June lO, 1963 FIG.10

Filed VJune 1o 196s SheetsSheet 7 FIG."

United States Patent O 3,284,716 VOLTAGE COMPARISON CIRCUIT Jacques Louis Chopin, Saint-Mande, France, assigner to Compagnie des Machines Bull (Socit Anonyme), Paris, France Filed June 10, 1963, Ser. No. 286,789 Claims priority, application France, .lune 19, 1962,

1 claim. (l. 328-146) The present invention relates to devices employed in character recognition systems according to the U.S. patent application of Morton Nadler, led on May 31, 1962, under Serial No. 198,843, now Patent 3,202,965.

More precisely, the present invention concerns electric circuits for exploiting, in accordance with the principles set forth in the specification of aforesaid Patent 3,202,965 the signals generated by the scanning device of the character recognition system according to the aforesaid patent specification.

The various objects, features and advantages of the electric circuits according to the present invention will become apparent from the following description and from the accompanying diagramamtic drawings, in which:

FIGURE 1 illustrates a type of circuit employed in accordance with the present invention in a character recognition system of the type described in the aforesaid patent specilication,

FIGURE 2 illustrates a circuit of the type indicated in FIGURE 1, adapted to the use of lan analogue inverter,

.FIGURE 3 illustrates an integrating circuit according to the present invention,

FIGURE 3a illustrates an integrating circuit identical to that of FIGURE 3 and provided with a return-tozero device,

FIGURE 3b illustrates an integrating circuit identical to that of FIGURE 3 and adapted to effect the integration only of voltages of a given polarity,

FIGURE 3c illustrates a two-input integrating device according to the present invention which effects the integration of voltages of Ia given polarity which are applied to one of its inputs and the integration of voltages of opposite polarity which are applied to the other one of its inputs,

FIGURE 4 illustrates a device according to the invention which is capable of effecting the integration of voltages of a given polarity in response to predetermined control signals,

FIGURE 5 shows the curves of the control and output signals of the circuit of FIGURE 4,

FIGURE 6 illustrates a detecting circuit according to the present invention,

FIGURE 7 illustrates a comparing circuit according to the present invention,

FIGURE 8 illustrates a comparing device utilising a number of comparing circuits identical to that of FIG- URE 7 so as to determine the largest of a number of voltages,

FIGURE 9 illustrates a threshold device utilising a comparing circuit identical to that of FIGURE 7, and

FIGURES l() 4and 11 illustrate two different constructional forms of an integrating circuit of the type illustrated in FIGURE 3a.

FIGURE 1 is a diagram illustrating the principle of a circuit employed in accordance with the present invention in a character recognition system of the type described in the aforesaid patent specification. Such a circuit comprises essentially an ampliiier A10 of high negative gain -and having an input circuit of very high impedance, circuit elements W11, W12, Win, each connecting the input E1 of the amplifier A10 to a differice ent input B11, B12 Bln of the circuit, and a circuit element W20 connecting the output S1 of this amplier to its input E1. The output B20 of the circuit is directly connected to the output of the amplifier A10.

The eiect of the negative feedback `applied to the amplifier A10 by the circuit element W20 is to maintain the input E1 of this amplifier at a substantially lixed potential when variable voltages are applied to the inputs B11, B12, Bln of the circuit. By reason of the very high impedance of the input circuit of the amplifier A10, the current flowing through the circuit element W20 is substantially equal at each instant to the algebraic sum of the currents flowing through the circuit elements W11, W12, Wln.

The following description shows how it is possi-ble to adapt a circuit of the aforesaid type to various uses for the purpose of providing certain devices of a character recognition system according to the parent specification.

FIGURE 2 illustrates an inverting circuit formed of a circuit of the type under consideration which comprises only lone input, Le., B11, and in which the circuit elements disposed at the input `and in the feedback loop of the amplifier are resistance-s R1 and R2 respectively, of like value. The voltage s set up at the output B20y of the circuit is then substantially equal, but of opposite p direction, to the voltage e applied to the input:

FIGURE 3 illustrates an integrating circuit formed of a circuit of the type under consideration which comprises only one input, i.e., B11, and in which the circuit element disposed at the input is a non-inductive resistance, i.e., R, and the element of this circuit connecting the output of the amplifier to its input is a condenser C. The voltage s set up at the output B20 lof the circuit is then connected to the voltage e applied to the input by the equation:

e s-o fR-dt e0 ybeing a constant which depends upon the initial conditions.

If the condenser C of this circuit is shunted by a switch T, -as shown in FIGURE 3a, and if this switch, controlled by a signal lapplied to 0, is closed until the instant t0, the output voltage s of the circuit is zero until the instant lo. lts value at a succeeding instant t is then:

t e toRCdt If the circuit element disposed at the input of the integrating circuit compri-ses fa diode D, as shown in FIGURE 3b, the current can oW only in a predetermined direction between the input and the output of the circuit. Consequently, the latter integrates Ionly the voltages of given polarity which are applied to its: input B11, when the voltage at the input E1 of the amplifier A10 is maintained at zero value by the negative feedback eifect.

FIGURE 3c illustrates an integrating circuit formed of a circuit of the type under consideration comprising two inputs i.e., B11 and B12, and in which the circuit elements disposed at these inputs are each formed of a resistance in series with a diode i.e., R11 :and D11 on the one hand, and R12 and D12 on the other hand, so that the circuit integrates only the voltages of given polarity which Iare applied to its input B11 and the voltages of opposite polarity which are applied to its input B12, the circuit Ibeing identical in other respects to that illustrated in FIGURE 3b.

FIGURE 4 illustrates a device according to the invention which is capable of effecting the integration of voltages of given polarity in response to predetermined control voltages, so as to perform the functions of a distributing circuit and of an integrating circuit of the so-called elementary analysis device illustrated in FIG- URE 6 of the aforesaid patent specification.

The device illustrated in FIGURE 4 comprises a positive AND circuit `621 and a negative AND circuit 622, as also an integrating circuit 67 identical with the circuit illustrated in FIGURE 3c. The outputs of the AND circuits 621 and 622 are connected respectively to the inputs B11 and B12 of the integrating circuit 67.

The device illustrated in FIGURE 4 performs the functions of the distributing circuit 62 and of the integrating circuit 67 of the elementary analysis device 12 illustrated in FIGURE 6 yof lche aforesaid patent specication when there are applied to the inputs of the circuit 621 and to the inputs of the circuit 622, respectively, the

voltages V+ and S, on the one hand, and S and V on the other hand, Irepresented by the diagrams of FIGURE 5.

In this gure, the voltages plotted along the abscissae are traced with reference to the same instants t1, t2, te, to as those 'used in FIGURE 7a of the aforesaid patent specication, and the voltages plotted along the ordinates are traced with reference to the potentials -V, 0V and +5V. The voltages V+ .and V are control signals dened in the aforesaid patent specication, and the voltages S and S are the scan signals supplied by the scanning device 10 of the system described in the aforesaid patent specification.

The circuit 621 transmits tc the input B11 of the integrating circuit 67 of a voltage (B11, FIGURE 5) which is equal at each instant to the lower of the voltages S and V+. The circuit 622 transmits to the input B12 of the integrating circuit 67 a voltage (B12, FIGURE 5) which is eqal at each instant to the higher of the voltages S and V. The integrating circuit 67 integrates only the positive voltages applied to its input B11 and the negative voltages applied to its input B12.

If the voltages S and S take the values represented by FIGURE 5, la positive voltage is applied to the input B11 between the instants f1 and t4, whereafter a negative voltage is applied to the input B12 between the instants t5 and t8. In addition, a pulse O controls the closing of the switch T between the instants to and t1.

If x is the value as a function of time of the voltage S applied to one of the inputs of the AND circuit 621, the value as a function of time of the voltage S applied to one of the inputs of the AND circuit 622 is equal to x. The volta-ge sv set up at the instant Z8 at the output B of the integrating circuit `67 is then:

t4 xdt ts mit n TCH-fn t0 r l'being the value of the resistances which are in series with the condenser C lboth during the integration of the positive voltage applied to B11, i.e.`, between the instants t1 and t4, and during the integration of the negative voltage applied to B12, i.e., between the instants t5 and f8.

The resistances R11 and R12 of the integrating circuit 67 just described have in principal the same value. 'Ilhey may nevertheless be -given different values in order to effect the adjustments or compensations rendered necessary Iby the design and conditions of use of the said integrating circuit.

It has been considered desirable, in a preferred form of construction of the character recognition system according to the invention, to adjust the operation of the scanning device in such manner that the extreme values of the voltage S (corresponding to perfect black and white) are respectively -1 volt and '+6 volts. This has the result that lshe integrator integrates the voltage 0 volt if the voltage S is between -1 volt and 0 volt, integrates the voltage S if the latter is between 0` volt and +5 volts, and integrates the voltage +5 volts if the voltage S is between +5 volts and +6 volts. Thus, the signals corresponding to pure shades are standardized: and black are interpreted in the same way, as also are 0% and 5% bl-ack. On the lother hand, the signals corresponding to intermediate shades are used as true values in the integrator and the logical decision is taken only at the output of the integrator.

FIGURE 6 illustrates a circuit of the type under consideration which is designed to operate as a detecting circuit. This circuit comprises a number of inputs B11, B12, B111. The circuit elements disposed at these inputs are non-inductive resistances, i.e. R11, R12, R111, while the circuit element connecting the output of the amplifier A10 to its input is a Zener diode DZ. When voltages e1, e2, en are applied to the inputs B11, B12, Bln respectively, the diode DZ is traversed by a current whose direction depends upon the sign of the `algebraic sum of the currents across the resistances R11, R12, R1n. Depending upon the direction of the current across the diode DZ, the potential difference across the terminals of the latter is zero or equal to its critical inverse voltage, which will be denoted by dz. The volta-ge supplied at the output B20 of the detecting circuit when the diode is connected in the manner indicated in the figure therefore takes either one of two characteristic values 0 and -dz, depending upon the sign of the sum:

FIGURE 7 shows how a detecting circuit of the type described in the foregoing can be employed to operate as a comparing circuit. This circuit then comprises only two inputs B11 and B12 and the resistances R11 and R12 disposed at these inputs are equal. This circuit is capable of indicating the direction of an inequality set up between two voltages el and e2 applied to its inputs. It is suicient to apply one of the voltages, i.e. el, to one of the inputs, and to apply to the other input a Voltage which is equal and of opposite sign to the other voltage, i.e. -e2. The output voltage s of the circuit then takes either one of the two characteristic Values 0 and -dz, depending upon whether the algebraic sum e1-e2 is negative or positive.

FIGURE 8 illustrates a comparing device according to the invention which is capable of comparing a number of voltages simultaneously applied to its inputs, so as to determine which of them `is the yhighest in absolute value and, where necessary, which of them are higher in absolute value than a predetermined fraction of the highest, the direction of the voltages applied not being predetermined.

Such a comparing device may be employed in the de- -vice for the recognition of shape elements of a character recognition system according to the aforesaid patent specification, in order to determine which of the voltages supplied by the integrating circuits of the elemental analysis device is highest.

This comparing device comprises a mixing circuit 400 comprising diodes and resistances which is capable of supplying at its output 420 an elemental voltage SM which is equal to a predetermined fraction (for example eym) of the lowest one of the voltages applied to its inputs, the output of this mixing circuit being connected to the cornmon point of two resistances 1R and 9R in series which apply the bias potential to the `diodes of the circuit. This circuit comprises a number of inputs equal to twice the number of voltages which are to be compared.

The comparing device comprises in addition a number of comparing circuits equal to twice the number of volta-ges to be compared. Each of these comparing circuits (denoted in FIGURE 8 by the reference numerals 401, 402, 408) is identical to that which is illustrated in FIGURE 7. The output 420 of the mixing circuit 400 is connected to one of the inputs of each of these comparing circuits. The voltages to be compared, sh, sv, sdl, SdZ, and the voltages of opposite direction -sh, -sv, -sd1, -sd2, are applied to the inputs of the mixing circuit `400, as also to those inputs of the comparing circuits 401, `402, 408 which are not connected to the output of lthe mixing circuit 400.

If, for example, sv is the highest of the voltages to lbe compared, the voltage set up at the output of the mixing circuit 400 is equal to -%0sv and the output voltage of the comparing circuit 402 is equal to the characteristic voltage -dz, because the sum sv-9/10sv is positive.

If the other voltages to be compared (sh, sat1, sd2) are lower in a'bsolute value than the predetermined fraction 9/10 of the highest voltage sv, the output voltages of the other comparing circuits are zero, because the sum of the voltages applied to the inputs of each of these other comparing circuits is then negative.

The information supplied by the occurrence of the voltage dz at the output of a single one of the comparing circuits can be utilised by the shape element recognising device of a system to the aforesaid paten-t speciiication.

If, however, one (or more) of the other voltages to 4be compared (sh, sdl, .rd2) is/ are higher than this predetermined fraction (9/10) of the highest voltage (sv), the output voltage of Ithe corresponding comparator or comparators is equal to the voltage -dz.

The simultaneous occurrence of the voltage dz at the output of a number of comparing circuits signifies that each of the voltages to -be compared which are applied to one of the inputs of these comparing circuits is higher than the said predetermined fraction of the highest of them. This information may also be utilized under certain conditions in a system according to the aforesaid patent specification.

In accordance with the principle pf the invention forming the subject of the aforesaid patent specification, the voltage set up at the output of each of the integrating circuits of the elemental analyzing device expresses the ccntrast of shades existing between two predetermined symmetrical portions of the elemental gure scanned during a `minor cycle. If the shade of the elemental figure scanned in the course of a yminor cycle is uniform, the elemental voltages set up at the output of the various integrating circuits are in principle equal to the lowest voltage which can be supplied by `each integrating circuit. In practice, the voltages set up in this case at the output of the integrating circuits are never equal -to one another, and at least one of them lis suiciently high in relation to the others for the characteristic voltage -dz to be set up at the output of at least one of the comparing circuits 401, 402, 408. This is also true if there exists `between two symmetrical portions of the elemental figure scanned a slight contrast having no significance in regard to the presence of an edge of a stroke in the figure scanned.

A characteristic voltage -dz supplied under these conditions by one of the comparing circuits must not be interpreted as an indication of the direction of the edge of a stroke scanned in the course of a minor cycle, as long as the Value yof the contrast existing between symmetrical portions of the elemental figure scanned in the course of a minor cycle is below a certain threshold value, i.e. `as long as this contrast is too slight to warrant the assumption that there exists an edge of a stroke in the elemental ligure scanned in the course of this minor cycle.

In accordance with a feature of the invention, a characteristic voltage -rdz which is set up at the output of one of the comparing circuits 401 to 408 and which indicates that the voltage applied to the input of this comparing circuit is higher than voltages applied to certain other ones of these comparing circuits, is transmitted to the shape element recognition circuits only if this voltage applied to the input of this comparing circuit is alsov higher than a predetermined lixed threshold voltage SF.

FIGURE 9 is a diagram illustrating the principle of a threshold device designed in accordance with the invention to transmit to `the shape element recognition circuits of a system according to the aforesaid patent specitication a voltage dz which might be supplied by one of the comparing circuits (Le. 402, for example) of the comparing device illustrated in FIGURE 8 only under the above-indicated conditions.

This threshold device comprises a comparing circuit 502 identical to the comparing cincuit illustrated in FIG- URE 7, and a logical NOR circuit 602 having three inputs.

There is applied to one of the inputs of the comparing circuit 502 the same voltage .sv as is applied to one of the inputs of the comparing circuit 402, and there is applied to the other input of the comparing circuit 502 a voltage equal and of opposite direction to the iixed threshold voltage SF. The output 522 of this comparing circuit is connected to one of the inputs of the NOR circuit 602. The output 422 of the comparing circuit 402 is connected to another input of this NOR circuit and a sampling voltage E (FIGURE 5) complementary to the voltage E defined in the aforesaid patent specification is applied to the third input of this NOR circuit.

A voltage dz supplied by the comparing circuit 402 gives rise to the occurrence of a positive pulse at the output 622 of the NOR circuit 602 on application of a sampling pulse E only if the comparing circuit 502 simultaneously supplies a voltage -dz which expresses the fact that the voltage sv, representing the contrast between tWo predetermined portions of the elemental ligure scanned, is higher than the iixed threshold voltage SF.

It is to be understood that the invention is not limited to particular constructional forms of the various circuits whose operating principle has been described in the foregoing. In order to facilitate the application of the invention, there have been shown by way of non-limiting example in FIGURES l0 and ll two constructional forms of an integrating circuit of the type described with reference to FIGURE 3a.

In a true construction according to FIGURE 10, the circuit elements are defined as follows:

T1 transistor type OC 44 T2 transistor type OC 80 DZO Zener diode whose critical inverse voltage is l0 volts r1 resistance of 1.2 kilohms r2 resistance of 2.2 kilohms.

I Claim:

A voltage discriminating device for simultaneously comparing a number of input signals, each signal being applied to said device in the form of two voltages having the `same absolute value and opposite polarities, said discriminating device comp-rising a series of input terminals, said series comprising a number of terminals at least equal to twice the number of signals to be compared, each of said signals being applied in its negative polarity to one of said terminals and in its positive polarity to another of said terminals, said discriminating device further comprising a number of diodes equal to the nurnber of said terminals, a voltage divider circuit consisting of a first resistor and la second resistor connected in series at one of their extremities, the other extremity of said first resistor being connected to a point of zero voltage and the other extremity of said second resistor being connected to each of said terminals via a different one of said diodes, said diodes being poled to conduct an electrical current from said point of zero voltage to said terminals, said discriminating device further comprising a number of detecting -circuits equal to the number of said terminals, each detecting circuit comprising two input means, one output rmeans, two resistors of identical values, an amplier with an input circuit of very high impedance and having an output connected to said output means and an input connected to each of said input means via a different one of said two resistors, and an unidirectional circuit element connected between said amplifier output and said amplifier input to carry an electrical current from said amplilier input to said amplifier output, no potential diIe-rence o1' a constant potential dilerence `existing at the terminals of said unidirectional circuit element according to the direction of said electrical current it carries, each detecting circuit being connected by means of one of its two input means to a respective one of said terminals, and by means of the other input means to the common point of the two series-resistors `of said voltage divider circuit, whereby the detecting circuit connected to a respective one of said 8 terminals to which is applied a positive voltage which is higher than a predetenmined fraction of the highest in absolute value, supplies a discriminating signal.

References Cited by the Examiner UNITED STATES PATENTS 2,632,845 3/1953 `Goldberg 328-94 2,775,694 12/1956 Blumlein 328--128 3,076,901 2/1963 Rubin 307-88-5 3,094,675 6/1963 Ule 307-885 DAVID I. GALVIN, Primary Examiner.

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