US3281810A - Pulse monitoring circuit - Google Patents

Description

Oct. 25, 1966 D. s. THORNBERG ETAL 3,281,810

PULSE MONITORING CIRCUIT Filed Oct. 7, 1965 United States Patent 3,281,810 PULSE MNHTORNG CIRCUIT Dean S. Thornberg and Richard M. Jepperson, Salt Lake City, Utah, assignors to Montek Division of Model Engineering and Manufacturing Corporation, Salt Lake City, Utah, a corporation of Indiana Filed Oct. 7, 1963, Ser. No. 314,257 8 Claims. (Cl. 340-213) The present invention relates to an improved delay and maintenance memory light circuit provding an indication of alarm and has more particular reference to circuitry useful in holding an alarm means in a delay condition without indication of the alarm and to signal the alarm in the absence of operation of the equipment being monitored or tested.

In many types of electronic equipment it is desirableto provide an alarm to indicate .that certain electronic components are defective or inoperative, and that the alarm is preserved by Ia memory lmeans so that the electronic equipment may be continuously monitored by the alarm means, and the alarm means may be periodically inspected to determine whether the electronic equipment is properly functioning. The present invention seeks to provide a delay and memory means so that there is provided an accurate and complete indication rof the continuous op eration of electronic equipment regardless of whether the equipment being monitored is continuously putting out or generating wide or narrow pulses in a recurring fashion. The delay and memory means of the invention is particularly adapted to providing an alarm in the absence of pulses within a given alarm delay time, which delay time may be defined as that period of time between loss of an input pulse and extinquishment of the normally illuminative memory lamp. The memory and alarm may be a lamp and a trigger functioning as a memory device to actuate the lamp, which may be known as an alarm memory lamp, and is manually set to its initially OFF condition, and the manual reset means may provide a pulse to the signal receiving means of the alarm delay and the maintenance memory light circuit so that the circuit as well as the lamp is conditioned for again determining whether certain apparatus is producing recurring pulses at a repetitive rate within the predetermined delay time that is characteristic of the circuit. In accordance with the present invention, the delay time may be any reasonable length of time for such periods as one second, or one minute, but more particularly the circuit is adapted to provide an alarm upon the absence of recurring pulses during Ztl-second periods or even within shorter periods, such as -one-fourth of a second.

The invention also seeks to provide a novel circuit of the type described so that regardless of the alarm inhibiting input pulse width, a timing means is reset to an initial or predetermined and precise level even when the alarm inhibiting input pulse is of such narrow values that would ordinarily allow the timing means to continue a cycle that has already been started in providing the delay of the energization of the alarm memory lamp, but is momentarily stopped or is backed up only for the interval of the period of time of the short" or narrow input pulse. `By the arrangement of the invention there is provided a result of completely resetting the timing means of the alarm so that the delay is re-initiated before which the lamp would ordinarily be programmed for energization of an alarm inhibiting input pulse of wider width.

It is therefore an object of the invention to provide a circuit for holding in memory an indication of the monitored parameters, regardless of whether narrow or wide pulses are provided to the alarm and memory means 3,281,810 Patented Oct. 25, 1966 ICC of `the invention, and thus provide considerable increase in maintenance and efficiency of determining the operability of electronic equipment, as well as providing irnproved equipment reliability of alarm systems.

`One of the important applications of the new alarm delay and memory circuit means is that it uses conventional components in a unique circuit which provides for successful testing and using of the invention in a wide variety of uses and environments including military uses, and under severe conditions from at least 54 C. to C., and other general types of adverse conditions.

These as well as further advantages which are inherent in the invention will become apparent from the following description, reference being had to the accompanying drawing wherein:

The ligure is a schematic circuit diagram of an alarm and maintenance memory light circuit in accordance with a preferred embodiment of the present invention.

Referring now to the figure, there is illustrated an alarm time delay circuit 10, including components all of which may be mounted on a single printed circuit board, and having a terminal 12 to which signals are received for applying the recurring signals to be monitored or examined by the alarm and memory means. Other terminals such as terminals 14, 16, 18, 20 are used to apply appropriate collective voltages to the transistors 22, 24, 26, of the time delay circuit 10. Other terminals may be conviently applied for completing circuits to be described hereinbelow without reference to sepcilic designation of the terminals of the printed circuit board.

A timing means or capacitor network includes one of the resistances 30, 32 and the capacitor 34, so that the capacitor 34 is slowly and substantially linearly charged through either of resistances 30, 32 depending upon the position of the single-pole double-throw switch 36. The switch 36 provides that a normal or short, respectively, period of delay is provided :between the interval of pulses contemplated to be the desired lapsed time within which the pulses should accordingly re-occur. The circuit is disposed for receiving signals of positive polarity at terminal 12 to inhibit the actuation of the alarm, -and :are thus inhibiting pluses which 'are coupled through the capacitor 38V to the base of transistor 24 of a holding circuit 40. The -transistor 24 is normally cut off until the inhibiting pulse is received from terminal 12. In the event that `the inhibiting pulses desired to be applied to the alarm circuit are negative, there may be applied conventional inverter arrangements to translate the pulse to positive polarity, as is well known. While the inhibiting pulse is applied to tihe base of transistor 24, the transistor 24 is thus driven into saturation, and any charge that is residual in capacitor 34 accordingly is discharged through transistor 24 and resistor 42. The capacitor Is completely discharged to a predetermined level where the inhibiting pulse applied to vterminal 12 is longer than the discharge time of the capacitor 34 through the resistor 42. The capacitor is then, in the absence of further pulses applied from terminal 12 to the transistor 2-4, allowed to restart the delay cycle. As long as there is at least one or more input inhibiting pulses applied to terminal 12 to momentarily saturate the transistor 24 within the selected alarm delay period determined by the position of the switch 36, the charge voltage of the capacitor 34 will not be allowed to rise to the firing point of the transistor 26, which in .the preferred embodiment is a normally cutoff unijun-c-tion transistor such as type 2N492. If the unijunction transistor 26 is precluded from ring, there will be no positive pulse developed across its base to resistor 44, and a normally nonconducting or normally cutoff silicon controlled rectifier 46 comprising a trigger 48 will not be a energized to saturation. From the output side of the trigger 48, there is a conductor Sli connected to an alarm memory lamp S2 which is normally illuminated and will not be extinguished until the silicon controlled rectifier 46 is triggered from the unijunction transistor 26. When the silicon controlled rectifier is triggered there is a negative alarmy pulse `developed acr-oss the SCR load resistor 56 to extinguish the lamp. The conductor 50 may provide a signal for other uses as is shown as being a connection to an OR `gate (not shown).

The capacitor 34 is charged in the absence of inhibitling pulses applied to terminal *12, but the capacitor 34 is discharged to a predetermined and precise level where the inhibiting pulses are significantly wide in terms of time to exceed the discharge time of the condenser through resistance 42 when the transistor 24 is saturated. However, when an irrhibit input pulse is applied to terminal 12 which is significantly narrow in time which does not allow the capacitor 34 to discharge to said predetermined level, the capacitor 34 starts to discharge during the application of the short inhibiting pulse, and in so doing there is produced a `positive voltage across the resistance 42, which resistance is the emitter resistor of transistors 22 and 24. This positive voltage is fed to the emitter of transistor 22 which is a normally conducting transistor. This transistor may be of a type such as 2N7016. The positive pulse applied to the emitter thus cuts off t-ransistor 22. The resulting positive voltage developed at .the collector of transistor 22 is coupled to the base of transistor 24 and holds transistor 24 in saturation. Thus transistor 24 is maintained in saturation long after the narrow input pulse has terminated and until the value of the charge of capacitor 34 has discharged to a point where the voltage developed across resistor 42 is insufficient to hold the transistor 22 in cut-off condition. The transistor 24 may be a type 2Nl893.

The absence of inhibiting pulses to the alarm delay circuit indicates a condition of malfunction in the parameters of the circuit being monitored. If no inhibiting input pulses are applied to terminal 12, there is no positive pulse applied to the base of transistor 24 from terminal l2, and the voltage across the timing means or the`capacitor network including capacitor 34 will within the expiration of the delay period rise to a value that exceeds the firing point or the saturation point of transistor 25. If transistor 26 is allowed to conduct or fire, a positive pulse is developed across resistance which is applied to trigger 48 to cause the SCR 46 to saturate, and effectively by-pass the lamp illuminating current that would be supplied through resistance 56 through the normally closed contacts of the manual reset button 66. `In this manner, the alarm memory lamp S2 is extinguished after the expiration `of the delay time, which may be in the order of magnitude of 2O seconds, or even 1A second, depending upon the desired setting of switch 36 and upon the `time that is required for condenser 34 to reach the value to render the SCR 46 conductive after the condenser 34- commences the charge cycle from the pre-set level. Once the SCR 46 has been driven into saturation, it will remain in the saturation condition until the manual re-set button 66 is, depressed even though or in spite of the voltage across resistance 44 being returned to a substantially zero value. It is contemplated that an alarm and memory circuit of the type of the present invention may be used with each circuit sought to be monitored in which there are cyclic or recurring pulses. Where there are a plurality of circuits monitoring various points of an electronic system, the SCRs 46 of the respective circuits will hold in memory the indication of which of the several monitored parameters have initiated the alarm, and thus by discerning which of the lamps `of the plurality of alarms has been extinguished, there is determined where the failure or malfunction is present. This feature thus results in a considerable increase in the maintenance ef- Cil "J ciency of the electronic equipment, and the equipment reliablilty of such electronic systems is seen to be substantially increased.

When the unijunction transistor 26 is saturated or fired and produces the alarm pulse for triggering the trigger 4S, it also concurrently discharges the capacitor 34. In the absence of alarm inhibiting pulses being applied to the delay circuit input terminal l2, the recurring charge and discharge of capacitor 34 becomes cyclic for the predetermined delay period and the trigger 43 receives from the unijunction transistor 26 a series of positive alarm pulses occurring and reoccurring at the end of each delay period.

Upon depressing the manual reset button 66, there is a positive voltage applied through the manual reset button to the base of transistor 24 for resetting the charge of the capacitor 34 to said predetermined level, and thus commence or initiate the period of the alarm delay, as well as resetting the alarm memory lamp to its illuminated condition. Where there is a plurality of memory lamps used as indicators, as described generally above, the memory lamps may be a press-to-test type and may utilize miniaturized flanged 4base type lamps, such as those having ratings of over 5,00() hours. The resistance values of resistances 30, 32 are chosen so that taken together with capacitor 34 provide for a delay time of 20 seconds for a normal delay period and a 1A second delay for short delay periods. The short delay is found to be useful in providing alignment and testing capabilities to the system.

It should be understood that the specific electrical system herein schematically illustrated and described in detail is intended to be representative only, as there are many changes which may be made without departing from the clear teachings of the invention. Accordingly, reference should be made to the following claims in determing the full scope of the invention.

What is claimed is:

ll. An alarm delay and memory circuit comprising a capacitor, alarm delay means for applying an alarm delay signal to charge said capacitor, signal receiving means for receiving recurring signals, means for discharging said capacitor while the recurring signals are received from the receiving means, means responsive to a substantial charge of said capacitor to produce a pulse, trigger means responsive to said pulse to produce a gate signal representative of an alarm condition, and a holding circuit responsive to said recurring signals for maintaining the capacitor in its discharging state when substantially narrow recurring signals are received by the signal receiving means until the charge of said capacitor is reduced to a minimum value.

2. An alarm delay and memory circuit comprising a capacitor network, alarm delay means for applying an alarm delay signal to said capacitor network, signal receiving means for receiving recurring signals, means for substantially linearly charging said capacitor network in the absence of said recurring signals and for discharging said capacitor network while the recurring signals are received, means responsive to a substantial charge of said capacitor network to produce a pulse, trigger means responsive to said pulse to produce a gate signal representative of an alarm condition to an alarm means, and a holding circuit responsive to said recurring signals for maintaining the capacitor network in its discharging state when substantially narrow recurring signals are received by the signal receiving means.

3. An alarm delay and memory circuit comprising a capacitor network, signal receiving means for receiving and applying recurring signals to said capacitor network, means for substantially linearly charging said capacitor network in the absence of said recurring signals and for discharging said capacitor network while the recurring signals are received, means responsive to a substantial charge of said capacitor network to produce a pulse,

and trigger means responsive to said pulse `to produce a gate signal representative of an alarm condition to an alarm means.

4. The alarm delay and memory circuit of claim 3 wherein the trigger means is a silicon controlled rectifier.

5. An alarm delay and memory circuit comprising a capacitor network, alarm delay means for applying an alarm delay signal to said capacitornetwork, signal receiving means for receiving recurring signals, means for charging said capacitor network in the absence of said receiving signals until the capacitor network is charged and for discharging said capacitor network while the recurring signals are received, means responsive to a predetermined charge of said capacitor network to produce a pulse, trigger means responsive to said pulse to produce a gate signal representative of an alarm condition, and a holding circuit responsive to said recurring signals for maintaining the capacitor network in its discharging state when substantially narrow recurring pulses are received by the signal receiving means until the capacitor network is substantially discharged near the end of said delay period.

6. The alarm delay and memory circuit of claim 5, wherein the trigger may be reset by a manual push button.

7. The alarm delay and memory circuit of claim 5, wherein said trigger means producing the pulse representative of the alarm condition includes a unijunction transistor.

8. The alarm delay and memory circuit of claim 7, wherein are means to regeneratively maintain said alarm condition by the capacitor network producing a series of positive alarm pulses occurring at a repetition rate of the order of magnitude of the time constant of said capacitor network.

References Cited by the Examiner UNlTED STATES PATENTS 3,111,591 11/1963 Conron et al. 3,131,545 5/1964 Gross et al. 3,162,772 l2/1964 Smith. 3,192,462 6/1965 James.

NEIL C. READ, Primary Examiner.

R. M. ANGUS, Assistant Examiner.

Claims (1)

1. 2. AN ALARM DELAY AND MEMORY CIRCUIT COMPRISING A CAPACITOR NETWORK, ALARM DELAY MEANS FOR APPLYING AN ALARM DELAY SIGNAL TO SAID CAPACITOR NETWORK, SIGNAL RECEIVING MEANS FOR RECEIVING RECURRING SIGNALS, MEANS FOR SUBSTANTIALLY LINEARLY CHARGING SAID CAPACITOR NETWORK IN THE ABSENCE OF SAID RECURRING SIGNALS AND FOR DISCHARGING SAID CAPACITOR NETWORK WHILE THE RECURRING SIGNALS ARE RECEIVED, MEANS RESPONSIVE TO A SUBSTANTIAL CHARGE OF SAID CAPACITOR NETWORK TO PRODUCE A PULSE, TRIGGER MEANS RESPONSIVE TO SAID PULSE TO PRODUCE A GATE SIGNAL REPRESENTATIVE OF AN ALARM CONDITION TO AN ALARM MEANS, AND A HOLDING CIRCUIT RESPONSIVE TO SAID RECURRING SIGNALS FOR MAINTAINING THE CAPACITOR NETWORK IN ITS DISCHARGING STATE WHEN SUBSTANTIALLY NARROW RECURRING SIGNALS ARE RECEIVED BY THE SIGNAL RECEIVING MEANS.

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