US3278734A

US3278734A - Coded decimal adder

Info

Publication number: US3278734A
Application number: US136710A
Authority: US
Inventors: Ulbrich Egbert; Martin Johannes
Original assignee: Telefunken Patentverwertungs GmbH
Current assignee: Telefunken Patentverwertungs GmbH
Priority date: 1961-09-05
Filing date: 1961-09-05
Publication date: 1966-10-11
Anticipated expiration: 1983-10-11

Description

Oct. 11, 1966 E. ULBRICH ETAL 3,278,734

CODED DECIMAL ADDER @(Sign (0) Sign (b) yes no Sign (u,b) poshive c) d k) Set K=L. Invert a and b Set K=O Form o+b=Z e) U Form u+b +c =2 Sign (2 )posifive.

yes

Invert Z' 1' Z" Set K=L. no

9) Add OLLD in all T- ofZ" =Z" h) In) Add 01.1.0 in all T of)I'. =E

yes no I) lnveriZ'" E =E LEGENDS T5 irunsfer flea ieiruds Slgn (u, b)posiiiv T transfer affected tetruds T tetruds with double transfer C) F -E {:Z' c 666...(0LLO in each te'lrod) 999... (LOOL in each tetrod) final result Fig. la

mvem'roa Egbert Ulbrich Karl voitel 8 10 Sheets-Sheet 5 Filed Sept. 5, 1961 o o o o o o o o o o o o o c c o 0 0 0 0 o o o o o o o o o o o c o o o m 0 o o o o o o o o o o o 0 o o o o o o o m 0 M 0 o o o o o o o c o o o o o o a 0 o o o o o o o o o o o o o v 0 M H H H o o o o o o o o o o o o o o o o o o o w 0 O 0 0. 0 O u n O c 0 n O o o o O O H M H o o o c o o o o o n c o o o o o o c o O 0 O O O. O O O O O O O O O O O O O O o o o o u o o a o o o o o o a o o c Ewwa a WWQJJWHUHMWMMMZMMZ INVENTORS Egbert Ulbrich Oct. 11, 1966 Filed Sept. 5, 1961 E. ULBRICH ETAL com) DECIMAL ADDER 10 Sheets-Sheet 4 Fig.

mvsurons Egbert Ulbrich Karl Voitel & Johannes Martin 1966 E. ULBRICH ETAL 3,278,734

CODED DECIMAL ADDER Filed Sept. 5, 1961 10 Sheets-$heet 5 -5.75V -2DV -20V 5.75!

-1.35v -20v -1.35V

5E +13.5V -5.4 V

Fig-

INVENTORS Egberi Ulbrich K 0 rl Voi tel 8 Oct. 11, 1966 E. ULBRICH ETAL CODED DECIMAL ADDER 1O Sheets-Sheet 6 Filed Sept. 5, 1961 5 789m M 5& 55885 S INVENTORS Egbert Ulbrich Karl Voiie! 8 Johannes Martin ATTORNEY Oct. 11, 1966 E. ULBRICH ETAL 3,278,734

CODED DECIMAL ADDER Filed Sept. 5, 1961 10 Sheets She t 7 Egbert Ulbrich Karl Voitel 81 Johannes Martin Oct. 11,1966 E. ULBRICH ETAL. I 3,278,734

CODED DEGIMAL ADDER Filed Sept. 5, 1961 10 heetsheet s AC (Fig.3

l I J3 l3 171 (Fig.4)

INVENTORS Egbert Ulbrich Karl Voitel 8 Johannes Martin Oct. 11, 1966 Filed Sept. 5, 1961 E. ULBRICH ETAL CODED DEGIMAL ADDER 10 Sheets-Sheet 9 MD Ac 8 5 1- 3 '7 0 0 00L0 0LOL 0 00LL 0LLL 0 0000 0000 1 10 I 0 0000 0000 0 00LL 0LLL 2 2 L LLLL LLLL 3 0v LL00 LL 00 4 0 0LLO 0LLO 0 00LL OLLL 5 5a 0 LO0L LLOL 0 0000 0000 5b 0 00L0 0LOL '0LO0L LL0L 5d 0 00L0 0LOL 0 LOLL L000 0 0000 LOL0 7 0 LOLL L000 0LOLL 00L0 0 000L 0000 3 0 LOLL L000 0 LL00 00L0 0 0000 0000 0b 0 L0LL L000 L 00LL LLoL 0 0000 0000 81: L 00LL LLOL. 0 LoLL L000 L 00LL LL0L 9 L 00LL LL0L L L000 0LOL 0 oLLL 0000 10 L LL00 00L0 12 0 0LLO 0000 13 13 0 0L00 0000 0 0LLL 0000 $11;

5 0 0LLO 0000 0 0000 0000 1 15 L 00LL LLOL 0 0000 0000 0 0LLO 0000 17 17 0 0000 0000 L 00LL LL01. 0 0LL0 0000 $1 10 0 0000 0000 L LO0L LLOL 0 0000 0000 186 0 0000 0000 0 0LLO 00L0 0 0000 0000 lNVENTORS Egbert Ulbrich Karl Voitel 8 Johannes Martin Oct. 11, 1966 Filed Sept. 5, 1961 E. ULBRICH ETAL CODED DEGIMAL ADDER 10 Sheets-Shed 10 7 MD -AC 08 1 2 7 3 5 U 0 00L0 0LLL LL00 LOL0 0 0000 0000 1 1b l 0 00L0 0LLL L LL00 LOL0 $5 6 0 GOLD 0LLI. L LLLO LLOL 0 0000 0L00 7 7 L LLLo LL0L L LLLO L00L 0 0000 L000 8 80 L LLLO LLOL L LLLL 000L 0 0000 0000 01: L LLLL 000L I. LLLO LLOL L LLLL 000L 9 9 0 000L LL00 L LL00 00L0 1o 0 0000 LLLO 11 13 0 0000 0L00 L LL00 00L0 14 16 1. LLLL 0001. 0 0000 0000 0 0000 0LL0 17 0 0000 0000 L LLLL 000L 0 0000 0LL0 18b 0 0000 0000 L'LLLL mu 0 0000 0000 INVENTORS Egbert Ulbrich Karl voitela Johannes Martin ATTORNEY United States Patent 3,278,734 CODED DECIMAL ADDER Egbert Ulbrich, Karl Voitel, and Johannes Martin, all of Backnang, Germany, assignors to Telefunken Patent! verwertungs-G.m.b.H., Ulm, Donau, Germany Filed Sept. 5, 1961, Ser. No. 136,710

' 15 Claims. (Cl. 235-469) The present invention relates generally to computers and more particularly to such devices for adding binary coded decimal numbers in a parallel binary arithmetic unit wherein negative operands are represented as complements or inversions (0 L, L- 0) of the corresponding positive values.

It should be noted that in order to prevent confusion with decimal 1, logic ONE will be indicated as L throughout the specification and claims.

The main object of the present invention is to provide a computer process for adding binary coded decimal numbers regardless of their algebraic signs.

Another object of the invention is to simplify this operation.

According to the present invention, when adding two positive operands OLLO (=6) is added in each tetrad and then OLLO is subtracted in those tetrads which did not result in a carry or transfer into the next higher tetrad (carry-free tetrads). When processing two negative operands, they are first made positive by inversion and.

then the process is carried out as with positive operands. Afterwards the corrected result is reinverted. When processing operands of different algebraic signs, after the addition of the two operands 0LLO is subtracted in the carry-free tetrads if the sum is positive; and if the sum is negative, OLLO is added in-the-tetrads where a carry has taken place (carry-affected tetrads). The subtrac-v tion of OLLO in the individual tetrads is preferably accomplished by inverting the total number, adding OLLO in the tetrads concerned, and reinverting the total number.

In a variation of the above-mentioned computing process, when adding two negative operands, OLLO is subtracted, i.e., LOOL is added, in each tetrad and then OLLO is added to the tetrads which have resulted in a double carry into the next higher tetrad.

Additional objects and advantages of the present invention will become apparent upon consideration of the following description when taken in conjunction with the accompanying drawings in which:

FIGURE 1 is a flow diagram of the process comprising the present invention. I

. FIGURE la is a flow diagram of another embodiment of this process with only the differing steps being identi- FIGURE 2 is a block diagram of a parallel arithmetic unit for a binary computer.

FIGURE 3 is an elevational view of a plugboard for the arithmetic unit for connecting the register elements for each digit to other circuits.

FIGURE 4 is a circuit diagram of one of the networks, which is connected to the plugboard.

FIGURES 4a-4c illustrate the legends used in the drawings to designate resistor connections, diode connections, and direct connections, respectively.

FIGURE 5 is a circuit diagram of a register element.

FIGURE 6 is a circuit diagram of a power element.

FIGURE 7 is a circuit diagram of the microprogram.

FIGURE 8 is a Boolean algebra notation of this program.

FIGURE 9 is a block diagram showing the circuit connection when switching chain element LS is in operation.

' and b! Set K=Ol along the no arrow.

ice

FIGURE 10 is an example of the computing steps when adding two positive numbers.

FIGURE 11 is an example when adding one negative and one positive number. I

In the following description, inversion of a binary number or of a binary coded decimal number means that each 0 is converted to a L and each L is converted to a 0. The above-mentioned computing process for a digital computer is shown as a flow diagram in FIGURE 1. In the boxes having a '2 at the end, the computer is to make a yes-no decision, and in the boxes having an I at the end, the computer is to carry out a command.

In the first step, the computer decides whether or not the signs of the two operands are equal. This is indicated by step (a) sign (a)=(b)?. In the event that the signs are equal, the process follows the yes arrow which points to step (b) sign(a,b) positive? where the further decision as to whether the signs are algebraicly positive or negative must be decided. In the event that the signs are positive, the process follows the yes arrow which points to step (0) Set K=L! Where this fact is stored in the computer by setting a bistable element K at condition L. In the event that both signs are negative, the process proceeds from step (b) to step (d) invert a In the step (d), a and b are to be inverted and the bistable element K is set at 0. 1

As the next step, when both signs are the same, the process proceeds to step (e) form a+b+c=2! wherein the sum of a+b+c is formed. It should be noted that +c means that OLLO is added in all tetrads. next step (1) invert E!=2 this sum is inverted. After the inversion step the process proceeds to step (g) add OLLO in all T; of 2!=2 where OLLO is added to the tetrads in which there was no carry. Now the result has to be again inverted if both signs were originally positive. If both were negative, the result already represents the final result. This information has already been stored in the bistable element K. The computer thus determines whether K stands at L, as indicated by step (h) K=L?. If the answer is yes the process continues with step (i) invert 2"!=E Where the last sum is inverted again. If the answer is no" 2 is already the result (=E).

If the two operands had different algebraic signs, firs the sum of a and b is formed. This is indicated by following the no arrow starting from step (a) sign (a): sign (b)? to step (k) form a+b=Z! where the sum of a and b is determined. Step (1) decides whether this sum is negative, and if so OLLO is added by step (In) in all tetrads in which there has been a transfer (T and the sum thus formed represents the final re-' sult E. If the sum is positive the process proceeds to step (n) set K=L! and the sum is inverted as in step (f). The further processing of the intermediate sum 2" is now performed in the same manner as was described for the steps performed when the signs of a and b are equal.

Another embodiment of carrying out the process, which is mentioned above is shown in FIGURE 1a, where only the steps deviating from the above described process are shown. If both signs are negative, no inversion step is performed, but LOOL (=9) is added in all tetrads as indicated in step (d') form a+b+c!=2'. Subsequently in step (e') OLLO is added in those tetrads T where there have been double carries.

The following description will set forth the design of a microprogram circuit for a parallel binary computer which carries out the process described. FIGURES 2, 3 and 4 shows a parallel arithmetic unit. As seen in FIGURE 2, this unit contains at least two registers, namely, an

Patented Oct. 11,1966

As the accumulator register AC, comprising the register elements Ra Ra Ra and a carry or transfer register UB comprising the register elements Ru Ru Ru An auxiliary register is also provided which in this case is a multiplicand register MD which is generally present in computers, and which comprises N register elements Rd Rd Rd Each register element of these registers has two inputs, which are designated by the corresponding lower case letter with a subscript and a prime. By means of these inputs, the register elements can be set at or L. The 0 inputs are indicated by a superscript horizontal bar. For example, the Nth element of the MD register Rd has input d for L and d for 0. Correspondingly, the outputs of the register elements are designated by the same character but without the prime. Thus, the outputs of element Rd are indicated d and d,,. In addition, each register element has a cycle or timing input T, which is connected with a source of cycle or timing pulses. The computer is organized in a known manner whereby the register elements include a preliminary storage element which is set by the inputs at 0 or L on one pulse and the information in the preliminary storage element is transferred to the register element proper on the subsequent cycle pulse.

FIGURE illustrates an example of a complete register element R in the form of a bistable flip-flop of the Eccles- Jordan circuit type. This includes the

transistors

1 and 2 which are controlled from their bases. The

capacitors

3 and 4, which are charged via the inputs p and p, serve as preliminary storage elements. A source of cycle pulses is connected with the terminal T. If, for example, the terrninal p is at a positive potential before a cycle pulse, the condenser 4 is first charged. On the next cycle pulse this charge is carried to the base of transistor 2 so that this transistor 2 now conducts and blocks transistor 1. The output terminal 2 then has a positive potential while the output terminal p has a negative potential. The mode of operation of such bistable elements is known per se and therefore will not be described in further detail.

The arithmetic unit shown in FIGURE 2 further comprises a time switching chain SK comprising the individual elements LS LS L5 which are designed in the form of power elements. Power elements are effective elements which, although logically representing customary conditions for a conjunction, differ electrically from other conditions in that they provide the total power for all connections to a conjunction and may be thought of as elements which activate or deactivate the conjunctions. This time switching chain controls the timing or sequence of the individual commands of a microprogram. The main characteristic of these power elements is that they provide substantially greater power at their outputs S S S than the register elements, in order to control the conjunctive and disjunctive connections of corresponding register elements which elements are generally in parallel for all N binary digits. Conjunctive connections are those logical connections effected by an AND circuit, i.e., all conditions must be met in order to complete the connections, and disjunctive connections are those logical connections effected by an OR-circuit, i.e., only one condition need be met in order to complete the connections. Each of the power elements has a single input S and a single output S If a positive voltage is applied to the input, the elements remain actuated from the next cycle pulse to the following cycle pulse, and are deactuated if the input voltage has disappeared by the time this latter pulse appears. To carry out this function, these elements are provided with a preliminary storage element which is connected with the input terminal.

In FIGURE 6, such a power element LS is shown in detail. When a positive DC. voltage is applied to the input 8' the preliminary storage element, which is a condenser 5, is charged via a transistor 6. This charge is transferred to the transistor 7 by means of the next pulse fed to the cycle pulse input terminal T. The

other transistors

8, 9 and 10 amplify the power which is to be tapped at the output S The detailed function of such a power element is not an object of the present invention and is therefore not described in further detail. Whenever a positive voltage is applied to the input S,,, a positive voltage with sufiicient power for controlling several logical circuits is provided at the output S in the next cycle.

In addition to the switching chain described, the arithmetic unit contains further power elements LA LA LA LA LA LD and LU (FIGURE 2) the functions of which are described in detail below. Furthermore, the arithmetic unit contains some register elements Rr ,Rr Rr which are designed the same as the register elements of the MD, AC and UB registers, and the functions of which will also be described below. In the foregoing, only the power and register elements which are necessary for the special microprogram of decimal addition for practicing the invention are set forth. The other parts of the computer have been omitted for the sake of clarity.

In addition to the register and power elements of FIG- URE 2, the arithmetic unit comprises a number of networks wherein, for each binary digit, the logical connections necessary for the calculating operations are provided by means of resistances and diodes. The number of networks corresponds to the capacity which is desired for the binary computer and one network is coordinated with each binary digit. In addition, at least one network is provided for the algebraic sign. FIGURE 4 diagrammatically shows a network that is constructed of Pertinax, for example, or some other suitable insulating material. The front side of this material is provided with horizontal conductors arranged parallel to one another, while the rear side is provided with conductors extending at right angles thereto. The ends of the horizontal conductors are provided with plug-in devices such as plugs which fit into corresponding sockets of a plugboard shown in FIG- URE 3.

For the sake of clarity, in FIGURE 4 the resistors are represented by a dot at the corresponding intersection of the horizontal and vertical conductors. As shown in FIGURE 4a, in each case these resistors connect a horizontal conductor with a vertical conductor. Diodes connect a horizontal conductor with a vertical conductor as indicated in FIGURE 4b. In FIGURE 4 this is indicated by a diagonal line connecting the two conductors. This diagonal has a dot at the end corresponding to the anode. In FIGURE 40, direct connections between horizontal and vertical conductors are indicated by a diagonal line having -a dot at both ends.

In FIGURE 4, legends near the ends of the horizontal conductors indicate terminals or plug-in devices which are plugged into the sockets of the plugboard which have corresponding legends. These legends indicate the terrninals of the register and power elements which are connected thereto. It should be noted that the index n extends from 1 to N. Thus, all sockets in the board having an index n, n-l, or n+1, are separately connected to the corresponding register element. On the other hand, the sockets without an index n are connected with one another for all N boards, as shown in FIGURE 3, so that the output of the corresponding power element acts simultaneously on all networks.

An exception to this is the socket series for A where two sockets are connected with one another, two are skipped, and then two sockets are again connected, etc. This series of sockets enables the arithmetic unit, which is for pure binary computation, to compute also with decimal numbers coded in tetrads. In the arrangement shown in FIGURE 3, it is assumed that the board with the index 1 is coordinated with the arithmetic sign V with O desigating the positive sign and L designating the negative sign. The

columns

2, 3, 4 and 5 are coordinated with the first tetrad T and the

columns

6, 7, 8 and 9 are coordinated with the second tetrad T etc. The bottom row k of the plugboard corresponds to a conjunction which responds if all register elements of the carry register UB are at 0, i.e., if the carry register is empty. Thes may be seen in FIGURE 4 when it is noted that, in each calculating unit network the horizontal conductor i is connected with the bottom line k via a diode and the vertical line to the extreme left.

The power elements of FIGURE 2, which have their outputs connected to each network of the arithmetic unit via the plugboard of FIGURE 3, have the following functions which are effected by the corresponding resistances and diodes shown in FIGURE 4.

LA., effects the connection of the conjunctions for the transfer of a number from the MD register into the AC register;

LA holds the cyclic sum in the AC register, that is, the sum modulo 2 of corresponding binary digits of the numbers recorded in the AC and UB registers, and simultaneously effects a transfer of the digits formed by the AC and the UB registers one position to the left into the UB register via conjunctive connections;

LA; inverts the content of the AC register, i.e., all Ls become s and all Os become Ls;

LA shifts the content of the AC register one position to the right thereby cancelling a but maintaining al LA cancels the AC register, i.e., all elements are placed at 0;

LA effects a partial cancellation of the AC register by setting the algebraic sign digit and the last two tetrad digits at zero while the other digits maintain their value;

LD effects a connection of the conjunctions for the.

transfer of a number from the AC register into the MD register, which is the opposite operation performed by LA and LU efiects the connection of the conjunctions for the transfer of a number from the AC register into the UB register.

The remaining individual register elements illustrated in FIGURE 2 have the following functions:

Rr is a flip-flop which is designed like a register element of the arithmetic unit (FIGURE 5) and which stores the finish signal of the transfer removal and makes it available. The transfer removal is finished when UB is empty, i.e., when all its register elements Ru are at zero. This is determined by the conjunction k and stored by the setting of Rr Rr is a similar indicator flip-flop which, for example, is set when both operands are negative.

Rr is a flip-flop which is set at L when the operation of the microprogram is completed. Its output transmits the finish signal of the operation to the command unit which then again has the arithmetic unit at its disposal for making further calculations.

FIGURE 7 diagrammatically shows the design of a microprogram network which is constructed similar to the arithmetic unit network of FIGURE 4 and which is designed for the microprogram of decimal addition which forms the object of the present invention. The outputs S S S of the time switching chain are connected with the input terminals of the microprogralm board via resistances. These outputs control the timing and the logical connections of the program generally outlined in FIGURE 1. The timing or sequence of this microprognam is shown in detail in FIGURE 8 using the Boolean algebra system of notation. The first column indicates a consecutive numbering of the states attained in the registers and, between these numbers, indicates the functioning outputs of the time switching chain. The three following columns MD, AC and U13 indicate the content of the MD register, the AC register, and the UB register at any given time. The last column contains the logical connections effected by the power elements LS L3 The inputs of the register elements (lower case letters) and of the power elements (capital letters) are indicated circuit inverts the content of the AC register.

6 in brackets. These inputs are set when, in addition to the positive output of the timeswitching chain element indicated in column 1, the conditions stated after the bracket are attained. Conjunctions are noted directly one after the other, while disjunctions are separated from one another by a v. The presence of the output voltage of the power element of the switching chain associated therewith has not been listed again, but as a further condition it must be provided. The wiring of the microprogram of FIGURE 7 is identical with the symbolic notation of FIGURE 8, and the latter represents an unambiguous indication for the circuit technician.

In order to illustrate the sequence or timing of the command, individual portions of the programs will now be explained. At the start, the operands Z and Z are carried into the MD and the AC registers in a known manner by a command in the command register (not shown). The first power element LS of the switching chain is set at L. The row S of the chart of FIGURE 8 indicates that three cases have to be distinguished, i.e., the cases in the right-hand column of the figure, noted by brackets and the following conditions which are set olf by semicolons:

Case 1: If the two sign register elements of the AC and MD registers are at condition L (outputs a and al and if the indicator register element Rr is at 0, which it always is at the start, this indicatesthat both algebraic signs are negative. Then, as indicated by the bracket, Rr LA and LS are set at L at the next cycle pulse. The switching chain thus remains in the first sequence stage (8' but prepares for Case 2 (r and initiates the inversion of Z in the AC register. The other negative operand Z is inverted (A' only in sequence stage 5 depending upon r r Case 2: If both signs are positive (a d or if during Case 1 the indicator flip-flop Rr has been set at L (1-5), then, as noted by the second bracket: the second sequence stage is prepared (8' the power element LU (U,,) is set which transfers the content of the AC register into the UB register; and the power element LA (A' is set which subsequently cancels the AC register. The state which is then attained is noted in row 1a of FIGURE 8. The first operand Z remains in the MD register, the absolute amount of the second operand Z appearsin the UB register, and the AC register is empty.

Case 3: If Z and Z have difii'erent algebraic signs, i.e., if one of the conditions FL; d or It] d is met, then, as noted in the third bracket: the sequence stages S to S are skipped and the sequence stage S of the switching chain (S' is prepared; the power element LU (U,,) is set, which effects the transfer of Z into the UB register; and the power element LA (A' is set, which effects the transfer of Z from the MD register into the AC register.

The sequence stages S S and S of the switching chain generate the 6 (OLLO) which is to be added or subtracted when the algebraic signs of the two operands are the same. This 6 (OLLO) is generated in each tetrad of the previously cancelled AC register (row 1a). As may be seen, this is accomplished by inverting the zeros (S by the action of LA partially cancelling the tetrads by means of the power element LA (S and shifting one digit to the right in each tetrad by means of the power element LA (S For better illustrating this action, the state of the circuit of the arithmetic unit in the sequence stage S is illustrated in detail in FIGURE 9. This state of the In the preceding cycle, the input S of the power element LS has voltage applied thereto by the output of the power element LS The first cycle pulse switches to the power elements LS via T so that a voltage appears at the output S This pulse also prepares the power elements LS (next sequence stage) and LA (inversion) to switch in through their input terminals 8' and A' The second cycle pulse switches in the power element LA via T so that the outputs a are now connected with the inputs a,, and the outputs a are connected with the inputs a' (n: 1,2,3, N) via the corresponding diades D and D which are placed into their conducting states by controlled action. At the third cycle pulse, the switching of the register elements Ra is carried out via the terminals T3- As early as the second cycle pulse, the power element LS of the switching chain was switched in via T' This power element prepares to carry out the operation of cancelling the sign digit and the last two tetrad digits by means of the power element LA (not shown), in the third cycle.

Sequence stage S forms the sum |Z |+c, where c is a number with 6 (OLLO) in each tetrad. First, the indicator flip-flop Rr is set at Zero in each case so that the condition F is obtained. As noted in the first set of brackets for stage S this condition is maintained, and the addition of [Z and c is carried out in the AC register (A' until the transfer is removed and the conjunction k responds (row 5a). At the next cycle pulse, this conjunction sets Rr at L and, at the same time, eifects the transfer of Z from the MD register into the AC register, and the transfer of lZ l-i-c from the AC register into the UB register. Further processing at sequence stage S now depends upon whether both operands were positive (F or negative (r If both operands were negative, which fact has been stored by setting the indicator flip-flop Rr in the sequence stage S the content of the AC register, namely the number Z is inverted (A and the sequence stage S is set (row 50). Then, in the sequence stage S the first cyclic sum 2 of lZ l, IZ I, and c is formed in the AC register while the carry bits, which have been shifted by one position to the left, are deposited in the UB register (n If both operands were positive (F the first cyclic 2 is formed in the AC register as early as the sequence stage S under the condition r 7 and the carry bits are deposited in the UB register. In this case the program immediately proceeds to sequence stage S7.

The first cyclic sum thus formed in the AC register, either in the sequence stage S (row 5d) or in the sequence stage S (row 6), must now be stored so that subsequently a determination may be made as to whether or not a transfer has taken place from a tetrad. Before describing this function of the microprogram circuit, the state prevailing when the sequence stage S is switched in will be summarized:

Case 1: Both operands have negative signs. The first cyclic sum 2 of |Z f and IZ I+c is held in the AC register. The indicator flip-flop Rr is set and thus has the output r L.

Case 2: Both operands have positive signs. The first cyc-lic sum 2 of Z and Z +c is held in the AC register, and the indicator flip-flop Rr is not set and has the output T2211, S r =0.

Case 3: Both operands have different signs. The first cyclic sum 2 of Z and Z is held in the AC register. The sequence stages to S have been skipped since in this case 0 has not been previously added.

Before the uncorrected addition result is formed by removal of the transfers deposited in the UB register, the first cyclic sum must be stored, so as to determine the carry-free and carry-affected tetrads, respectively. This is accomplished by comparing this first cyclic sum with the addition result which is still uncorrected regarding the presence of pseudo tetrads. Therefore, in sequence stage S7, the first cyclic sum 2 is stored in the MD register (D1,), and simultaneously the adding of the new carries produced by the first cyclic sum according to the principle of progressive carry removal (A,,) is initiated. This step is completed in the sequence stage S (S' A' As soon as the transfer is removed, i.e., the content of the UR register is zero, the conjunction k responds and:

with a positive sign (an) effects inversion of the uncorrected addition result (A';); or, with a negative sign (0 sets the indicator flip-flop Rr (r' In both cases, the flip-flop Rr is simultaneously set (r so that, at the next cycle pulse, the power elements LD,,, LU LA are switched in whereby the negative of the absolute value of the uncorrected addition result S is transferred into the MD and the UB registers and the stored first cyclic sum is transferred into the AC register (row 8c).

The corrections (addition or subtraction, respectively, of OLLO) still to be made to the pseudo tetrads formed depend upon the tetrads from which transfers into the next higher tetrad have or have not occurred. The presence of a transfer is determined by addition modulo 2 of the first cyclic sum 2 and the uncorrected addition result S. The auxiliary result obtained contains an L or a 0, respectively, in the lowest digit of a tetrad, depending upon whether a transfer has or has not taken place from the lower tetrad. This is based on the fact that when there is a transfer, the next higher binary digit changes from 0 into L or from L into 0 so that its sum modulo 2 equals L. If no change has occurred, the sum modulo 2 of 0 and 0 or of L and L is in each case equal to 0. The number OLLO to be added is formed from the L which appears, in a manner which will be described below.

If OLLO is to be added in carry-free tetrads, the cyclic sum 2 is inverted before the modulo 2 addition with the uncorrected addition result so that the auxiliary result then has a L in the next binary digit above those tetrads from which no transfer has taken place. This inversion is carried out in sequence stage 8,; (second bracket) if the sign digit in the AC register is positive (5 and the indicator flip-flop Rr has not been set at L6 in the sequence stage S In sequence stages 8,, to S the correction number is formed from the auxiliary result by a shift to the right (A and partial cancellation (A' This correction number contains OLLO in the tetrads to be corrected and 0000 in the tetrads which are not to be corrected. It is then carried into the UB register. Then, in sequence stage S this correction number is added to the uncorrected addition result |S'| which has in the interim been stored in MD and was then carried back to AC (A,,) in sequence stage S The formation of OLLO in the AC register is indicated, for one tetrad, in rows 9 to 15 of FIGURE 8 in column AC. The content of this one tetrad is indicated in the brackets, and the determining binary digit is shown in front. The symbol means that the determining L or 0 occurs in this case, X means that L or 0 occurs at random in this case, and 0 means that, by a partial cancellation, a 0 stands in this case.

In sequence stage S after the addition (A',,) of the correction number onto the uncorrected addition result IS], the content of the AC register under certain condition (F is inverted (A';) as soon as the transfer has been removed (k At the finish, the corrected addition result S stands in the AC register, the indicator flip-flops are set at 0 (F 73), and the sign end of operation is signalled (r by the flip-flop Rr The operation of the microprogram for decimal addition in a binary parallel computer has been described using an example which has been kept as simple as possible. Only the AC and UB registers need be capable of addition, while the MD register is used only as an auxiliary register. In general, in a binary computer the MD register, too, will be capable of computations and, possibly, further registers will be available. In such an event, some computing operations of the above-described program may be combined (for example, the addition of Z +Z +c) and the computing time may be even shorter. Thus, the circuit diagram shown in FIGURE 7 and the corresponding flowsheet of FIGURE 8 do not represent the only realization of the invention possible in connection with the microprogram according to FIGURE 1. This only represents one embodiment for which the special problem of decimal addition is provided, with as few circuit elements as possible, without regard to other programs to be carried out with this machine. Depending upon the circuit mean-s and logical connections which are present in the computer for other purposes, the network of FIGURE 7 may be correspondingly modified. Also, in the arithmetic unit according to FIGURES 2 and 4, only the circuit elements and logical circuits necessary for decimal addition are shown so that the description is not made more complex by statements which are not necessary for understanding the invention.

FIGURES 10 and 11 show two computing examples which may be readily understood with reference to FIG-

URES

7 and 8. FIGURE 10 shows the addition of two positive numbers +37=+62, and FIGURE 11 shows the addition of one positive and one negative number +27-35=-8.

It will be understood that the above description of the present inventionis susceptible to various modifications, changes, and adaptations, and the same are intended to be comprehended within the meaning and range of equivalents of the appended claims.

What is claimed is:

1. A computer, comprising in combination: an accumulator register; a carry register; an auxiliary register; a plurality of power element mean-s for simultaneously applying power signals to at least several elements of each register to carry out predetermined steps; control network means connecting said power element means with said registers and providing a predetermined connection forming a circuit means therebetween for each of a plurality of sequence stages, each predetermined connection being in a ditferent portion of said network means; sequence switching chain means adapted to receive timing pulses and individually actuating the predetermined connections, said network means being arranged to cause addition of decimal numbers having their digits binary coded in tetrads to form operands which are summands when ready for an addition process whether previously processed or not,-the circuit means defining said network means including: first circuit means for controlling said power element means to selectively invert the content of a register when it represents a negative binary number so that it represents the corresponding positive number; second circuit means for controlling said power element means to add two binary numbers in two registers to form a first cyclic sum exclusive of. all carries and for adding the carries to said sum to form an uncorrected addition result; and third circuit means for controlling said power element means to add said first cyclic sum and said uncorrected addition result to for man auxiliary number in one of said registers which indicates in the lowest digit of each of its tetrads whether a transfer from the next lower tetrad has taken place during formation of the uncorrected addition result.

2. A computer, comprising, in combination: an accumulator register; a carry register; an auxiliary register; a plurality of power element means for simultaneously applying power signals to at least several elements of each register to carry out predetermined steps; control network means connecting said power element means with said registers and providing a predetermined connection forming a circuit means therebetween for each of a plurality of sequence stages, each predetermined connection being in a different portion of said network means; sequence switching chain means adapted to receive timing pulses and individually actuating the circuit means, said network means being arranged to cause addition of decimal numbers having their digits binary coded in tetrads trolling said power element means for selectively inverting the content of a register when it represents a negative binary number so that it represents the corresponding positive number; second circuit means for controlling said power element means for adding in a binary manner the content of two registers according to the principle of progressive carry removal; and third circuit means for controlling said power element means for determining those tetrads in which a carry occurred, by adding the first cyclic sum of the binary addition before the carry removal, to the sum after the carry removal.

3. In a decimal addition control section of a parallel computer for controlling arithmetic registers formed of binary elements, the control section including means for inverting all binary positions of negative operands in the registers to represent them as corresponding positive numbers, an adder for adding in a binary manner the contents of two arithmetic registers according to the principle of progressive carry removal to form a first cyclic sum which is free of carries, and to form an uncorrected addition result which includes the carries, and means for forming correction numbers in an arithmetic register for selectively processing numbers coded in binary tetrads whose operands are arranged so that a decimal carry appears as a tetrad carry, the improvement comprising means for comparing the first cyclic sum of the binary addition with the uncorrected addition result to form in dependence upon the comparison a correction number in the content of one of said registers, and said correction number forming means being actuated responsive to a predetermined binary condition in said one register in the lowest binary position of the respective next higher tetrad from the one in which the carry occurred as an indication of a carry.

4. The improvement in a decimal addition control section as defined in claim 3 wherein the operands in two of the registers have negative signs and comprising means responsive to the two negative signs of the operands for subtracting OLLO in each tetrad of one of the operands said sign responsive means being arranged to thereafter add OLLO in those tetrads which have had a carry twice.

5. The improvement in a decimal addition control section as defined in claim 3 wherein the decimal numbers have their digits encoded in the natural binary code (84-2-1), and said correction number forming means being arranged to form a correction number of OLLO for each tetrad requiring correction.

6. The improvement in a decimal addition control section as defined in claim 5 comprising means for placing said one register into the predetermined binary condition in all binary positions, after which the means for forming correction numbers (OLLO) in all tetrads becomes effective and prepares for the addition of decimal 6 in each tetrad.

7. The improvement in a decimal addition control section as defined in claim 3 comprising means for adding ()LLO in each tetrad of a binary number when required for addition.

8. The improvement in a decimal addition control section as defined in claim 5 comprising means for adding OLLO in each tetrad of a binary number when required for addition.

9. In a parallel arithmetic unit of a computer for adding decimal numbers whose digits are binary coded in tetrads and wherein negative binary numbers are represented by inverting all binary digits representing the corresponding positive number, the unit including a plurality of registers formed of elements which represent binary digits, the improvement comprising means for adding two binary numbers in the registers to form in one register a first cyclic sum which omits carries and for then forming an uncorrected addition result by adding the carries; and means for comparing the lowest digit of each tetrad of the first cyclic sum with the similar digits of the tetrads of the uncorrected addition result to determine those tetrads in which a carry occurred.

10. The improvement in a parallel arithmetic unit as defined in claim 9 comprising means for forming a correction number in dependence upon the appearance of a carry in the tetrad during addition.

11. The improvement in a parallel arithmetic unit as defined in claim 10 comprising means for adding said correction number to the uncorrected addition result to thereby correct the addition result.

12. The improvement in a unit as defined in claim 9 wherein said comparing means is arranged to form an auxiliary number by adding the first cyclic sum and the uncorrected addition result, which auxiliary number thus has an L in the lowest binary digits of those tetrads into which a carry has moved and a O in the lowest binary digits of those tetrads into which no carry has moved, and further comprising means for forming a correction number from the auxiliary number which correction number includes a first correction tetrad in those tetrads of the auxiliary number where an L appears and a second correction tetrad in those tetrads of the auxiliary number where an appears.

13. The improvement in a unit as defined in claim 12 comprising means for adding said correction number to said uncorrected addition result to form a corrected addition result.

14. The improvement in a unit as defined in claim 12 wherein said correction number forming means is arranged to form OLLO as the first correction tetrad and 0000 as the second correction tetrad.

15. In a parallel arithmetic unit of a computer for adding decimal numbers in binary coded tetrad form which uses complementing and thus may need correction of addi- 1 addition result; and third means for causing addition of said first cyclic sum and said uncorrected addition result to form an auxiliary number which indicates in the lowest digit of each of its tetrads whether a transfer from the next lower tetrad has taken place during formation of the uncorrected addition result.

References Cited by the Examiner UNITED STATES PATENTS 2,947,479 8/1960 Sclmer 235-169 2,989,237 6/1961 Duke 235--169 2,991,009 7/1961 Edwards 23s 169 OTHER REFERENCES IBM Reference Manual 1401 Data Processing System, 1961.

IBM 650 Data Processing System Bulletins, 1958-59.

MALCOLM A. MORRISON, Primary Examiner. WALTER W. BURNS, JR., ROBERT C. BAILEY,

. Examiners.

B. D. REIN, M. J. SPIVAK, Assistant Examiners.

Claims

1. A COMPUTER, COMPRISING IN COMBINATION: AN ACCUMULATOR REGISTER; A CARRY REGISTER; AN AUXILIARY REGISTER; A PLURALITY OF POWER ELEMENT MEANS FOR SIMULTANEOUSLY APPLYING POWER SIGNALS TO AT LEAST SEVERAL ELEMENTS OF EACH REGISTER TO CARRY OUT PREDETERMINED STEPS; CONTROL NETWORK MEANS CONNECTING SAID POWER ELEMENT MEANS WITH SAID REGISTERS AND PROVIDING A PREDETERMINED CONNECTION FORMING A CIRCUIT MEANS THEREBETWEEN FOR EACH OF A PLURALITY OF SEQUENCE STAGES, EACH PREDETERMINED CONNECTION BEING IN A DIFFERENT PORTION OF SAID NETWORK MEANS; SEQUENCE SWITCHING CHAIN MEANS ADAPTED TO RECEIVE TIMING PULSES AND INDIVIDUALLY ACTUATING THE PREDETERMINED CONNECTIONS, SAID NETWORK MEANS BEING ARRANGED TO CAUSE ADDITION OF DECIMAL NUMBERS HAVING THEIR DIGITS BINARY CODED IN TETRADS TO FORM OPERANDS WHICH ARE SUMMANDS WHEN READY FOR AN ADDITION PROCESS WHETHER PREVIOUSLY PROCESSED OR NOT, THE CIRCUIT MEANS DEFINING SAID NETWORK MEANS INCLUDING: FIRST CIRCUIT MEANS FOR CONTROLLING SAID POWER ELEMENT MEANS TO SELECTIVELY INVERT THE CONTENT OF A REGISTER WHEN IT REPRESENTS A NEGATIVE BINARY NUMBER SO THAT IT REPRESENTS THE CORRESPONDING POSITIVE NUMBER; SECOND CIRCUIT MEANS FOR CONTROLLING SAID POWER ELEMENT MEANS TO ADD TWO BINARY NUMBERS IN TWO REGISTERS TO FORM A FIRST CYCLIC SUM EXCLUSIVE OF ALL CARRIES AND FOR ADDING THE CARRIES TO SAID SUM TO FORM AN UNCORRECTED ADDITION RESULT; AND THIRD CIRCUIT MEANS FOR CONTROLLING SAID POWER ELEMENT MEANS TO ADD SAID FIRST CYCLIC SUM AND SAID UNCORRECTED ADDITION RESULT TO FOR MAN AUXILIARY NUMBER IN ONE OF SAID REGISTERS WHICH INDICATES IN THE LOWEST DIGIT TO EACH OF ITS TETRADS WHETHER A TRANSFER FROM THE NEXT LOWER TETRAD HAS TAKEN PLACE DURING FORMATION OF THE UNCORRECTED ADDITION RESULT.