US3268871A - Computer control device - Google Patents

Computer control device Download PDF

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US3268871A
US3268871A US218873A US21887362A US3268871A US 3268871 A US3268871 A US 3268871A US 218873 A US218873 A US 218873A US 21887362 A US21887362 A US 21887362A US 3268871 A US3268871 A US 3268871A
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command
elements
microprogram
chain
register
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Handler Wolfgang
Maier Roland
Martin Johannes
Muller Otto
Voigt Heinz
Voitel Karl
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Telefunken Patentverwertungs GmbH
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Telefunken Patentverwertungs GmbH
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems

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  • All program controlled digital computers include at least one functional section capable of performing organization or arithmetic operations, such as an arithmetic unit. Such computers further include a functional section which retains information in a ready and avail able state so that the arithmetic unit may be provided with information from this functional section and may transfer information to this functional section, such as an input unit, an output unit, and/or a storage unit. These computers further include a functional section for controlling the information trailic between these units as well as the function of these units, such as a command unit.
  • a further development of the computer is the provision of a control device which assumes the control functions of the command unit and, in turn, handles the command unit as a passive functional section of the computer in the same manner as all of the other units. In this case general organization operations and all address calculations are performed in the command unit.
  • Such a control device for a program controlled digital computer is supplied with commands usually together Iwith one or more addresse-s indicating operands.
  • Such comands are provided from a storage unit or an input/ output unit.
  • the command unit is provided with a cornmand register for storing the command signals which are usually presented in electrical binary form.
  • This register is formed of bistable register elements, for example, flipllops or magnetic core devices having rectangular ferrites.
  • the contents of the command register is fed to a decoding device which is provided for the control device and which, in turn, controls one or more operation elements which make possible elemental operations, such as, for example, the logical connection of several registers in a computer, the transfer of information, or similar operations.
  • the decoding and encoding device which is a purely passive logic network is not sufficient for command decoding.
  • a known control device of this type uses magnetic bistable circuits as members of the continuous switching chains and includes a continuous switching chain for each command with chronologically successive elemental operations. It can be seen that a control device of this type is not constructed for optimum conditions especially with respect to the large expense which it entails,
  • a main object of the present invention is to provide a control device for a program controlled digital computer having further advantages over the above-described devices and which may be provided at less expense.
  • Another object of the instant invention is to provide a control device of the character described wherein various microprograms may selectively utilize other microprograms, to simplify the programming of the computer.
  • a further object of the present invention is to provide a control device which controls microprograms in such a manner that individual nanoprograms may be used in a plurality of microprograms in order to simplify operation and programming of the computer and render it more versatile.
  • a control device having bistable operational elements and a command register in a cornmand unit of the computer are provided.
  • this command unit an N-digit command is to be carried out and, if desired, one or more information addresses are stored in the form of binary command signals.
  • the bistable operation elements are controlled on the basis of a combination of command signals in the command section of the command register by means of a decoding device, to cause elemental operations.
  • a decoding device In order to carry out a command it is usually necessary to perform several elemental operations simultaneously and chronologically or sequentially; this is a so-called microprogram.
  • the various operational elements are connected with different members of continuous switching chains corresponding to the decoding device.
  • These switching chains include bistable elements with program controlled succession of members, so that only the rst member of such a continuous or sequence switching chain is selected by means of the command decoding.
  • the decoding device in addition to the continuous switching chains, is provided with several bistable operation elements so that one of 2N microprograms is chosen by selecting the first member of one of 2n continuous switching chains in dependence upon a lirst partial group of n command signals, and by selecting one of the ZN-n microprograms connected to a continuous switching chain by means of one or more conditional elements.
  • conditional elements are activated in dependence upon a second partial group of N-n command signals and remain activated or switched in during performance of the command.
  • FIGURE 1 is a block diagram illustrating the principle of a program controlled digital computer.
  • FIGURE 2 is a schematic view of a control device illustrating the principle of operation according t-o the present invention.
  • FIGURE 3 is a circuit diagram of a known bistable element which is a register element.
  • FIGURE 4 is a circuit diagram of a known bistable element which is a power element.
  • FIGURE 5 is an explanatory view indicating the block symbol which is used yin the following drawings to indicate the register element.
  • FIGURE 6 is an explanatory view indicating the block symbol which is used in the following drawings to indicate the power element.
  • FIGURE 7 is a 4block diagram partially in schematic representation indicating a portion of the control device of FIGURE 2.
  • FIGURE 8 illustrates one embodiment of a decoding device in accordance with the present invention.
  • FIGURE 9 illustrates another embodiment of a decoding device according to the instant invention.
  • FIGURE 10 is a circuit diagram of the connection or interrelationship between the connecting circuit and the circuit elements illustrated in the drawings.
  • FIGURE 11 is a block diagram of operation elements to ⁇ be placed on an element plate.
  • FIGURE 12 is an explanatory view indicating the symlbols used in the following drawing to indicate a resistor and a diode.
  • FIGURE 13 is a schematic view of a known decoding circuit provided in matrix form on a matrix plate.
  • FIGURE J Program controlled digital computer, FIG URE J
  • a command unit l an arithmetic unit 2, a storage unit 3, an input/ output unit 4, and a control device 5 are connected to cooperate in a known manner.
  • the paths of information indicated by arrows are incomplete and are only symbolical in nature.
  • the processing and the transfer of a word (group of binary signals) are carried out simultaneously (in parallel) in the example shown.
  • the command unit 1 contains a command register 6, 7, which includes the operation or instruction register OP (r6) and the address register A (7).
  • the operation register OP which in the present case has eight register elements, contains, in coded form, the operational part of a command to be presently carried out.
  • the address register A contains the address of the command for the storage unit control.
  • a command counter Bz (8) is provided in the command unit 1 which increases the address continuously by 1.
  • a register B (9) is provided in the command unit for address conversions.
  • the arithmetic unit 2 includes three registers AC (10), HR (11) and MD (12).
  • the storage unit 3 includes an index storage means X (14) with the control register AX (13) for address decoding pertaining thereto, and with the storage register SRX (1S) also pertaining thereto. Further included are a storage block SP (17) with address decoding register AR (16) and storage register SR (18). Information is fed to the computer or extracted from the computer by the input and output portions, respectively, of unit EA (4).
  • the functional section comprising the present invention is the microprogram control device 5 with the decoding devices 19, 20, and 21; an operation element LAp (23); and the control section proper MPS (22) containing the continuous switching chains and the conditional elements, this control section controlling the chronological sequence of all commands.
  • the operation element 23 is controlled at the start of the operation of the computer by the connecting terminal 24, simultaneously with the input/output unit 4. This operation element sets the microprogram control device 5 into operation.
  • a distributor register VR (25) transfers information between the individual units and briefly, in an intermediate sense, stores information.
  • the command register 6, 7 possesses the same capacity as the arithmetic unit registers 10, 11, 12, the storage register 18, and the distributor register 25.
  • FIGURE 2 Principle of the control device, FIGURE 2
  • the command register of FIGURE 1 (6, 7) is shown as being divided into three boxes representing sections 31, 32, and 7, of which 31 and 32 designate the instruction section OP and 7 designates the address section A.
  • FIGURES l and 2 Corresponding elements in FIGURES l and 2 are indicated by the same reference numerals. The number and the llength of the addresses are of no significance for the present discussion and in the following description the address portion need no longer be considered.
  • the S-digit command portion is divided into a first partial group 31 of n command signals which, in the example illustrated is 3, and a second partial group 32, having the remainder of the command signals.
  • two devices 19 and 20 for decoding 1 out of 23 and 1 out of 23-3 are provided so that one of 23 or 8 continuous switching chains 36 and one of 28*3 or 32 conditional elements 37 are switched in by each command.
  • Each continuous switching chain Sa where a is a number between l and 23 or 8, includes three chain members LSal, LSa2, and LSa3, but this number is merely used as an example and in practice will usually be larger.
  • the individual members of one chain are advantageously not fixedly connected with each other, but are advanced in a sequence depending upon the program.
  • the device 19 selects one of the 23 continuous switching chains on the basis of the first partial group 31 of the command signals, that is, a preferred member of one cha-in.
  • This chain member, and any other, is capable of controlling several operation elements which, in turn, make the operations possible.
  • FIGURE 2 several operation elements to be switched in simultaneously within a microprogram are symbolically illustrated by means of a small circle 38.
  • This structure can be thought of as a spat-ital network which is constructed of such little circles, whereby one of the 23 planes lying parallel to the plane of the drawing is selected by device 19, while the 28-3 conditional elements 37 control a column and the respective position of the continuous switching chain controls a row.
  • microprogram is wired into a vertical column of one plane and such microprogram is selected by a conditional element 37, for example, Rbz, and a continuous switching chain, for example, S1.
  • conditional element 37 for example, Rbz
  • continuous switching chain for example, S1.
  • three different stations or positions with respectively several elementary opera- OIIS are possible: 0112, 0122, and 0132.
  • Each microprogram has exactly one column in one plane, i.e., it is fixedly connected with a continuous switching chain and with a conditional element. Further switching within one microprotgram is carried out by means of only one continuous switching chain. Thus, far fewer continuous switching chains are provided than possible commands.
  • Predetermined groups of command signals are assigned to the continuous switching chains 36 and to the conditional elements 37, respectively, so that several microprograms which are to be combined into groups in accordance with any desired considerations, are controlled by one conditional element or by one chain, and thus possess a similar command code.
  • FIGURES 3 and 4 In FIGURES 3 and 4, two kinds of bistable elements are shown which may be incorporated in a practical construction for utilizing the principle illustrated in FIG- URE 2.
  • FIGURE 3 shows a known bistable element having the transistors T9 and T10 arranged in an Eccles- Jordan circuit. The circuit has two information inputs E' and a clock pulse input T, and two information outputs E and E, as well as two storage capacitors 11 and 12 whose charge, which is dependent upon the input information, is interrogated by the clock pulse.
  • the bistable element is brought into condition ONE by the next clock pulse, so that a voltage corresponding to logical ONE is present at output E, and a ZERO voltage is present at output
  • This condition is provided by a positive potential of output E in comparison with The lclock pulse by itself is not capable 0f changing the element.
  • FIGURE 4 a similar known bistable element is illustrated which has only one input E and one output E for information, as well as a clock pulse input T and storage capacitors 13 and 13a.
  • a ONE voltage will appear at output E only when the capacitor 13 has been charged by the input E' and a clock pulse is present. If only the necessary clock pulse is present, the element is again put into condition ZERO via the capacitor 13a and the emitter of a transistor of the bistable circuit, it being noted that the more positive voltage shall always be considered to mean the ONE voltage.
  • FIGURE 3 the element according to FIGURE 3 will be called register element R, and the element according to FIGURE 4 will be called power element L; the former is symbolically illustrated, in the following FIGURES 7 through ll, as a rectangle with four terminals (see FIGURE 5), while the power element is indicated by means of a rectangle with two terminals (see FIGURE 6).
  • FIG- URE 7 Construction and operation of the control device, FIG- URE 7
  • the illustration is confined to one plane, i.e., to one continuous switching chain S1 and even to only one microprogram which is controlled by the conditional element Rb2. rI ⁇ he three lattice points from FIGURE 2, Om, 0122, Om, correspond to the circuit shown in FIGURE 7.
  • the first partial group of command signals selects the iirst power element LSll of the rst continuous switching chain through the decoding circuit 19.
  • Two conjunction resistors 44 and 45 are connected with the output of this first power element. They respectively lead to the conjunction point of a known AND-circuit.
  • the diodes pertaining thereto are connected to the conditional register element Rb2 and are connected for fultilling additional conditions, depending upon a former program, upon the position of the arithmetic registers, or upon similar facts.
  • the terminals for these additional conditions are designated S6 and S7.
  • the output of the AND- circuit is constituted by the conjunction point proper and is, in turn, effective as the input of a succeeding OR- circuit whose working or operating resistance is in the input circuit of the succeeding bistable elements.
  • the first switching circuit with the resistor 44 switches in the second power element of the continuous switching chain LS12 and a register element 46 if LSll and Rb2, as well as the additional condition 56, have positive output potential.
  • the second connection circuit (with the resistor 45) is activated and no operation element, but only the third chain member LS13 is activated, LS12 being by-passed,
  • the brief exemplary program is continued in the tirst case, by changing the second member LS12 of the continuous switching chain to ONE by means of the succeeding clock pulse, while the first chain member is deactivated in a conventional manner by means of the clock pulse.
  • two further elements 47 and 48 which are a power element and a register element, re ⁇ spectively, are activated or switched in without any additional conditions, and the third member of the continuous switching chain is prepared.
  • This third member could, if desired, already be controlled before this step by LSll via resistor 45.
  • two possibilities are provided, i.e., there is conditional operation and a register element 49 varies the program.
  • the microprogram is assumed to be finished, and a final signal element 50 is set.
  • element 49 is assumed to be at condition ZERO; then the conjunction device with the resistor 51 is switched in, but not the conjunction device with the resistor 52.
  • a power element 53 and the register element 49 are prepared and the jump to the first member LSll of the continuous switching chain is performed.
  • the above described program begins again and, at the end, the power element 53 is not activated, but two other elements, power element 54 and register element 5S, as well as the final signal element 50 are set, because the element 49 was in condition ONE.
  • control device described thus far may be varied substantially, and one of the many advantageous variations will be discussed.
  • 2s (256) microprograms are examples of 2s (256) microprograms.
  • command signals 32 which up to now determined one of the conditional elements 37, is once more divided.
  • One or two (considered generally m) command signals are branched off, and they form, and/or control, modification elements which represent additional conditions in the manner described in connection with FIGURE 7, c g., terminals 56 and 57.
  • modification elements By means of these modification elements, several similar microprograms present at a continuous switching chain and a conditional element are differentiated from one another with respect to the different portions of their programs, so that the modication elements thus are interrogated only in such different portions.
  • a register element is switched in as a chain lengthening element, and an extension chain, as well as a further conditional element are controlled.
  • the chain lengthening element is effective as an additional condition in the sense of terminal 56 in FIGURE 7 in all steps of the succeeding chain and has to be canceled at the end of the program.
  • the extension chain may be any desired other chain, or it may be the same continuous switching chain; the command register is not changed in the course of this extension.
  • the chain extending elements which can be used by all chains are required in addition to the ZN-n conditional elements provided by the decoding device.
  • control device proves especially advantageous in the processing of frequently occurring sub-routines, so-called nanoprograms.
  • Such program portions which are not independent commands may be applied to one or several additional continuous switching chains, which cannot be controlled via the command decoding step.
  • FIGURE 8 shows, in the usual logical representation, a portion of a mcroprogram in which a nanoprogram is employed.
  • the members of a nanoprogram chain which cannot be controlled directly by the command register are designated LNSl to LNS4.
  • LS are the members of a normal continuous switching chain
  • LO are power elements
  • Rb designates the conditional elements 37. At the instant being considered, this conditional element is in ONE condition together with the member 58 of the normal continuous switching chain.
  • a register element 59 is set as a nanoprogram element which is analogous to the conditional element in the microprogram.
  • a nanoprogram is carried out with all of the possibilities which are already known from considering the microprogram.
  • a conditional jump from LNSI to LNS3 is provided and whose condition is set, for example, by the superior microprogram.
  • LNSI, LNSZ or LNSl, LNS3, LNS4 are subsequently activated.
  • element 59 is again canceled so that processing of the microprogram may proceed.
  • the return from the nanoprogram to the correct microprogram has to be arranged. This may be done,
  • each of these microprograms set a certain number of register elements provided for this purpose when jumping into the nanoprogram.
  • the nanoprogram in its last step, and in dependence upon these register elements, activates by setting a certain member of its continuous switching chain and a certain one of its conditional elements, only that microprogram from which the jump into the nanoprogram was made. This requires:
  • a simplication of this return from the nanoprogram is provided according to the invention, in that the superior microprogram, simultaneously with its advance into the nanoprogram, advances, for example, to the next member 60 of its continuous switching chain and there controls this member during the course of the nanoprogram as long as the nanoprogram element 59 is set.
  • the operation which is connected with the member 60 is arranged to become effective only when the nanoprogram, in the last step, has canceled its nanoprogram element 59. Then, the nanoprogram, after it has run its course, need cancel only its own nanoprogram element, since only the superior microprogram which had been waiting is continued.
  • the nanoprogram and the microprogram may be carried out simultaneously, if simultaneous operation of several units of the computer is possible.
  • the waiting period in this case may take place at a subsequent member of the microprograrn continuous switching chain.
  • a further return is provided wherein the nanoprogram, in its last step, controls the superior microprogram by renewed decoding of its operation code which is still present in the command register.
  • FIGURE 9 F. Microprogram without a nanoprogram chain
  • FIGURE 9 an arrangement having a function similar to that of FIGURE 8 is illustrated. However, this arrangement omits the members of the nanoprogram chain. The reason for this is that since operation elements, as Well as the members of the chains, may be constructed of power elements according to FIGURE 4, the chain members may be replaced by operation elements. However, a xed sequence of operation can only be provided if the operation elements serving for continuous switching all differ from one another, as well as from the other operation elements of the nanoprogram, which often is the case in simple programs.
  • the control device is also well suited for fast computers having simultaneous operation.
  • Such computers have several units for processing the bits of information, for example, several arithmetic units, or one arithmetic unit, one control unit, and a storage unit.
  • microprograms for the above mentioned purpose are differentiated in accordance with the unit or units which they use.
  • microprograms which are processed only in the command unit and in the storage unit, eg., jump commands, commands for address computations, substitution commands, and word group transfer commands within the storage device, and the remainder of the microprograrns which are processed in the arithmetic unit.
  • microprograms of the tirst type are connected exclusively to one or two continuous switching chains so that in the latter case the first (n-1) command signals indicate the type of command.
  • conditional elements 37 and the modification elements are provided in duplicate whereby the first group only affects continuous switching chains which are associated with the independently operating microprograms, while the other group cooperates with the other chains.
  • the next following command is transferred into the command register, and an examination determines Whether this command permits simultaneous operation. If it does, then the register element for indicating simultaneous operation is automatically activated and the second command is decoded partially to the continuous switching chains and partially to the corresponding group of conditional elements and modification elements, whereby the choice as to which group is selected is determined from the first command signal. Now, two continuous switching chains work simultaneously to process different programs.
  • microprograms are also advantageous (l) to apply such microprograms to a special continuous switching chain and which only initially use several units, and then continue to operate an independent unit, or (2) provide such microprograms which initially use an independent unit and subsequently no longer permit simultaneous operation. In such cases, a waiting period is interposed and the simultaneous operation element is canceled or set when the simultaneous operation must end or may begin, respectively.
  • one of the two programs being performed should receive superiority over the other, while the remaining program is placed into a waiting period or loop which is controlled until certain conditions for further processing are fulfilled.
  • these conditions are, for instance, the missing final signal of the superior program, or the ofF' condition of the simultaneous operation element.
  • microprogram used as a narzoprogmm
  • the control device of the present invention may use a microprogram as a nanoprogram.
  • a microprogram was understood to mean a succession of elemental operations, the first of which is controlled by decoding the command section of the command register to a first member of a continuous switching chain. This definition must be more precise for the present type of operation since a microprogram may be initiated from the cornmand register, while a nanoprogram must be initiated or controlled by another microprogram or nanoprogram. In this sense the terms command and microprogram also have to be differentiated.
  • Each microprogram carries out, perhaps together with nanoprograms, just one simple command; but complicated commands use, if required, several microprograms.
  • a microprogram as a nanoprogram, e.g., the microprogram addition within the scope of a microprogram vector addition
  • a reasonable transition must be provided at the beginning and at the end of the subordinate microprogram.
  • the first member of the new continuous switching chain, the conditional element, and the modification elements are activated by the superior program, while the conditional element and the modification elements for the superior program are canceled.
  • a new register element, the blocking element remains to be activated in order to prevent the transfer of a new command into the command register together with the nal signal of the subordinate program.
  • the superior command is still present, as explained above. If this final signal appears, the command register is again decoded to the continuous switching chain, conditional elements, and modification elements, the blocking element is canceled, and the operation of the superior program is continued.
  • command cycle or organizational phase shall be understood to mean those microoperations which initiate each execution of a command, i.e., obtain the next command from the storage device, modify the same, if necessary, obtain the operands, activate the continuous switching chain, the conditional element, and the modification element, and supervise a possible simultaneous operation.
  • This organizational phase is preferably provided only once for all commands combined.
  • the organizational phase must be considered as being the latter, because it is not to be assigned to any independent command.
  • the organizational phase because of its special nature, is outside of both of these definitions, if considered systematically, it nevertheless may be activated by the same means, i.e., operation elements, continuous switching chain, etc. and may be described just as the normal programs.
  • FIGURE l0 shows a simple logic circuit and indicates the analogy to the circuit algebra.
  • a power element has its output connected to terminal L which is connected with conjunction points via resistors R (conjunction resistors).
  • the outputs a, b c, d, and e of register elements are connected to the conjunction diodes D1, D2, D3, D4, and D5, respectively, and the input x' of a further operational element (register or power element) is connected to the disjunction diodes D6 and D7.
  • the diodes D1 to D3 form one group and diodes D4, DS form another group, the groups forming one conjunction, respectively, and these groups are connected by disjunction diodes D6 and D7, respectively.
  • the disjunction resistors of these diodes are in the input circuit of the bistable elements.
  • the diodes D1 to D3 and D4, D5 affect the input of the bistable element (x' in FIGURE 10).
  • a conjunction is expressed by means of a multiplication sign (period) between the symbols representing the element outputs, but when the meaning will be clear, the period may be omitted.
  • a disjunction is represented by means of the or sign v or between the corresponding element symbols.
  • the wiring of a program controlled parallel computer is provided by matrix plates to form a systematic arrangement, for example.
  • the matrix plates are insulated plates which have groups of parallel conductors printed on both sides. Both groups of conductors are in right angle relationship toeach other, and only one group of conductors extends externally by means of contacts or terminals.
  • the matrix plates are provided with circuit components such as resistors and diodes and are connected with plates carrying the circuit elements corresponding thereto in such a manner that terminals of the same type on different matrix plates and element plates are connected with one another. Thus, if the terminal S1 appears on one matrix plate, the output of the power element LS1 present on an element plate is connected with this terminal.
  • a crossing point between two conductors without any marking means that the conductors are not connected with each other at this point.
  • a crossing point with an oblique line indicates a crystal diode connecting the conductors in such manner that the cathode of the crystal diode is connected with the conductor leading to the element terminals.
  • a dot indicates that a resistor connects the conductors.
  • FIGURE l1 The bistable elements required for performing the programs are shown in FIGURE l1. They may be provided on printed circuit plates at random, as far as their construction is concerned.
  • R01 R06 are six of the bistable elements contained in command register 6;
  • Ral is an element of the address section 7;
  • Rrw, Rbw, Rs, Rx, Re, Rra, Rrb, Rrc, Rm, Rrs, Rrf, and Rrl are register elements for specific functions which will be described below.
  • the register elements RblR Rb8R and RblB Rb8B are the above-described two groups of conditional elements for selecting individual microprograms.
  • LSl).1 LS7.1 are, respectively, the rst members of the eight microprogram continuous switching chains.
  • LS4.2, 1.55.2, and LS5.3 are further members of microprogram continuous switching chains.
  • LNSl LNS4 are the members of a nanoprogram chain which also controls the interrogation program together with the nanoprogram element RaB.
  • LBv causes command pre-decoding for modifying the interrogation program
  • LAz causes transfer of the contents of the command counter into the address section of the command register
  • LAp causes a jump into the interrogation program
  • LPa activates a storage cycle whereby the register elements Rs, Rx, and Rrs effect the differentiation between the main storage device and the index storage device and/or between reading and writing;
  • LVs transfers the contents of the storage register 18 into the distributor register 25;
  • LAv transfers the contents of the distributor register to the command register
  • LRv represents an operation of the concluding mixed program but, since the subject of this description is the organization of the course of the program and the technique of connecting one program to another, and this concluding mixed program does not form part of this description, the further operations of this program will be described only in general terms;
  • 2 increases the contents of the address section 7 bytwo.
  • FIGURE 13 shows a matrix having the logical connection for pre-decoding and main decoding in disjunctive normal form.
  • this wiring system is represented in circuit algebraic form. If the operation power element LBv is activated, it causes the activation of elements Rrw and/or Rbw, depending upon the command code and whether the command present in the command register uses the arithmetic unit (r'w), the command unit (b'w), or both (rw, b'w). Furthermore, the power element sets the element Rs or the element Rx if the operand for the command is to be taken from the main storage device or the index storage device. Finally, the element Re is set if the present command provides for an address substitution. Besides this, Table 1 contains the wiring system of decoding to continuous switching chains and conditional elements. This decoding is caused by the power element LE.
  • Table l represent operations which ⁇ are controlled by the operation elements LBv and LE.
  • this type of representation is not used and only the control of the operation elements is being considered, while the effect of such control is presumed to be known.
  • the explicit presentation of the logical function on matrix plates is not provided since, after a consideration of the above explanations, the technical construction may be provided without difculty from the circuit algebraical representation.
  • the operation power element LAp is controlled by the end of a microprogram, for example, together with one of the program elements Rra, Rrc, Rrd.
  • This power element LAp together with the element Rm, provides setting of the nanoprogram element RaB of the interrogation phase in the first cycle of the interrogation program.
  • the contents of the command counter is transferred into the address section 7 (Az).
  • the operation element LAz is activated and is simultaneously effective as a member of this continuous switching chain. It causes the increase of the contents of the command counter (ZLH) and the control of the main storage cycle
  • LPa which is another operation element, is effective as continuous switching member and provides for a waiting period if the storage cycle is not yet finished (s). If the information then is available in the storage register (s), it is transferred into the distributor register (Vs).
  • a normal nanoprogram continuous switching member LNSI is activated ⁇ and the command present in the distributor register is transferred into the command register (Av). Now, the command may be pre-decoded (B'v) and, in the next cycle, the operand may be obtained (Pa).
  • the program automatically again moves on into this loop and transfers a word from the storage device into the distributor register.
  • the substitution command was Selected from the many possible modifications.
  • This substitution command was characterized in the command pre-decoding step by setting the register element Re, because in that case, in step LNSZ, the operand was not obtained, but a further command was obtained, which now again must be pre-decoded.
  • the element Rrb which had been inactivated in the preceding Step was set again, so that after the storage device control, the contents of the distributor register is again transferred into the command register. Only when a command is no longer a substitution command does the program again proceed into the described final phase.
  • the interrogation program may have already progressed up to decoding, while, at the same time, another program is still being processed in the arithmetic unit. In such cases, the interrogation program must be channeled into a waiting period or loop (NS'3:NS3-aB-rw'ff).
  • the elcment Rrf represents that the arithmetic unit is occupied; and it will be switched to ONE only when the yarithmetic unit is ready to handle a new program.
  • decoding may follow immediately since the interrogation program itself occupied the command unit.
  • the next following command may already pass through its interrogation phase, so that upon decoding at LNS4, LAp is already being controlled again.
  • This interrogation program may also be used as a normal nanoprogram by activating the element LAp by a superior microprogram as will be described below. The point where this occurs is determined by the program element Rrc or Rrd. Correspondingly, the pre-decoding or the main decoding are initiated immediately. The interrogation program is used before each execution of a command, and it also serves las an interrogation phase for the following microprogram.
  • This microprogram is illustrated in Table 3 (see Appendix) and shows the connection of the interrogation program with a program which is being processed in the arithmetic unit and in the command unit.
  • This program is present at the continuous switching chain 4 and is connected with the conditional element RblR.
  • this microprogram illustrates how a microprogram controls another microprogram.
  • This other microprogram is present, for example, at the continuous switching chain 5 and the conditional element RbZR.
  • the interrogation program transfers an operand into the distributor register. Then, when the arithmetic unit is unoccupied, it activates the continuous switching chain and conditional element in the main decoding step.
  • the operations R'v, A'B and BA are connected with the rst member.
  • register 9 In register 9, initially the first address of a group of bits of information is present, which is connected with a second group whose first address is present in the register 7.
  • the two addresses are adjacent each other so that the two groups are alternately inserted in the storage device one into the other with the two addresses adjacent.
  • the operation Rv for example, causes the transfer of the first operand from the distributor register into a first arithmetic register.
  • the return from the subordinate microprogram into the superior program is now combined with the indication that the arithmetic unit is unoccupied (rf) with the aid of a portion of the interrogation program.
  • the interrogation program was used in step LNS3, i.e., in the main decoding step. There, a waiting period is provided which, for main decoding, is nished when element Rrf is in a certain condition.
  • an operand of the second group with Mv is transferred into a second arithmetic register, since element Rrl was set when the program was carried out the rst time, which element was inactivated again at the second cycle.
  • an operand of the one group and an operand of the other group is transferred into the respective arithmetic register and is processed in the subordinate microprogram, until the last operands have been processed.
  • the end is indicated, for example, by the element Ral which is set after the last operand of the second group, by means of further counting in register 7 (At-2).
  • the interrogation program is used in step Rb1R LS4.2 for taking over a new command.
  • the nanoprograms effect a shortening of many microprograms, since the contents of a nanoprogram would otherwise have to be inserted into several microprograms.
  • the organization of returning from a nanoprogram into a microprogram by means of a waiting period and/or renewed operation-code-decoding makes possible a flexible application of the nanoprograms and simultaneous operation of a microprogram and a nanoprogram.
  • the simultaneous operation shortens the computing times with the computer speed remaining the same.
  • a microprogram control device of a program controlled digital computer with bistable operation elements which when activated initiate corresponding elemental operations, and with a command register in a command unit of the computer, in which an N-digit command to be carried out is stored, and, if desired, one or more information addresses are stored in the form of binary command signals, the command register being arranged so that generally one command controls, via a decoding device, the activation of a whole microprogram, wherein a microprogram comprises a number of selected operation elements activated in a number of sequential steps which immediately follow one another, the decoding device comprising several switching chains made up of bistable chain elements which in turn activate the selected operation elements, each switching chain having a first chain element activated by decoding a first group of n command signals, and having further chain elements each being activated when the preceding chain element is deactivated, the improvement that the decoding device includes 2n switching chains each being connected to activate a group of 2N-n microprograms, and .2N-n bistable conditional elements
  • a microprogram control device for a computer comprising, in combination:
  • a command register for containing an N-digit command to be performed and dipossed in two groups, a first group providing n command signals, and a second group providing N-n command signals;
  • ZN' bistable conditional elements activated by the decoding device pertaining to the second group of command signals and being arranged so that the second group of command signals determines for each chain which of the microprograms connected to the chain is to be activated by selecting at least one of said conditional elements for activation, whereby the sequential activation of the chain sequentially activates the operational elements of the selected microprogram.
  • microprograms are connected to the switching chains in an arrangement such that at least one of the switching chains only controls microprograms which in turn control an operating unit of the computer which operates independently of the other units of the computer, and said device further comprising means to take over, in such cases, a further command and to process the same at the same time to provide for simultaneous operation.
  • a control device as defined in claim 4 wherein thc conditional elements are provided in duplicate, and at least one bistable element is provided which is set when simultaneous operation in several units of the computer which operate independently from one another is possible, so that one of the groups of the conditional elements accepts only independent commands and is etiective upon switching chains, which carry out the microprograms in an independently working unit, while the other group of the conditional elements cooperates with the other switching chains and is assigned to the other commands.
  • a control device for a computer comprising, in combination:
  • a command register for containing an N-digit command to be performed and disposed in two groups, a first group providing n command signals, and a second group providing N-n command signals;
  • conditional elements connected with the decoding device pertaining to the second group of command signals and each connected with 2 microprogram assemblies which are in turn each connected with a different switching chain, said conditional elements being arranged with said decoding device s that the second group of command signals determine which conditional element is to be activated, whereby activation of a conditional element and a switching chain selects one of the 2N microprogram assemblies to be performed and the sequential activation of the chain sequentially activates the operation eiements of the selected microprogram assembly.
  • a control device as defined in claim 7 comprising at least one further switching chain connected to be activated by a member of one of the microprogram continuous switching chains and which is arranged to initiate sequences of elemental operations forming frequently used sub-routines or nanoprograms.
  • a control device as defined in claim 9 comprising a plurality of bistable nanoprogram elements for performing and selecting several nanoprograms with one nanoprogram switching chain, and arranged so that at least one of the nanoprogram selecting elements is set by a respective superior microprogram assembly and is again inactivated in the last step of the nanoprogram.
  • a control device as defined in claim 9 comprising a plurality of nanoprogram elements arranged so that nanoprograms with few elemental operations which are different from e-ach other are effected by actuating the nanoprogram element corresponding to the first elemental operation of the nanoprogram and an actauted bistable element cooperating with the actuated nanoprogram element for effecting under the conjunctive condition a continuotrs switching out of the swit-ching chain.
  • a device as defined in claim 10 comprising elements forming a special nanoprogram for performing an interrogation program said elements being connected to the elements of at least one of said microprogram assemblies for providing organization routines which precede the execution of a command, said elements of the special nanoprogram being activated by the elements of said microprogram assemblies in a time relationship with respect to the preceding microprogram.
  • a control device as defined in claim 19 comprising individual independently operating units, each having a bistable element for indicating its condition of occupation and said units being connected to have the program therefor run through waiting loops if a unit already occupied is controlled by a simultaneously operated program.
  • a control device for a computer comprising, in combination a command register for containing an N-digit command to be performed and disposed in two groups, a flrst group providing n command signals, and a second group providing N-n command signals;
  • bistable elements arranged for initiating predetermined elemental operations when in the activated condition, selected groups and said bistable elements being arranged to form microprograms for initiating different sequences of elemental operations which form a microprogram;
  • 2Nn bistable conditional elements connected with the decoding device per-taining to the second group and each connected with 2n microprograms which are in turn each connected with a different switching chain, said conditional elements being arranged with said decoding device so that the second group of command signals determine which conditional element is to be activated, whereby activation of a conditional element and a switching chain selects one of the 2N microprograms to be performed and the sequential activation of the chain sequentially activates the bistable elements of the selected microprogram, and the number of chains and conditional elements being the same and representing an exponent of 2.
  • a control device for a computer comprising, in
  • a register capable of containing an N-digit command signal divided into a first group of n binary digits and a second group of N-n binary digits
  • switching chains each having a plurality of actuating elements which, upon triggering of the first actuating element, are sequentially triggered, said switching chains being connected to so much of said register which pertains to said irst group of binary digits so that the n digits of said first group are determinative of which switching chain is selected;
  • each microprogram having a plurality of elements corresponding in number to the number of elements in said switching chains, ⁇ the elements of said microprograms being connected to respective elements of said switching chains and actuated thereby so that upon the running through of a particular switching chain, the determined microprogram is caused to run through.
  • a miicroprogram control unit for the execution of microprograms, each of which comprises a number of partly simultaneously, partly subsequently performed elemental operations, which operations are released by an operation element corresponding thereto said microprogram unit comprising:
  • n N each comprising several chain members each formed by a bistable element, the rst chain member of which is activated when a microprogram is called by the command register, the remaining members of the chain being activated sequentially when the preceding member is deactivated so that always only one chain member is activated;
  • a rst decoding circuit with n inputs which are connected to n of the N digits of the command register, and with 2n outputs, each of which is connected to one chain member of the 2 switching chains;
  • a second decoding circuit with N-n inputs which are connected to the remaining N-n inputs of the N digits of the command register, and with 12N-n outputs which are connected to the inputs of said ZN-n conditional elements;

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3413609A (en) * 1965-04-15 1968-11-26 Gen Electric Indirect addressing apparatus for a data processing system
US3417380A (en) * 1965-04-05 1968-12-17 Ibm Instruction selection apparatus
US3493936A (en) * 1967-05-04 1970-02-03 Ncr Co Low cost high capability electronic data processing system
US3569939A (en) * 1963-12-31 1971-03-09 Bell Telephone Labor Inc Program controlled data processing system
US3781823A (en) * 1972-07-28 1973-12-25 Bell Telephone Labor Inc Computer control unit capable of dynamically reinterpreting instructions
US3872447A (en) * 1972-04-07 1975-03-18 Honeywell Inf Systems Computer control system using microprogramming and static/dynamic extension of control functions thru hardwired logic matrix
US3938103A (en) * 1974-03-20 1976-02-10 Welin Andrew M Inherently micro programmable high level language processor

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3478322A (en) * 1967-05-23 1969-11-11 Ibm Data processor employing electronically changeable control storage
DE2327950C3 (de) * 1973-06-01 1981-05-21 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Vorrichtung zur Steuerung industrieller Einrichtungen

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3039690A (en) * 1955-11-16 1962-06-19 Int Computers & Tabulators Ltd Computing machines

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3039690A (en) * 1955-11-16 1962-06-19 Int Computers & Tabulators Ltd Computing machines

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3569939A (en) * 1963-12-31 1971-03-09 Bell Telephone Labor Inc Program controlled data processing system
US3417380A (en) * 1965-04-05 1968-12-17 Ibm Instruction selection apparatus
US3413609A (en) * 1965-04-15 1968-11-26 Gen Electric Indirect addressing apparatus for a data processing system
US3493936A (en) * 1967-05-04 1970-02-03 Ncr Co Low cost high capability electronic data processing system
US3872447A (en) * 1972-04-07 1975-03-18 Honeywell Inf Systems Computer control system using microprogramming and static/dynamic extension of control functions thru hardwired logic matrix
US3781823A (en) * 1972-07-28 1973-12-25 Bell Telephone Labor Inc Computer control unit capable of dynamically reinterpreting instructions
US3938103A (en) * 1974-03-20 1976-02-10 Welin Andrew M Inherently micro programmable high level language processor

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