New! View global litigation for patent families

US3209074A - System for multiple output of spoken messages - Google Patents

System for multiple output of spoken messages Download PDF

Info

Publication number
US3209074A
US3209074A US11522861A US3209074A US 3209074 A US3209074 A US 3209074A US 11522861 A US11522861 A US 11522861A US 3209074 A US3209074 A US 3209074A
Authority
US
Grant status
Grant
Patent type
Prior art keywords
word
output
drum
audio
pulse
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
Inventor
Walter K French
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K21/00Details of pulse counters or frequency dividers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F3/00Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/16Sound input; Sound output
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11BINFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B3/00Recording by mechanical cutting, deforming or pressing, e.g. of grooves or pits; Reproducing by mechanical sensing; Record carriers therefor
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04MTELEPHONIC COMMUNICATION
    • H04M3/00Automatic or semi-automatic exchanges
    • H04M3/42Systems providing special services or facilities to subscribers

Description

Sept. 28, 1965 SYSTEM FOR MULTIPLE OUTPUT 0F SPOKEN MESSAGES Filed June 6, 1961 W. K. FRENCH FIG.|

3 Sheets-Sheet 1 OUTPUT CHANNELS A TTORNE Y6 3 Sheets-Sheet 2 W. K. FRENCH SYSTEM FOR MULTIPLE OUTPUT OF SPOKEN MESSAGES Sept. 28, 1965 Filed June 6, 1961 same 25;

Sept. 28, 1965 w. K. FRENCH SYSTEM FOR MULTIPLE OUTPUT OF SPOKEN MESSAGES Filed June 6, 1961 3 Sheets-Sheet 3 l 2E @258 8028525 fi 8E; 02% on QEQ mo mo dill mm o S J 2% m mm mo a Cum 2 & E1; :20 @7223 n. N- E0; 202 w 29mm 2525 V N m o 1 95 52,: 9mm 8! E; 75; mm Tam r mo m 228 mm 6 5%; 052 N k: o P M2: 02% 55% M92 E; 1. ME 525 mm 9 a 08 5 50d m2: 3:55 25 Eza 8\ United States Patent 0 3,209,074 SYSTEM FOR MULTIPLE OUTPUT 0F SPOKEN MESSAGES Walter K. French, Montrose, N.Y., assign-or to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed June 6, 1961, Ser. No. 115,228 6 Claims. (Cl. 179-1) This invention relates to a system for the multiple output of spoken messages and more particularly to such a system in which a plurality of messages is composed from a reservoir of audio words and these message compositions are done simultaneously for a plurality of output message channels whereby each channel may contain an entirely diflFerent message.

Systems are known in which a number of different speech messages are separately stored on diflerent tracks of a constantly rotating drum in which control signals select one of these messages for transmission. Systems are also known in which a plurality of speech sounds are stored on a rotating drum and coded signals are used to synthesize the speech specified by the code. However, this invention is directed to the synchronous sampling of, individual speech sounds stored in individual tracks on a constantly rotating drum so that individual speech messages are composed and gated simultaneously to a plurality of selected output channels. Such is the broad object of this invention.

A further object is to achieve such a system while employing time division multiplexing or switching whereby the quantity of switching equipment is minimal.

These objects as well as others are achieved simultaneously in accordance with the present invention by a system for composing speech messages in a plurality of output channels, said messages being composed of at least one word that comprises means to store words in the form of audio signals at discrete addresses in a word storage device, means to store selected discrete addresses in a word address storage device, means to address said word storage device with said selected discrete adrcsses in accordance with a predetermined time multiplex sequence, means to condition said output channels to receive said words in accordance with said predetermined sequence, means to gate portions of said words as determined by said discrete address to said output channels whereby said predetermined repetitive sequence of addressing and gating results in the composition of said speech messages in said output channel.

Other objects and advantages of the invention will be pointed out in the following description and claims and illustrated in the accompanying drawings, which disclose, by way of example, the principles of the invention and the best mode which has been contemplated of applying these principles.

In the drawings:

FIGURE 1 is a block diagram showing the system constructed in accordance with the present invention; and

FIGURES 2A and 2B comprise a diagrammatic representation of the components of the system constructed in accordance with the present invention.

Referring first to FIGURE 1, a constantly rotating drum has stored thereon in real time a plurality of words in audio signal form. Preferably there is one word per drum track. Each signal starts at the same time location on the drum and the beginning of each of the words is time related to a drum sync pulse preferably stored on a separate sync track. The sync pulse is fed to a computer or the like which responds by sending to the drum register a seven-bit word address which is to designate one of the word tracks on the drum.

The transfer of this first word address to the drum register initiates the operation of the control circuits. These control circuits perform a number of functions. Among these functions are the following: First, the scanner ring is stepped to store each successive word address received by the drum register into the core array. Second, the drum register is reset after each of the word addresses therein has been stored in the core array. Third, after the storage of each of the word addresses in the core array, the computer is ordered to send another word address to the drum register.

Ultimately, a plurality of word addresses is stored in the core array. Now, the stepping of the scanner ring reads out each of the word addresses to the drum register and the contents thereof are decoded by the decoding matrix. This matrix functions to gate a portion of a selected word from the drum to a selected output channel determined by the scanner ring. Output gating circuitry functions to accomplish this. As each word address is read out of the core array to the drum register and is decoded by the matrix, it is also read back into the core array. Repetition of this reading out process with the resultant repetitive sampling of selected words in the form of audio signals on designated drum tracks results in the composition of selected words in audio form in the output channels. Repeated loading and readout of the core array results in multiword messages in these output channels.

It should be noted that the word addresses are read out from the core array in a predetermined repetitive sequence as determined by the scanner ring and its connections to the core array. The scanner ring also establishes this predetermined sequence for conditioning the output channels. For instance, the word addresses in the array may be read out from the first word stored therein to the fiftieth word. As the first address is read out for decoding and addressing of the drum, the first output channel is simultaneously conditioned to receive that portion of the drum word which is so addressed. This portion may come from any one of the tracks on the drum, the particular track being determined by the contents of the drum register being decoded by the decoding matrix at that instant of time. By virtue of this scheme, time multiplexing or switching is achieved. In other words, during the first period of time a portion of the first word for channel 1 is gated to channel 1. During the second period of time, the first portion of the word for channel 2 is gated to channel 2. If there are, for instance, fifty output channels, then during the first fifty periods of time each channel receives the first portion of the first word ultimately to be incorporated into the message for said channel. During the second fifty periods of time, the second portion of each of the words is gated to each of the output channes. By repeating this process the first word in each of the messages for each of the output channels is composed. The second Word for these messages is similarly composed. Ultimately, after a number of these sequences, the entire message for each of the channels is composed.

Referring to FIGURES 2A and 2B, the word drum 10 contains a plurality of tracks thereon. In one particular embodiment there are 128 word tracks and one sync track. Words in the form of audio signals at real time are individually stored on the tracks, one word per track. There are a plurality of output channels which are identified herein from channel 1 to channel 50. By means to be explained, messages composed of a plurality of words selected from the drum tracks are composed and are simultaneously made available at the output channels. For instance, channel 1 may provide message 1, channel 2 may provide message 2, etc. A typical ap plication of this invention is in a stock quotation system. For instance, channel 1 may read out the fact that stock A is presently quoted at 12%. At the same time, channel 2 may readout that stock B is presently quoted at 25 /2. Means not shown may be provided for connecting to any one of the output channels depending upon the stock of interest.

The drum rotates at one revolution per second. Therefore, each word in the 128 tracks is made available once per second. All the audio signals constituting the words start at the same instant of time during the revolution, said time being correlated with the sync pulse in the 129th track. The outputs from the audio tracks on the drum are fed to the audio amplifiers WAl through WA128. There are 128 analog gates which are identified here as word gate 1 (W61) through word gate 128 (WG128). The outputs of all of these gates feed a common bus 11. This bus connects with analog gates associated with each of the output channels and here identified as 12 through 15. Low pass filters 12a-15a are employed to recover the audio signals from a sample data sequence. The use of such filters is conventional and is described in: Radio Telemetry," Second edition, by M. H. Nichols and L. L. Rauch, published by John Wiley & Sons, copyright 1956, with specific reference to chapter 16.

To better understand the operation of the inventive system, said operation has been divided into two parts; namely, (1) loading word memory and (2) readout from word memory.

(1) Loading word memory When the drum sync pulse is received from track 129 of the drum at the output of the pulse amplifier 16, it generates a command which instructs computer 18 to provide seven-bit addresses to be loaded into the word memory. The drum sync pulse also conditions control circuitry to enable the loading process as follows: The drum sync pulse resets flip-flop 1 (FFl), and flip-flop 2 (FF2) and sets flip-flop 3 (FPS). The drum sync pulse through each of the OR gates 19 through 22 associated with the word memory core array 23, resets all of the cores in the word memory core array 23, which is used to store the address words. There is one read and one write driver for each row of cores. This word memory core array is composed of a 7 x 50 array of two-state cores. In this particular instance, the dimensions are determined by the fact that there are 50 output channels to be serviced and the code employed in the system to designate the address Words identifying the respective audio tracks is a seven-bit code. The outputs of the OR gates 19 through 22 feed their associated read drivers, each of which provides full reset current to the associated cores. The set state of fiip-flop 3 de-conditions AND gate 26 so that the AUDIO SAM- PLE LINE is down to inhibit the decoding matrix 36. The drum sync pulse also turns on the RD-l stage of the scanner ring 28.

Now all of the cores in the word memory core array 23 have been reset. Flip-flops 1 and 2 have also been reset and flip-flop 3 has been set. The one megacycle clock 24 which is continuously in operation is supplying its output pulses to gate 25 but gate 25 is blocked because fiip-flop 1 is reset.

The drum sync pulse generates the signal START WORD TRANSFER in the computer which responds by sending the first seven-bit word into drum register 27. This computer word is not to be confused with the audio words on the drum. The computer supplied word is actually a drum track address. The first computer word is now in register 27.

FF3 provides the signal READ INHIBIT LEVEL. While the line READ INHIBIT LEVEL is up during loading of word memory, all sense amplifiers 41-47 are inhibited by this signal through OR gate 50.

At the time that this first computer word is transferred from the computer to register 27, the line COM- PUTER LOADS DRUM REGISTER goes up to set fiipflop 1 to unblock gate 25. The unblocking of gate allows clock pulses from generator 24 to pass to the control circuitry. This gate supplies a scanner ring stepping pulse to the scanner ring 28. The first stage of the scanner ring is identified as RD-l or read 1. It has been turned on by the drum sync pulse. Therefore, the first pulse from the clock 24 through gate 25 to the scanner ring steps the scanner ring to the WRT-1 (write 1) stage. This same first pulse will flip the flip-flop 2, through the complement input, to its set state to generate the first WRT PULSE. The set state of FFZ conditions gate 37. The turning on of WRT-1 stage in the scanner ring provides through the write driver associated therewith a one-half select current through the first row of cores. At the same time, the information stored in the seven-bit drum register 27 supplies one-half select current to selected columns of cores through the corresponding write drivers 29-35. The first WRT PULSE makes this possible since it is supplied in parallel to all of these write drivers 29 through to condition these write drivers. The first row of cores then receives the contents of register 27; that is, the first word transferred from the computer. This Write cycle requires one microsecond. The line AUDIO SAMPLE from AND gate 26 is down and therefore inhibits the decoding matrix 36 so that the contents of the register 27 do not affect said matrix and the analog gates connected to the output of said matrix.

The second clock pulse through gate 25 passes through gate 37 which is conditioned by the set state of FF2. Thi second pulse is fed to the complementing input of FFZ and resets FFZ but not before said second pulse gets through gate 37 to delay unit 38. This unit emits DRUM REGISTER RESET pulse shortly thereafter to reset register 27 through OR gate 39. The pulse output from OR gate 39 also passes through AND gate 40, conditioned by READ INHIBIT LEVEL, to supply the computer the signal WORD DEMAND. This causes the computer to transfer the second computer word to register 27. The second clock pulse steps the scanner ring to RD-2. The third clock pulse accomplishes the same as the first clock pulse with respect to said second computer word.

This process continues repetitively and the scanner ring is continuously stepped in this manner until the last thereof, namely, WRT50, is turned on. At this time the final word from the computer, the fiftieth word in this case, is stored in the last row of cores in the array 23.

(2) Readout from word memory The turning on of stage WRT- generates the signal WRT-50 which is fed to ilip-fiop 3 to reset said flip-flop to unblock AND gate 26. This occurs on the th micro-second pulse. The resetting of llip-ilop 3 brings down the line READ INHIBIT LEVEL. This line through OR gate 50, controls the operation of the output sense amplifiers 4l 47 associated with the array 23, to inhibit these amplifiers during loading of the array 23 when it is up. The next pulse (the 101st) that is fed to the scanner ring returns the ring to the RD-l stage. This supplies full reset current to the row 1 cores and these cores are thereby read out through the sense amplifiers 41 through 47, inclusive, and word 1 address stored in register 27. The 102ml pulse to scanner ring 28 steps the ring to WRT-L AND gate 26 being conditioned by fliptlop 3 in its reset state now passes this l02nd pulse to provide the first AUDIO SAMPLE pulse to the matrix 36. This sample pulse will permit the contents of register 27 to raise one of the lines at the output thereof, said line continuing in this state for the duration of the AUDIO SAMPLE pulse. Let us assume that it raises line 48. This then will condition word gate 1 (WGI) which is associated with the output of word amplifier l (WAI) which in turn is ussociatcd with the audio word stored in truck I of the word drum 10. The conditioning of word gate 1 by raising of output line 48 from matrix 36 will gate to the bus 11 a portion of the audio signal on track 1. It will suppy this portion to all of the gates 12 through 15, inclusive, for the 50 output channels. However, only AND 12 is conditioned by the WRT-1 pulse and this gate passes the audio sample to channel 1. The WRT-1 pulse laso writes the address in drum register 27 back into row 1 of the word memory 23. During this rewriting, the sense amplifiers 41-47 are inhibited by the WRT pulse applied to the sense amplifier through OR gate 50.

The scanner ring 28 continues to step through its stages, each of which controls the transfer of an address from word memory to drum register, the conditioning of one of the audio gates WGl-WG128, the conditioning of one of the analog gates l2-15 and the subsequent rewriting of the address back into the word memory. After stepping through the WRT50 stage, the ring steps to the RD1 stage and the cycle, which occupies 100 micro-seconds, is repeated.

This process of reading out from the core array to the register 27 and then decoding by the matrix 36 continues for one complete revolution of the word drum. At the end of this complete revolution the first word of a message has been supplied to each of the output channels, and of course these first words may be entirely different and usually are in a stock quotation system. During the construction of each word in the output channels, the audio tracks associated with each of the output channels are sampled once each 100 micro-seconds. If it is considered that the drum rotates once each second, then that means that each audio signal is sampled ten thousand times. Therefore, the reproduction of the signals on the track is quite complete.

When the drum has completed one revolution, the audio reproduction of the words on each of the output channels is complete and the occurrence of the drum sync pulse signals the computer that another group of 50 words to be read out on each of the output channels should be loaded into the word memory. Upon occurrence of the drum sync pulse, the loading process described previously is repeated until the entire message for each channel has been completely composed. Said messages may be repeated, changed, or staggered as desired.

In some cases a word of considerable length may be called for, i.e., one which can not be stored completely on one drum track. In this event, the first part of the word is stored on one track and the remaining part or parts on other tracks. These other tracks may or may not have other words or parts thereof stored thereon. The system can be programmed so that during one revolution the first part of this long word is read out and then during successive revolutions the remaining part or parts are read out.

Also all messages need not be started at the same time. Some may start at the first revolution and others at selected succeeding revolutions. Programming of the system accommodates this procedure.

While there have been shown and described and pointed out the fundamental novel features of the invention as applied to the preferred embodiment, it will be understood that various omissions and substitutions and changes in the form and details of the device illustrated and in its operation may be made by those skilled in the art without departing from the spirit of the invention. It is the intention, therefore, to be limited only as indicated by the scope of the following claims.

What is claimed is:

1. A system for simultaneously composing speech messages in a plurality of output channels, said messages being composed of at least one word, said system comprising word storage means for concurrently storing a plurality of words in the form of audio signals at discrete addresses, address storage means to store concurrently a series of selected discrete addresses; output channel gating mean to condition said output channels in accordance with a repeated time multiplex sequence, to receive portions of said audio signals, the time duration of one such multiplex sequence being a small fraction of the time required to read out the audio signal stored at any one of said addresses; and means including said word address storage means operating synchronously with said time multiplex sequence to gate portions of the audio signals stored at said series of selected addresses individually and sequentially to said output channel gating means; whereby said predetermined repetitive sequence of addressing and gating results in the composition of said speech messages in each of said output channels.

2. The system recited in claim 1 wherein the word storage device is a rotating magnetic drum, said audio signals being stored in discrete tracks on said drum, and means to read the audio signals stored in each of said discrete tracks and to transmit said signals to said output channel gating means.

3. The system recited in claim 1 and an external source of addresses specifying words composing the speech messages for said plurality of output channels.

4. The system recited in claim 3 wherein said address storage means is a magnetic core memory, means for transferring a plurality of addresses from said external source of addresses to said magnetic core memory, each of said addresses specifying a word to be transmitted on a particular one of said plurality of output channels, and means to repetitively read each of said addresses out of said magnetic core memory and to repetitively restore each of said read out addresses into said magnetic core memory in accordance with said predetermined time multiplex sequence, said means to address said Word storage means being enabled by said read out addresses.

5. A system for simultaneously composing speech mes sages in a plurality of output channels, said messages being composed of at least one word, said system comprising an external source of addresses, each of said addresses specifying a particular word to be transmitted on corresponding ones of said output channels, a magnetic drum having a plurality of drum tracks, means for storing word in the form of audio signals in discrete tracks of said magnetic drum, a word address storage device, means to transfer a plurality of addresses from said external source of addresses to said word address storage device, means operating subsequently to the transfer of said plurality of addresses for sequentially and repetitively reading said addresses out of said word storage device in accordance with a predetermined time multiplex sequence, means to condition said output channels sequentially to receive said words in the form of audio signals in accordance with said predetermined sequence, and means to gate portions of said audio signals from said drum tracks to said output channels during each multiplex sequence, said last named means being enabled by the addresses read out of said word address storage device.

6. The system recited in claim 5 wherein said word address storage device includes a magnetic core memory and said means for selectively and repetitively reading said addresses out of said memory includes a scanner ring, said scanner ring being connected to said magnetic core memory so as to selectively address different groups of said cores in said memory.

References Cited by the Examiner UNITED STATES PATENTS ROBERT H. ROSE, Primary Examiner. L. MILLER ANDRUS, Examiner.

Claims (1)

1. A SYSTEM FOR SIMULTANEOUSLU COMPOSING SPEECH MESSAGES IN A PLURALITY OF OUTPUT CHANNELS, SAID MESSAGES BEING COMPOSED OF AT LEAST ONE WORD, SAID SYSTEM COMPRISING WORD STORAGE MEANS FOR CONCURRENTLY STORING A PLURALITY OF WORDS IN THEW FORM OF AUDIO SIGNALS AT DISCRETE ADDRESSES, ADDRESS STORAGE MEANS TO STORE CONCURRENTLY A SERIES OF SELECTED DISCRETE ADDRESSES; OUTPUT CHANNEL GATING MEANS TO CONDITION SAID OUTPUT CHANNELS IS ACCORDANCE WITH A REPEATED TIME MULTIPLEX SEQUENCE, TO RECEIVE PORTIONS OF SAID AUDIO SIGNALS, THE TIME DURATION OF ONE SUCH MULTIPLEX SEQUENCE BEING A SMALL FRACTION OF THE TIME REQUIRED TO READ OUT THE AUDIO SIGNAL STORED AT ANY ONE OF SAID ADDRESSES; AND MEANS INCLUDING SAID WORD ADDRESS STORAGE MEANS OPERATING SYNCHRONOUSLY WITH SAID TIME MULTIPLEX SEQUENCE TO GATE PORTIONS OF THE AUDIO SIGNALS STORED AT SAID SERIES OF SELECTED ADDRESSES INDIVIDUALLY AND SEQUENTIALLY TO SAID OUTPUT CHANNEL GATING MEANS; WHEREBY SAID PREDETERMINED REPETITIVE SEQUENCE OF ADDRESSING AND GATING RESULT IN THE COMPOSITION OF SAID SPEECH MESSAGES IN EACH OF SAID OUTPUT CHANNELS.
US3209074A 1961-06-06 1961-06-06 System for multiple output of spoken messages Expired - Lifetime US3209074A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US3209074A US3209074A (en) 1961-06-06 1961-06-06 System for multiple output of spoken messages

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US3209074A US3209074A (en) 1961-06-06 1961-06-06 System for multiple output of spoken messages
GB2075362A GB977917A (en) 1961-06-06 1962-05-30 System for multiple output of spoken messages
DE1962J0021893 DE1233177B (en) 1961-06-06 1962-06-05 Data output device for a data processing Geraet

Publications (1)

Publication Number Publication Date
US3209074A true US3209074A (en) 1965-09-28

Family

ID=22360051

Family Applications (1)

Application Number Title Priority Date Filing Date
US3209074A Expired - Lifetime US3209074A (en) 1961-06-06 1961-06-06 System for multiple output of spoken messages

Country Status (3)

Country Link
US (1) US3209074A (en)
DE (1) DE1233177B (en)
GB (1) GB977917A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3296371A (en) * 1963-03-18 1967-01-03 Burroughs Corp Voice encoder
US3337847A (en) * 1963-09-17 1967-08-22 North Electric Co Communication system for connecting subscribers to a multiplex message synthesizing system
US3662115A (en) * 1970-02-07 1972-05-09 Nippon Telegraph & Telephone Audio response apparatus using partial autocorrelation techniques
US3810106A (en) * 1972-10-05 1974-05-07 Apm Corp System for storing tone patterns for audible retrieval
US3990050A (en) * 1974-09-25 1976-11-02 Bell Telephone Laboratories, Incorporated Computer controlled automatic response system
US4016540A (en) * 1970-12-28 1977-04-05 Gilbert Peter Hyatt Apparatus and method for providing interactive audio communication
US4068099A (en) * 1975-06-13 1978-01-10 Telefonaktiebolaget L M Ericsson Method of and apparatus for switching service information units in a TDM system
US4352956A (en) * 1977-09-02 1982-10-05 Pierre Gallet G Multi-responder telephone intercept apparatus
US4686622A (en) * 1970-12-28 1987-08-11 Hyatt Gilbert P Computer system architecture using serial communication
US4825364A (en) * 1970-12-28 1989-04-25 Hyatt Gilbert P Monolithic data processor with memory refresh
US4829419A (en) * 1970-12-28 1989-05-09 Hyatt Gilbert P Microcomputer control of machines
US4896260A (en) * 1970-12-28 1990-01-23 Hyatt Gilbert P Data processor having integrated circuit memory refresh
US5440637A (en) * 1990-11-27 1995-08-08 Vanfleet; Earl E. Listening and display unit
US5594908A (en) * 1989-12-27 1997-01-14 Hyatt; Gilbert P. Computer system having a serial keyboard, a serial display, and a dynamic memory with memory refresh
US5615380A (en) * 1969-11-24 1997-03-25 Hyatt; Gilbert P. Integrated circuit computer system having a keyboard input and a sound output

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2885659A (en) * 1954-09-22 1959-05-05 Rca Corp Electronic library system
US2935569A (en) * 1957-09-26 1960-05-03 Bell Telephone Labor Inc Time assignment speech interpolation system
US2946044A (en) * 1954-08-09 1960-07-19 Gen Electric Signal processing system
US2959351A (en) * 1955-11-02 1960-11-08 Ibm Data storage and processing machine
US2961492A (en) * 1957-09-26 1960-11-22 Bell Telephone Labor Inc Elastic multiplex speech interpolation system
US3016527A (en) * 1958-09-04 1962-01-09 Bell Telephone Labor Inc Apparatus for utilizing variable length alphabetized codes
US3055983A (en) * 1957-01-23 1962-09-25 British Telecomm Res Ltd Telephone or like systems
US3133268A (en) * 1959-03-09 1964-05-12 Teleregister Corp Revisable data storage and rapid answer back system

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2946044A (en) * 1954-08-09 1960-07-19 Gen Electric Signal processing system
US2885659A (en) * 1954-09-22 1959-05-05 Rca Corp Electronic library system
US2959351A (en) * 1955-11-02 1960-11-08 Ibm Data storage and processing machine
US3055983A (en) * 1957-01-23 1962-09-25 British Telecomm Res Ltd Telephone or like systems
US2935569A (en) * 1957-09-26 1960-05-03 Bell Telephone Labor Inc Time assignment speech interpolation system
US2961492A (en) * 1957-09-26 1960-11-22 Bell Telephone Labor Inc Elastic multiplex speech interpolation system
US3016527A (en) * 1958-09-04 1962-01-09 Bell Telephone Labor Inc Apparatus for utilizing variable length alphabetized codes
US3133268A (en) * 1959-03-09 1964-05-12 Teleregister Corp Revisable data storage and rapid answer back system

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3296371A (en) * 1963-03-18 1967-01-03 Burroughs Corp Voice encoder
US3337847A (en) * 1963-09-17 1967-08-22 North Electric Co Communication system for connecting subscribers to a multiplex message synthesizing system
US5615380A (en) * 1969-11-24 1997-03-25 Hyatt; Gilbert P. Integrated circuit computer system having a keyboard input and a sound output
US3662115A (en) * 1970-02-07 1972-05-09 Nippon Telegraph & Telephone Audio response apparatus using partial autocorrelation techniques
US4825364A (en) * 1970-12-28 1989-04-25 Hyatt Gilbert P Monolithic data processor with memory refresh
US4829419A (en) * 1970-12-28 1989-05-09 Hyatt Gilbert P Microcomputer control of machines
US4016540A (en) * 1970-12-28 1977-04-05 Gilbert Peter Hyatt Apparatus and method for providing interactive audio communication
US4686622A (en) * 1970-12-28 1987-08-11 Hyatt Gilbert P Computer system architecture using serial communication
US4896260A (en) * 1970-12-28 1990-01-23 Hyatt Gilbert P Data processor having integrated circuit memory refresh
US3810106A (en) * 1972-10-05 1974-05-07 Apm Corp System for storing tone patterns for audible retrieval
US3990050A (en) * 1974-09-25 1976-11-02 Bell Telephone Laboratories, Incorporated Computer controlled automatic response system
US4068099A (en) * 1975-06-13 1978-01-10 Telefonaktiebolaget L M Ericsson Method of and apparatus for switching service information units in a TDM system
US4352956A (en) * 1977-09-02 1982-10-05 Pierre Gallet G Multi-responder telephone intercept apparatus
US5594908A (en) * 1989-12-27 1997-01-14 Hyatt; Gilbert P. Computer system having a serial keyboard, a serial display, and a dynamic memory with memory refresh
US5440637A (en) * 1990-11-27 1995-08-08 Vanfleet; Earl E. Listening and display unit

Also Published As

Publication number Publication date Type
GB977917A (en) 1964-12-16 application
DE1233177B (en) 1967-01-26 application

Similar Documents

Publication Publication Date Title
US3648255A (en) Auxiliary storage apparatus
US3343141A (en) Bypassing of processor sequence controls for diagnostic tests
US3377619A (en) Data multiplexing system
US5648929A (en) Flash memory card
US4298954A (en) Alternating data buffers when one buffer is empty and another buffer is variably full of data
US4145739A (en) Distributed data processing system
US4879551A (en) Switching array with concurrent marking capability
US4719601A (en) Column redundancy for two port random access memory
US4646270A (en) Video graphic dynamic RAM
US5040153A (en) Addressing multiple types of memory devices
US4750149A (en) Programmable FIFO buffer
US5365489A (en) Dual port video random access memory with block write capability
US4694394A (en) Microprocessor system having a multiplexed address/data bus which communicates with a plurality of memory and input/output devices including TTL output gates
US6525952B2 (en) Recording system, data recording apparatus, memory apparatus, and data recording method
US7111143B2 (en) Burst mode implementation in a memory device
US6542956B1 (en) Latched address multi-chunk write to EEPROM
US6272052B1 (en) Block-erase type semiconductor storage device with independent memory groups having sequential logical addresses
US5933385A (en) System and method for a flexible memory controller
US4040026A (en) Channel for exchanging information between a computer and rapid peripheral units
US3082406A (en) Decoding device
US4611299A (en) Monolithic storage device
US4204252A (en) Writeable control store for use in a data processing system
US5406527A (en) Partial write transferable multiport memory
US3623022A (en) Multiplexing system for interleaving operations of a processing unit
US6252807B1 (en) Memory device with reduced power consumption when byte-unit accessed