US3189883A

US3189883A - Test and reset circuit for intrusion alarm system

Info

Publication number: US3189883A
Application number: US160116A
Authority: US
Inventors: Raymond D Lucas; George C Byrne; John C Mcdonald
Original assignee: Sylvania Electric Products Inc
Current assignee: GTE Sylvania Inc
Priority date: 1961-12-18
Filing date: 1961-12-18
Publication date: 1965-06-15
Anticipated expiration: 1982-06-15

Description

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June 15, 1965 R. n.1.ucAs ETAL 3,189,833

TEST AND RESET CIRCUIT FOR INTRUSION ALARM SYSTEM Filed Dec. 18, 1961 RAYMOND D, LUCAS GEORGE C. BYRNE JOHN C. McDONALD BY @ffm/@E ATTORNEY United States Patent O 3,189,883 TEST AND RESET CRCUT FOR INTRUSION ALARM SYSTEM Raymond D. Lucas and George C. Byrne, Mountain View,

and John C. McDonald, Los Altos, Calif., assignors to Sylvania Electric Products Inc., a corporation of Delaware Filed Dec. 18,1961, Ser. No. 160,116 8 Claims. (Cl. 340-214) This invention relates to intrusion alarm systems, and more particularly t-o a reset and test circuit which enables such a system to be returned to its readiness or reset state after it has been alarmed and which provides a system operativeness check by artificially simulating an unauthorized intrusion.

Intrusion alarm systems of the type described in Patent Number 2,660,718 protect a specific area by beaming microwave energy into the area and by processing signals from the area in a microwave receiver so as to sound or otherwise indicate an alarm when an intruder is present. Such systems usually are monitored at a central station which is remote from the protected area. When an alarm is sounded and after its cause has been investigated at the protected area, the guard should be able promptly to reset the system, i.e., return it to its readiness state. In order to permit the guard to reset the receiver and leave the protected area without alarming the system, a relatively long delay (i.e., 1 minute) should be provided between the time the guard initiates the reset operation and the time the system is again in its readiness state.

Allied to this resetting function is a built-in circuit capable of testing itself to determine if its components, connections and networks are operating properly. This is done by deliberately injecting into the circuit a signal similar to that produced by an intruder. lf the system is functioning properly, the alarm is sounded automatically. The test circuit should then promptly turn off the alarm and return the system to its readiness state. For this purpose, a short time delay (10 seconds) is desirable.

A general object of this invention is the provision of a test and reset circuit which incorporates the above features.

This and other objects of the invention will become apparent from the following description of ya preferred embodiment thereof reference being had to the accompanying drawing showing an intrusion alarm system with a block and circuit diagram of the test and reset circuit.

Referring to the drawing, the area A to be protected lies between antennas 1 and 2, connected respectively to a continuous wave radio frequency transmitter 3 and a receiver 4. Movement of an object in area A produces a Doppler shift in the frequencyl of the received waves whichappears in the output of the receiver on lines 5, 5 and is detected in discriminating circuits 6, 6'. Two circuits y6 and `6' are provided for improving reliability through redundancy and it is lthe function of each to discriminate between suprious and intruder signals on the basis of the Doppler frequency shift, the magnitude of the signaland the persistence (time integral) of the signal. The discriminator circuits 6 and 6 may be of the type described in copending application on Signal Processing Circuit For Intrusion Alarm System, by John C. McDonald, Serial No. 200,019J tiled May 31, 1962, and assigned to the assignee of this application or the types described and referenced in Coincidence Techniques for Radar Receivers Employing a Double Threshold Method of Detection, by E.,Endresen and R. Hedemark, page 1561, volume 49, Proceedings of the IRE, No. 10, October 1961.

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The outputs of discriminating circuits 6 and 6 on lines, 7, 7' pass to an OR gate 10 which responds to the output of either to cause an alarm relay 11 to actuate an alarm mechanism 12 such as a bell or light. Relay 11 preferably is normally energized, and produces an output to activate alarm 12 when the relay is de-energized.

Receiver 4 also produces a direct current output on line 14 in response to reception of the continuous wave by antenna 2, and this D C. component is applied to the OR gate 10 which keeps relay 11 energized. If this D.C. output of the receiver falls below a certain level, which is indicative of malfunctioning of any of the componen-ts from the transmitter 1 to receive 4, the alarm is given.

In order to test operability of the intrusion alarm system described above, a test circuit is provided by which a signal representing an intruder is deliberately injected in the system. If alarm 12 is actuated, as it should be, the test circuit should then reset the entire system automatically in a relatively short time, say l0 seconds.

The test circuit comprises a signal generator 20 having a push button 21 by which the guard or operator initiates the test cycle. This generator may comprise a blocking oscillator capable lof producing a pulse on output lines 22 and 23 when push button 21 is depressed, and a source of unidirectional potential which normally produces on a third output line 2S a positive Voltage which is changed to a negative voltage when push button 21 is depressed. The pulse on line 22 is applied to receiver 4 and is of such character that it appears as an intruder signal so as to cause alarm device 12 to function if all of the intervening circuits are operating properly, or conversely, to indicate a malfunction if the alarm does not respond. lf either `of the redundant discriminator circuits 6 |or 6' is faulty, the alarm is given but the system will not reset. This indicates that one of the circuits 6 or 6 is defective. The circuits by which this is accomplished are explained more fully below.

Output line 23 of the test generator is connected to a triple input AND gate 26 as are

output lines

27 and 27 from discriminator units 6 and 6', respectively. As the output 'of gate 26 initiates the system reset cycle both discriminator circuits must be operating properly in order that resetting take place. Gate 26 is connected by line 28 to a bi-stable multivibrator or ip-flop 30 which is actuated (set) in response to an output from the gate. A push button 31 preferably located at or near protected area A and electrically connected to flip-flop circuit 30 as indicated by broken line 32 also actuates the flip-flop when depressed.

Flip-flop circuit 30 is connected by line 33 to a time delay network 35 the output of which appears at line 36 and is applied to a trigger amplifier 37. This delay network, described below, produces a long delay (approximately 1 minute) for signals applied to it by actuation of push button 31, and a short delay (approximately 10 seconds) for signals produced by depressing button 21 on generator 20. Trigger amplifier 37 is connected by line 38 to a normally open reset relay 39 and produces an output of suiiicient amplitude to operate the latter. Relay 39 may comprise a coil 40 and

contacts

41 and 42 which, when closed, connect a source of energy 43 to

relay outputs

44 and 45. As long as there is an input on line 36 to amplifier 37, the latter continues to conduct and relay 39 operates to close its contacts. When the input to amplifier 37 is removed, its output on line 38 drops and relay 39 opens.

Delay network 35 comprises a normally conducting gate transistor 50 connected in parallel with an amplifier transistor 51, and a delay control transistor 52. Amplifier transistor 51 is normally non-conducting and has a trigger amplifier 37 to operate.

occurrence, of the pulse from flip-flop 30 until triggerV "amplifier 37 operates is determined by the RC time constant of the charging network which is essentially con- Transistor 51, capacitor 53, and-resistors 60 and 61 are connected tofunction as a Miller integrator circuit as dejscribed in Waveforms, volume 19, pages`278-284jof Radiation Laboratories Series (McGraw-Hill, 1949). Delay control transistor 52 'is normally non-conducting,

e is connected in parallel with base bias resistor 60 and 'has its base 66 connected to the D.C. output of a test rsignal generator 20 throughline 25.

aisasss Prior to initiation ofthe resetting cycle, with transistor 51 not conducting and transistor-50 conducting, the charge on capacitorr53 is negligible and potential at the output 36 is slightly below ground potential. .When transistor 50 is cut-'off bythe output of fiip-iiop 30, transistor 51 vconducts and capacitor 53 begins to charge negatively through resistor 60 and base 55 of amplifier 51. The potential at 36 goes sufficiently negative to cause The time between the trolled by the gain of amplifier 51. The time in this instance is approximately one minute.

When caused to conduct by testgenerator 20, 'tran- Vsistor 52 operates to shorten the charging time of capacitor 53 by short-circuiting base resistor 60. b l s g Resetaction ofthe alarmed intrusion detection system is Vinitiated by actuating test button31 which triggersV Vbi-stable fiip-fiop 30 and applies @Positive potential to AAbasev49 of normally conducting transistor 50 which is saturated duringA stand-by operation. This reverse biases andcuts off transistor S0 causing the potential on collector'. of transistor amplifier 51 to fall toward Vthe nega- Mtive supply potential V, i.e., in the direction to turn vamplifier 51 on hard. The VVaction of capacit-or 53 causes ,amplier 51 to conduct at a linear rate and capacitor 53 to charge through basebias resistor 60 at a linear rate.

-Y During this charging phase, delay control transistor 52 is .reverseV biased and is non-conducting. Y

When the charge across capacitor l53 reaches a predetermined level, `-V, trigger amplifier 37 is forward Ybia-sed and conducts. The output of amplifier 37 venerg'izesV coil 4t) ofreset relay 39 to close its contacts and `connect source l43 to generator 20 andto alarm relay 11 Viiop V30V to vreset it. Until flip-flop 30 is thus reset, push button 31 has no effect on it.

Resetting of flip-flop 30 causes transistor n5t) to again conduct and saturate. The potential on collector 56 of `'amplifierSl becomes less negative and causes the latter `to cut-ofi. "Capacitor 53 discharges rapidly through transistor 50, andthe output at line 36 becomes less negative resetfrelay 39 and the resetting cycle is complete. Alarm lrelay 11 has atypical hold-in ooil arrangement so that it remains-energized after the input to it on line 44 is removed...

.In order to test system operation, test button 21 of test Ygenerator 20 is depressed. This sends a simulated intruder, signal to receiver 4 via line 22, and causes alarm 'device 12 to be activated if the intervening circuits are functioning properly. The outputs from discriminator respectively, to AND gate 26 to'condition the latter vfor j enabling resetting action. lf either circuit 6 or 6" is not functioning'properly AND `gate 26 will prevent reset action taking place.

where (i0` luntiltrigger amplifier 37 is cut-ofi?. This de-energizes Y 701Y `circuits`6 and 6 are also -applied via lines 27 and l27',

negative to positive. transistor 52 to cut it off. Reset relay 39 also *resets ialarm'relay 11 in the same manner as described above 'Another output from generator 2) is a negative pulse fed through line 25 to forward bias base 66 of delay controlV transistor 52. This transistor is Ymaintained non-conducting, however, due to the reverse Abias potential between its collector 67 and emitter 68.

A third output fromtest generator-20, Yis fed through line 23 to AND gate 276. When a trigger pulse from generator 2t)y and both discriminator circuits 6 and 6 are yreceived simultaneously, AND gate 26 `triggers bi-stable -flip-flop 3f) andlinitiate's a cycle similar to the reset cycle described above. Briefly, the fiip-iiop 3,0 applies a positive potential to base 49 of transistor 5t?, causing it to cut-off. Amplifier51 tries to turn on hard as the potential on collector 56 falls toward the negativesupply potential. Due to v4the action of vcapacitor 53, the potential on base 55 of transistor 51 becomes negative and forward biases collector 67 of delay control transistor -sothe latternow conducts. `,Delay control transistor 52 saturates and essentiallyl short-circuits base Vbias resistor 60, removing it from the circuit. When'capacitor 53 charges to a predetermined voltage trigger amplifier 37 trigger amplifier 37 fires, i.e., the potential to which capacitor SSVchar-lges is lmuch less thane'the supply voltage -V, the rate at which capacitor 53 charges is approximately v fr `1 m VRM1-FA)Cnn-bca@ RLisY the amplifier load resistance 6 2,

.Cfb is the capacitance of capacitor53,

A is the effective-gain of amplifier 51,

Cbelis the straycapacitance between the base and emitter of amplifier 51, and `-V is the'negative supplypotential y yWhen' the currentV gain i.e., the rate of change of ance 61, the effective gain A of amplifier-51 is approximately equal tok this ratio. rl`jhus, a` decrease in base `bias resistance 60, due to jconduction` Vof delay control :transistor 52,-causes the effective gain of amplifier 51 to decrease and capacitor 53 to charge much more rapidly than during the reset cycle previously described. The 'difference in charge `ti'meof capacitor 53 during reset and system test preferably is approximately 50 seconds.

The outputof trigger amplifier 37 energizes reset relay 39 which produces an output on line 45 to test generator 20 whose output at line 2S is thereby switched from This reverse biases delay control in connection with the "system resetting operation.

What is claimed is: 1.- Intrusion alarm apparatus rcomprising 'microwave receiver means responsive to an intruder signal for producing an output,

an alarmrelay having first and `second operating states, `said relay being responsive to the output of the receiver meanstov change from the first to the second state, Y

alarm when the relay is in said second state; and

a'system testjcircuit comprising a test generator for Y :producing a simulated intruder signal and having first, second andvthird outputs,

thefirst output of said generator being connected `to -said receiver meansl Vfor actuating -said alarm relay and said 'alarrn^device,

anjANDfgate having a first input Vconnected to the output of the receiver means and a second input connected to the second output of said generator,

an alarm device connected to said relay to give an fris nu@ E,

a bi-stable flip-nop connected to the output of said AND gate and having first and second operating states,

said fiip-iiop being responsive to the output of the AND gate to change from the first to the second operating state,

a delay network having a first input connected to the output of said Hip-flop and a second input connected to the third output of the test generator,

said network being responsive to the output of said generator and to the output of said flip-flop in its -second operating state for producing an output after a predetermined time delay,

said alarm relay being responsive to the output of said delay network for changing from said second to said rst operating state to de-activate said alarm device,

and means for resetting said fiip-iiop to its first operating state in response to change of the alarm relay to its first operating state.

2. Apparatus according to claim 1 in which said delay network comprises first and second transistors having collectors connected to the network output,

said first transistor having its base connected to the output of said flip-flop, a capacitor connected between the collector and base of said second transistor,

.a resistor connected between the base and emitter of said second transistor,

and means responsive to said third output of the generator for selectively shorting out said resistor whereby to shorten the charging time of said capacitor.

3. In combination,

intrusion alarm apparatus responsive to condition for giving an alarm,

a test and reset circuit comprising a test generator having first, second and third outputs,

means to actuate said generator to generate signals at said three outputs,

the first output being connected to said apparatus to simulate the condition and give the alarm,

an AND gate having an output and having a first input connected to an output of said apparatus and .a second input connected to the second output of the generator,

a bi-stable flip-Hop having an input connected to the output of said AND gate and having an output,

and a delay network having a first input connected to the output of said flip-fiop and a second input connected to the third output of said generator,

said network having an output connected to said apparatus for resetting same a predetermined time after said test generator is actuated,

and means connecting said fiip-op to said apparatus for resetting the Hip-nop simultaneously with the alarm apparatus.

d. Intrusion alarm apparatus comprising microwave receiver means responsive to an intruder signal for producing an output,

an alarm relay having first and second operating states, said relay being responsive to the output of the receiver means to change from the first to the second state,

an alarm device connected to said relay to give an alarm when the relay is in said second state; and

a system test circuit comprising a test generator for producing a simulated intruder signal and having first and second outputs,

the first output of said generator being connected to said receiver means for actuating said alarm relay and said alarm device,

an AND gate having a first input connected to the output of the receiver means and a second input connected to the second output of said generator,

a bi-stable circuit connected to the output of said AND gate and having first and second operating states,

said bi-stable circuit responsive to the output of the AND gate to change from the first to the second operating state,

a delay network having input connected to the output of said bi-stable circuit,

said network being responsive to the output of said bi-stable circuit when in the second operating state for producing an output after a predetermined time delay, said alarmrelay being responsive to the output of said delay network for changing from said second to said rst operating state to de-activate said alarm device,

and means for resetting said bistable circuit to its first operating state in response to change of the alarm relay to its first operating state.

5. Intrusion .alarm apparatus comprising receiver means responsive to an intruder signal for producing van output,

an alarm relay having rst and second operating states, said relay being responsive to the output of the receiver means to change from the first to the second state,

a system test and reset circuit comprising a test generator for producing a simulated intruder signal and having first, second and third outputs,

a bi-stable Hip-flop connected to the output of said AND gate,

said flip-fiop being responsive to the output ofthe AND gate to produce an output,

manual reset means connected to said flip-flop and operative independently to produce an output from the tiip-fiop,

a time delay network having input connected to the output of said fiip-iiop and another input connected to the third output of the test generator,

said network being responsive to the output of said generator and to the output of said flip-flop for producing an ouput after a first time delay and being responsive to the output only of said flip-flop for producing an output from the network after a second time delay greater than the first delay,

said alarm relay being responsive to the output of said delay network for changing from said second to said first operating state to de-activate said alarm device,

and means for resetting said flipfiop in response to change of the alarm relay to its first operating state.

6. Intrusion alarm apparatus comprising microwave receiver means responsive to an intruder signal for producing an output,

a system reset circuit comprising a bi-stable flip-flop having first and second operating states,

manual means associated with said tlip-fiop and operative to change same from the first to the second operating state,

a delay network having input connected to the output of' said Hip-flop,

said network being responsive to the output of said 'Hob Whenin lha second Operating state fof roducing an 'output after a predetermined time delay, y said alarmV` relay being responsive to the output ofV said delay netvvork for changing from Vsaid second `fr giving an alarrnl ,a testlsignal generator having rst and second outputs,

means 'for selectively actuating said generator to pro- Y, duce signals atsaid outputs,4 and vcircuit means for resetting said apparatus, l' s Y said circuit means having an output connected to said apparatus and having a lirst input connected to the second output of saidge'nerator and a second input connected to `said apparatus, s Y said apparatus being responsive to a signal on the first l'output Aof said generator to give an alarm,

-said circuit means being responsive to the signal on Ysaid circuit means independently of said generator to pro- V y`duce a signal on the output 'of said circuit means for resetting saideapparatus.

References Cited by the Examiner UNITED STATES `PATENTS 2,732,544 1/56 'Bagno v 340-214 2,845,547 7/58 Althouse Y Y v 307-885 .2,845,548 7/58 siuiman et Va1 307-885 '3,022,496 2/62 Bagno s V340-214 `NETL C; READ, Prinmry Examiner. Y

KMHLEENH.V CLAEEY, CHESTER L., JUSTUS,

y l Y Examiners.

Claims

3. IN COMBINATION, INTRUSION ALARM APPARATUS RESPONSIVE TO CONDITION FOR GIVING AN ALARM, A TEST AND RESET CIRCUIT COMPRISING A TEST GENERATOR HAVING FIRST, SECOND AND THIRD OUTPUTS, MEANS TO ACTUATE SAID GENERATOR TO GENERATE SIGNALS AT SAID THREE OUTPUTS, THE FIRST OUTPUT BEING CONNECTED TO SAID APPARATUS TO SIMULATE THE CONDITION AND GIVE THE ALARM, AN AND GATE HAVING AN OUTPUT AND HAVING A FIRST INPUT CONNECTED TO AN OUTPUT OF SAID APPARATUS AND A SECOND INPUT CONNECTED TO THE SECOND OUTPUT OF THE GENERATOR,