US3125744A

US3125744A - Stage

Info

Publication number: US3125744A
Authority: US
Publication date: 1964-03-17
Anticipated expiration: 1981-03-17

Description

March 17; 1964 E. oLsoN 3,125,744,

MAGNETIC CORE LOGICAL CIRCUIT Filed. April 29, 1959 '2 Sheets-Sheet 1 FIG. 1

1 0 JUL/16 11 11 b I'NVENTOR GEORGE E. OLSON ATTORNEY March 17, 1964 G. E. OLSON MAGNETIC CORE LOGICAL CIRCUIT 2 Sheets-Sheet 2 'Filed April'29. 1959 STAVGETI sTXE STAKE 2 sue? 1 FIG. 5

United States Patent 3,125,744 MAGNETIC CORE LGGICAL CCUIT George E. Olson, Wappingers Falls, N.Y., assignor to International Business Machines Corporation, New York, N.Y., a corporation of New York Filed Apr. 29, 1959, Ser. No. 809,772 7 Claims. (Cl. 34tl174) The present invention relates generally to electrical circuits employing magnetic cores and more particularly to improvements in logical circuits of the type useful in forming counters and shift registers and which include magnetic cores as principal components thereof.

The invention is directed to a logical circuit of the type which utilizes a bistable magnetic core in combination with a switching and amplifying device such as a transistor and wherein predetermined alterations of the magnetic state of a core caused by input pulses are used to cause a normally non-conductive switching device to operate for the purpose of producing powered output pulses and for the further purpose of activating control means coupled to the core for resetting or maintaining the core in a desired magnetic state. In a circuit of this type, the switching device is rendered operative by an output resulting from an alteration of the state of the magnetic core. The operation of the switching device commences during the alteration and is substantially coincident with the input pulse causing the alteration. The activation of the control means for resetting or maintaining the core in reset condition must continue, however, for some time after the alteration of the state of the core has ceased. It has been necessary, therefore, to provide means for maintaining the switching device conductive for a period after the alteration of the state of the core has been completed whereby to insure effective activation of the control means.

It is the principal object of this invention to provide a circuit of the character described wherein the switching device is permitted to return to non-conductive condition when the alteration of the state of the core has been completed and wherein the activation of the control means for resetting or maintaining the core in reset condition is continued after the switching device has become non-conductive.

A further object of the invention is to provide temporary electrical storage means in the output circuit of the switching device adapted to store energy during operation of the switching device and deliver the stored energy to the control means after the switching device has become non-conductive.

It is also a purpose of the present invention to provide a system including a plurality of circuits of the character described having considerable flexibility and which may be adapted for decimal counting as Well as for binary counting and shift register purposes.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular description of preferred embodiments of the invention, as illustrated in the accompanying drawings.

In the drawings:

FIGURE 1 is a diagrammatic illustration of a logical circuit constructed in accordance with the present invention;

FIGURE 2 is a diagrammatic illustration similar to FIGURE 1 but showing a modified form of the invention;

FIGURE 3 illustrates a plurality of applicants improved logical circuits combined to form a binary counter;

FIGURE 4 illustrates a plurality of applicants improved logical circuits combined to form a decimal counter; and

"ice

FIGURE 5 is an illustration of a typical hysteresis loop of magnetic material suitable for use with the present invention.

The logical circuit provided in accordance with the present invention is of the type useful in forming counters and shift registers. The circuit, generally identified by the numeral It in the drawings, operates substantially as a binary trigger, being switched from one stable condition to another by pulses delivered thereto. The first of a series of input pulses results in the circuit 10 being switched from its initial or reset condition to a set condition. The second input pulse switches the circuit 10 from the set condition back to the initial condition. During the change of state from the set condition to the reset condition, the switching device is operated to provide a powered output pulse signifying the application of two input pulses.

The elementary bistable unit of the circuit 10 is a bistable magnetic core 11 formed of a magnetic material having a substantially wide hysteresis loop similar to the one shown in FIGURE 5, whereby to provide alternate stable states of substantial magnetic remanence. These alternate states are identified in FIGURE 5 as the 1 and the 0 states, in accordance with customary binary terminology. It will be understood that the magnetic state of core 11 may be altered by application of magnetic force thereto through a suitable winding coupled to the core 11. The magnetic force may be in either of two directions, as shown by the vectors +H and I-I in FIGURE 5. A force having the sense and magnitude of 4-H will drive the core 11 to a positive saturation condition +B and a force having the sense and mag nitude of H will drive the core to a negative saturation condition B The core will, of course, remain in saturated condition only so long as the magnetic force exists, and when the force is removed, the core will traverse its hysteresis loop to the nearest remanence state; the 1 state if driven to -l-B and the 0 state if driven to B The core 11 has three windings magnetically coupled thereto. These are an input winding 11a, an output winding 11b, and a control winding 110. It will be noted that each of the several windings illustrated in FIGURE 1, and throughout the drawings, is provided with a black dot adjacent one end. These dots serve to indicate the sense of the windings. According to the notation adopted herein, current flowing into the dotted end of a winding will drive the associated core from the l remanence state to the 0 remanence state. Current flowing into the undotted end of a winding will drive the associated core from the 0 remanence state to the 1 remanence state. The dots also indicate the polarity of voltage induced in a winding by a flux change in the core coupled therewith. When a core traverses its hysteresis loop from the 0 state to the 1 state, the voltage induced in windings coupled thereto will be negative at the dotted ends. When a core traverses its loop from the 1 state to the 0 state the induced voltage will be positive at the dotted ends of the associated windings.

As shown in FIGURE 1, the input winding 11a of the core 11 has a capacitor 10. connected in series therewith. A resistor 13 is connected across the series combination of the winding 11a and the capacitor 12 to form a closed circuit loop. Input pulses are delivered to the input cir cuit just described through

input terminals

14 and 15 connected as indicated in FIGURE 1. A unilateral conducting device 16 is provided at the terminals 14 and is poled to pass current into the dotted end of the winding 11a. With this arrangement, input pulses of a polarity positive at the terminal '14 and of magnitude and duration suflicient to drive the core 11 from one stable state to the other will cause current flow through the winding 11a in a direction to create a force tending to drive the core ill to its negative saturation condition B and hence the remanence state. These input pulses will, at the same time, charge the capacitor 12, storing electrical energy therein. While the resistor 13 forms a shunt across the winding 11a and the capacitor 12, its value is chosen to provide a relatively high impedance compared with that of the winding 11a and the capacitor 12. Most of the energy delivered to the circuit will pass through the winding 11a and capacitor 12.

Assuming the magnetic history of the core to be such that it is initially in the "0" remanence state, substantially no flux change will take place when it is driven to its negative saturation condition, B The winding 111a will, therefore, exhibit low impedance, and most of the energy of the input pulse will pass through the winding 11a and become stored in the capacitor 12. Upon termination of the input pulse the capacitor 12 will discharge through the closed circuit comprising the winding 1 1a and the resistor 13. The discharge current will pass through the winding Ma from the undotted end to the dotted end and will create a force tending to drive the core 11 to its positive saturation condition +13 and, hence, to the 1 remanence state. The circuit parameters are chosen to provide a discharge pulse of sufiicient magnitude and duration to fully switch the core 11. This input circuit is thus operable upon the application of a single input pulse, to drive the core first to its 0 state, and next to its 1 state.

The output winding lllb of the core 11 will have a voltage induced therein each time a flux change occurs in the core 11. This voltage will be positive at the dotted end when the core traverses its hysteresis loop from the 1 remanence state to the 0 remanence state, and negative at the dotted end when the core is driven from the 0 state to the 1 state. As illustrated in FIGURE 1 the winding llb is connected between the base 1% and emitter 176 of a transistor 17. The collector 170 of the transistor 17 is connected through a load resistor 18 to a positive voltage source such as the battery 19. The emitter 17e is connected to ground through a temporary storage capacitor 20.

The transistor 17 shown in FIGURE 1 is of the NPN type, and will remain in a cut-off or non-conductive state until the base 17b thereof is made positive with respect to the emitter 17c. With the connections shown in FIGURE 1, this can only occur during the time winding 1112 experiences an induced voltage having a polarity positive at the dotted end thereof. This condition obtains only during the time the core 11 is being driven from the 1 remanence state to the O remanence state. When the core 11 is being driven from the 0 state to the 1 state, the voltage induced in winding 11b is negative at the dotted end, back biasing the base-emitter junction of transistor 17 to maintain it non-conductive. When no voltage exists in Winding 11b, the base 17b and emitter 17@ are at the same potential, and the transistor is held non-conductive.

It will be understood that if the hysteresis loop of the core 11 is not perfectly rectangular, small flux changes will occur when the core is driven from the 0 state to the negative saturation condition '-B These flux changes will induce small voltages in winding 11b of a polarity tending to turn on the transistor 17. To insure that the transistor is not turned on in response to these voltages, a resistor 21 may be inserted between the dotted end of winding 11b and the base 17b of transistor :17. The resistor 21 will reduce the voltage applied to base 17b in response to activation of Winding 11b, and if its value is properly selected, it may be made to insure that no signal other than signals induced in response to switching the core 11 from the 1 to the 0 state, will turn on transistor 17.

When the transistor 17 is rendered conductive, current flow will be established from the voltage source 19 through the load resistor 18, the transistor 17 and the temporary storage capacitor 26 to ground. This current flow will provide a powered output which, for example, may be obtained from terminals 22 connected to the ends of resister 13, and will also serve to place a substantial charge upon capacitor iii. The current flow will, however, exist only during the time core 11 is experiencing a flux change, and when the core is fully switched, the voltage in winding ll llb necessary to activate the transistor 17 will disappear and the transistor 17 will cut-off.

The purpose of capacitor 20, as will more clearly appear later herein, is to provide temporary storage of energy to be ultimately delivered to a control circuit including the winding lie of the core 11. The control Winding is provided for the purpose of cancelling the eifect of certain ones of the discharge pulses delivered from the capacitor 12 in the input circuit of core ll. The energy stored in capacitor Z53 is delivered to winding 110 by a line 23 connected between the dotted end of winding 11c and the emitter l7e of transistor 17. A resistor 24 is interposed in line 23 to control the discharge of capacitor 2d.

The operation of the circuit shown in FIGURE 1 is as follows: Assuming the core lid to be initially in the 0 remanence state, the first input pulse applied to the terminals 14- and 15 will energize input winding 11a to drive the core 1 1 to the negative saturation condition -B and at the same time charge capacitor 12. When the core ill is driven from the 0 state to --B the fiux change therein will be slight, as will be apparent from examination of FIGURE 5. The voltage induced in winding 1111 will be slight, and of insufficient magnitude to turn on transistor -17.

Upon termination of the first input pulse, capacitor 12 will discharge through winding 11a and resistor 13, producing a force in the core 11 in a direction to drive it to the positive saturation condition +B and, hence, to the 1 remanence state. Substantial flux change will occur during this magnetic excursion of the core 11, but the polarity of the voltage developed thereby in winding 11b will be negative at the dotted end, back biasing the base-emitter junction of transistor 1'7 and maintaining it non-conductive. Voltage of the same polarity may be induced in the control winding 11c, placing a charge on capacitor 20, but this charge will be quickly dissipated once the core has been switched, and will not effect the circuit. When the capacitor 12 has been fully discharged after termination of the first pulse, the core 11 is left in the 1 remanence condition. No output pulse has been delivered to the output terminals The second input pulse delivered to the

terminals

14 and 15 will energize input winding Illa to create a force in a direction to again drive core 11 to its negative saturation condition -B and, hence, to the O remanence state. Since core lll was left in the 1 state after the first pulse, a substantial flux change will occur during this excursion, and a substantial voltage, of a polarity positive at the dotted end, will be induced in output winding 11b. This voltage will cause transistor 17 to conduct. Current will be thus permitted to flow in the collector and emitter circuits from the battery 19 to ground, providing a powered output at terminals 22, and charging capacitor 24 Some current may also flow from emitter 176 through control winding 110 to ground thus aiding the switching of core 11 from the 1 state to the 0 state, but due to the impedance of resistor 24, most of the flow will be through capacitor 20 until it is fully charged. As soon as the core has fully switched, the voltage in output winding 11b will disappear, allowing the transistor 17 to cut-off, terminating both the output at terminals 22 and the charging of capacitor 20.

It will be noted that the cut-01f of transistor 17 is substantially simultaneous with the termination of the second input pulse, presuming that said input pulse is of no longer duration than the period of time required to switch core 11 from the 1 state to the state.

Capacitors

12 and 20 are thus allowed to commence discharging at the same time. For proper operation of the circuit, the parameters of the discharge circuits of these two capacitors should be adjusted to provide substantially identical RC time constants so that current flow through control winding 11c occurs simultaneously with the flow of capacitor discharge current through winding 11a. Since the current flow in winding 110 is at this time from the dotted to the undotted end, and the current flow in winding 11a is in the opposite direction, the magnetic forces produced thereby oppose each other leaving the core 11 in the 0 condition to which it was driven by the second input pulse.

It will be seen from the foregoing that after the second input pulse, the circuit 10 is left in its initial condition, and that only a single output has been produced, that output being a result of the second input pulse. A third input pulse applied to the

terminals

14 and 15 will affect the circuit 10 in the same manner as the first, and a fourth input pulse will produce the effects of the second. The circuit thus operates as a binary counter.

The advantage of the circuit over prior art devices resides in the fact that the transistor 17 is not maintained in conduction for a longer period than that required to switch core 11 from one state to the other, and that the on time of the transistor 17 does not control the inhibiting function of the control circuit including winding 110. The length and magnitude of the inhibiting pulse is controlled by the characteristics of the temporary storage network including capacitor 20 and resistor 24.

The transistor 17 shown in the circuit of FIGURE 1 is, as previously described, of the NPN type. It will be understood, however, that a PNP transistor may be used without departing from the spirit of the invention. The use of a PNP type transistor in place of transistor 17 will, of course, necessitate corresponding reversals of the polarity in the several circuit elements associated therewith, but it is believed that such changes will be obvious to those skilled in the art. It should also be understood that a suitable vacuum tube or other equivalent device may be used in place of the transistor 17. The transistor 17 operates primarily as a switch, and any other switching device capable of providing the same function may be substituted therefor.

Although the values of the circuit components are not critical and may be varied within reasonable limits, and although it is believed that the selection of values of the several components necessary to practice the invention is within the purview of the skilled technician, a typical set of values for the several components has been set forth in the table below.

Table I Resistor 13:470 ohms Resistor 18:470 ohms Resistor 24:220 ohms Capacitor 12:.005 microfarad Capacitor 20:.01 microfarad Battery 19:18 volts Core 11=ferrite core of substantially square loop material Inside diameter=80 mils Outside diameter=ll mils Winding 11a=40 turns Winding 11b=10 turns Winding 110:40 turns Transistor 17 =type NPN alloy junction FIGURE 2 of the drawings illustrates another embodiment of the invention wherein the transistor 17 is connected as an emitter follower, with a load resistor 18 in the emitter circuit rather than in the collector circuit as in FIGURE 1. This circuit, identified as is intended to operate in the same manner as the circuit 10 of FIGURE 1 and is shown as exemplary of the modification which may be made in the circuit without departing from the spirit of the invention. Examination of FIGURE 2 will show that upon operation of the circuit of FIGURE 2, an output is provided at terminals 22' at the same times and in the same manner as previously described.

FIGURE 2 also illustrates another modification which may be made in applicants improved logical circuit. Whereas, in FIGURE 1, the winding 11b of core 11 is connected directly between the base 17b and emitter 172 of transistor 17, the undotted end of winding 11b of the circuit 10' shown in FIGURE 2, is connected through a negative bias source 25 to ground. This bias source 25 will normally maintain the transistor 17 cut off, but is small enough to be overcome by the substantial voltage induced in winding 11b when the core 11 switches from the 1 state to the 0 state. The bias source 25 serves to insure against activation of the transistor 17 by spurious noise signals.

In FIGURE 3, there is shown a four stage binary counter utilizing the circuit 10. A counter of this type should provide an output from the last stage after the sixteenth input pulse, and is often referred to as a sixteen counter. As shown, the counter comprises four of the circuits 10 connected in cascade to form counter stages 1, 2, 3 and 4. The four stages are identical except that in

stages

2, 3 and 4 the resistor 13, normally a part of the input circuit, is omitted and the load resistor 18 of the preceding stage is substituted in its place. Coupling from one stage to the next is provided in this manner. Only the first stage is provided with

input terminals

14 and 15 to receive input pulses to be counted, and only the last stage is provided with output terminals 22.

The counter of FIGURE 3 is initially set with all cores in the 0 remanence condition. The first input pulse applied to

terminals

14 and 15 drives the core of stage 1 to its negative saturation condition l3 and charges capacitor 12 of stage 1. Upon termination of the first input pulse, capacitor 12 discharges and drives the first stage core to its 1 remanence state. Theother three cores remain in the O remanence state. The second input pulse applied to

terminals

14 and 15 drives the first stage core 11 from the 1 remanence to the 0 remanence state providing an output which turns on the first stage transistor 17. This provides an input pulse to the second stage and also charges capacitor 21) of stage 1, energizing the control circuit including Winding 11c, hereinbefore described, to insure that the core of stage 1 is left in the O remanence state. The input pulse to the second stage results in that core being switched to the 1 remanence state in the manner hereinbefore described. The second pulse, then, leaves the cores of

stages

1, 3 and 4 in the 0 condition and the core of stage 2 in the 1 condition.

The third input pulse affects stage 1 in the same manner as the first input pulse, leaving the core thereof in the 1 state but providing no output to the second stage. After the third input pulse the cores of

stages

1 and 2 are in the 1 state and the cores of

stages

3 and 4 are in the 0 state. The fourth input pulse, finding the core of stage 1 in the l remanence state switches that core to its 0 state and turns on the first stage transistor 17 to provide an input pulse to the second stage. The input pulse to the second stage, finding the core 11 thereof in the 1 state switches that core to the 0 state and turns on the second stage transistor 17 providing an input to the third stage core 11. Since both the first and second stage transistors 17 have been turned on, the control circuits thereof are activated, resulting in both the first and second stage cores being left in the 0 remanence state. The input pulse provided to the third stage is the first experienced by the third stage core 11 and that core is consequently left in the 1 remanence 7 state. Therefore, after the fourth input pulse, the cores of

stages

1, 2 and 4 are in the remanence state and the core of stage 3 is in the 1 remanence state.

The fifth and succeeding input pulses applied to the

terminals

14 and 15 affect the circuits of stages 14 in a manner similar to that just described, so that upon the application of the sixteenth input pulse the transistor 17 of stage 4 is turned on to provide an output at the terminals 22 connected in the collector circuit thereof. Table II, below, illustrates the conditions of the several stages after each of the sixteen input pulses. It will be noted that if weights are assigned to the several stages so that stage 1 represents 2, stage 2 represents 2 stage 3 represents 2 and stage 4 represents 2 the several conditions of the counter will represent the binary numbers zero through fifteen, inclusive.

Table 11 Input Pulse Stage 1 Stage 2 Stage 3 Stage 4 O O 0 0 0 1 1 0 0 0 2 0 1 0 O 3 1 1 O 0 4 0 0 1 0 5 1 0 1 0 6 0 1 1 0 7 1 1 1 0 8 0 0 0 1 9 1 O 0 1 10 0 1 0 1 1 1 1 1 0 1 12 0 0 1 1 13 1 0 1 1 14 O 1 1 1 15 1 1 1 1 16 0 0 0 0 Applicant has found that logical circuits constructed in accordance with the present invention may be utilized for decimal counting as well as for binary counting. If means are provided in a circuit such as that shown in FIGURE 3, to provide an output and reset the counter upon application of the tenth input pulse, decimal counting may readily be accomplished. Examination of Table II will show that the counter of FIGURE 3 will reside, after the ninth input pulse, in a condition wherein the first and fourth stage cores 11 are in the 1 remanence state and the second and third stage cores 11 are in the 0 remanence state. The tenth input pulse drives the first stage core 11 to the 0 state providing an output which turns on the first stage transistor 17. Current flow in the output of the first stage transistor charges the first stage capacitor 20 to activate the control circuit of the first stage whereby to maintain the first stage core 11 in the 0 state, and also provides an input pulse to the second stage. The second stage core 11, being in the 0 state is not switched, and the capacitor 12 associated therewith receives a substantial charge, whereby to drive the second stage core to the 1 state upon termination of the tenth pulse. Since the second stage core 11 is not driven from the 1 to the 0 state, no output to the third stage is provided. After the tenth pulse, then, the first and third stage cores 11 are in the 0 state and the second and fourth cores are in the 1 state.

To adapt the circuit of FIGURE 3 for decimal counting, it is necessary to provide means operable on the application of the tenth input pulse to drive the fourth stage core 11 to Zero, whereby to provide an output signifying that ten pulses have occurred. It is also necessary to activate the control circuit of the second stage to prevent the core thereof from being switched to the 1 stage by discharge of its associated capacitor 12. FIGURE 4 shows a circuit wherein means for accomplishing these results are provided. With the exception of the modifications hereinafter described, the circuit of FIGURE 4 is 8 identical to that of FIGURE 3 and operates in exactly the same manner.

In order to drive the fourth stage core 11 to the 0 state upon application of the tenth pulse, the control winding of the fourth stage is connected, by lines 31) and 31, in the collector circuit of the first stage transistor 17 It will be noted from examination of FIGURE 4, that the connections are arranged so that current flowing in the collector circuit of the first stage transistor 17 passes through the fourth stage winding 110 in a direction to drive the associated core to the 0 remanence state. Since, at the time of application of the tenth input pulse, the first stage transistor 17 is rendered conductive as soon as the first stage core 11 commences to traverse its hysteresis loop from the 1 state to the 0 state, the first and fourth stage cores are driven to the 0 state simulta neously.

The voltage induced in winding 11b of the fourth stage when the core 11 thereof commences to switch to the 0 state, is of a polarity positive at the dotted end, and turns on the fourth stage transistor 17. The resulting current flow through the fourth stage load resistor 18 produces an output at terminals 22 to signify the count of ten input pulses.

It will be noted that the circuit including lines 34 and 31 and winding 110 of stage 4 is activated, not only upon application of the tenth input pulse, but each time the first stage transistor 17 is turned on, that is, upon the second, fourth, sixth, eighth and tenth pulses. Examination of Table II will show that the fourth stage core 11 is left in the 0 state after each of the first seven pulses, however, so the activation of its winding 110 by the second, fourth, sixth and eighth pulses has no effect.

Immediately upon termination of the tenth input pulse, all cores 11 of the circuit are in the 0 emanence state. The cores 11 of

stages

1 and 4 have been driven to that state as a result of that pulse, and the cores 11 of

stages

2 and 3 were previously in the 0 state. The input circuit capacitors 12 of

stages

1 and 2 are charged however, due to the application of current pulses to their associated windings 11a. Immediately upon termination of the tenth pulse, these capacitors commence to discharge, producing forces in their associated windings 11a in a direction to switch the cores 11 of

stages

1 and 2 to the 1 state. Since the first stage transistor 17 was turned on during the tenth input pulse, the capacitor 21 in its emitter circuit received a charge. The control circuit of stage 1 is therefore activated coincidently with the discharge of the first stage capacitor 12 to cancel the elfects thereof, maintaining the first stage core 11 in the 0 state. The transistor 17 of the second stage was not turned on during the tenth pulse, however, and did not charge the capacitor 20 in its control circuit. Since it is necessary that the second stage core 11 be maintained in the 0 state to reset the counter at home position, means must be provided to charge capacitor 23 of stage 2 during the tenth pulse. This is accomplished simply by connecting the emitter 17a of the fourth stage transistor 17 to the emitter 17e of the second stage transistor 17 by a line 32 so that the second stage capacitor 21) may be charged by either. Transistor 17 of stage 4 being on during the tenth pulse as hereinbefore described, will thus charge capacitor 20 of stage 2 to provide for activation of the associated control circuit after termination of the tenth pulse, insuring that core 11 of stage 2 is maintained in the 0 state.

It is believed apparent from the foregoing that the present invention provides a logical circuit that is extremely useful and efiicient. As shown in FIGURES 3 and 4 it is well adapted for both binary and decimal counting, providing in each case a reliable circuit which requires no drive means other than the pulses to be counted. Since the outputs of the several stages are powered, the input pulses are required to drive only the first stage, and throughout the counting operation the load upon the input 'pulse source remains the same, regardless of the number of stages included.

It will be understood, of course, that while the counters of FIGURES 3 and 4 are comprised of circuits constructed as shown in FIGURE 1, they may also comprise the modified circuits of FIGURE 2. The circuits of

FIG URES

1 and 2 are equivalents.

It should also be understood that while applicant has shown the present invention incorporated in counting circuits alone, this showing is to be considered as exemplary only and is not intended to limit the invention. It will be apparent to those skilled in the art that the improved logical circuit disclosed herein is also useful in forming shifting registers and other devices.

While the invention has been particularly shown and described with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein Without departing from the spirit and scope of the invention.

What is claimed is:

1. An electrical circuit comprising a magnetic core having alternate states of magnetic stability, input means coupled to said core for altering the magnetic state of said core, an output winding magnetically coupled to said core wherein voltage is induced upon change of the core from one stable state to the other, switching means coupled to said input winding for producing a manifestation in response to voltage of a predetermined polarity induced in said output winding, a control winding magnetically coupled to said core for afiecting the magnetic state of the core, and storage means coupled to said switching means and to said control winding operably responsive to said manifestation for applying current to said control winding whereby to affect the magnetic state of said magnetic core in response to operation of said switching means.

2. An electrical circuit comprising a magnetic core having alternate states of magnetic stability, input means coupled to said core for altering the magnetic state of said core, an output winding magnetically coupled to said core wherein voltage is induced upon change of the core from one stable state to the other, a temporary storage capacitor, switching means coupled to said output winding and to said capacitor responsive to voltage of a predetermined polarity induced in said output winding for charging said capacitor, and discharge circuit means connected to said capacitor, said discharge circuit means including a control winding magnetically coupled to said core and operable to aifect the magnetic state of said magnetic core upon discharge of said capacitor.

. 3. An electrical circuit comprising a magnetic core having first and second magnetic stable states, an input winding magnetically coupled to said core, input means connected with said winding for applying input pulses thereto in a direction to develop a magnetizing force tending to drive said core to its first stable state, means coupled to said input winding operable upon termination of each said input pulse to apply a pulse to said winding in a direction to develop a magnetizing force tending to drive said core to its second stable state, an output winding magnetically coupled to said core wherein voltage is induced during changes of the core from one state to the other, switching means coupled to said output winding for producing a manifestation in response to voltage induced in said output winding during change of said magnetic core from its second state to its first state, a control winding magnetically coupled to said magnetic core, and means coupled to said control winding and to said switching means operable upon termination of said manifestation to apply a pulse to said control winding in a direction to develop a magnetizing force maintaining said magnetic core in its first state whereby to oppose the force developed by the second named means coupled to the input winding.

4. An electrical circuit comprising a magnetic core having first and second magnetic stable states, an input winding magnetically coupled to said core, input means connected with said winding for applying input pulses thereto in a direction to develop a magnetizing force tending to drive said core to its first stable state, means coupled to said input winding operable upon termination of each said input pulse to apply a pulse to said winding in a direction to develop a magnetizing force tending to drive said core to its second stable state, an output winding magnetically coupled to said core wherein voltage is induced during changes of the core from one state to the other, a temporary storage capacitor, switching means coupled to the output winding responsive to voltage induced in said output Winding during change of said core from its second state to its first state for charging said capacitor, and discharge circuit means connected to said capacitor, said discharge circuit means including a control winding magnetically coupled to said core and being operable upon discharge of said capacitor to apply a pulse to said control winding in a direction to develop a magnetizing force tending to maintain said core in its first state whereby to oppose the effect on the core of the second named means connected to the input winding.

5. An electrical circuit comprising a magnetic core having first and second stable states, an input winding magnetically coupled to said core, input means for applying an input pulse to said winding in a direction to develop a magnetizing force tending to drive said core to its first stable state, first capacitive storage means coupled to said input winding operable to be charged upon application of said input pulse and operable upon termination of said input pulse to apply a pulse to said input winding in a direction to develop a magnetizing force tending to drive said core to its second stable state, an output winding coupled to said core wherein voltage pulses are induced in response to change of the core from one magnetic state to the other, second capacitive storage means, switching means coupled to the output winding responsive to voltage induced in said output winding during change of said core from its second state to its first state for charging said second capacitive storage means, and discharge circuit means connected to second capacitive storage means, said discharge circuit means including a control winding magnetically coupled to said core and being operable upon discharge of said second capacitive storage means to apply a pulse to said control winding in the direction to develop a magnetizing force tending to maintain said core in its first state whereby to oppose the magnetizing force developed by discharge of said first capacitive storage means.

6. In an electrical circuit the combination of a magnetic core capable of assuming first and second alternate states of magnetic stability, an input winding magnetically coupled to said core, means for applying an input pulse to said winding to cause said core to assume the first alternate magnetic state, an output winding magnetically coupled to said core wherein voltage pulses are induced upon change of said core from one state to the other, switch means having a control circuit and an output circuit, said control circuit being connected to said output winding whereby to activate said switch means only upon a change of said core from said second state to said first state caused by application of said drive pulse, first electrical storage means connected with the input winding of said magnetic core operable to receive energy during applicatron of said drive pulse and operable to discharge upon termination of the drive pulse whereby to apply a pulse of opposite polarity to said input winding to change said core from said first magnetic state to said second state, seeon electrical storage means connected in the output circuit of said switch means and adapted to receive energy during current flow in said output circuit, and to discharge energy upon termination of said flow, and a discharge circuit for said last named electrical storage means including th rd winding means coupled to said magnetic core, said third winding means being operable upon discharge of energy from said last named storage means therethrough 11 to maintain said magnetic core in the first magnetic state and thereby cancel the etfect of the discharge of said first named electrical storage means.

7. A decimal counting circuit comprising four magnetic cores each having first and second stable states, a separate input winding magnetically coupled to each said magnetic core, separate input circuit means coupled to each said input winding operable upon application of an input pulse thereto to pass current through the input winding in a direction to develop a magnetizing force tending to drive the associated magnetic core to its first stable state, separate capacitive storage means coupled to each said input winding for receiving a charge upon application of each said input pulse and operable to discharge upon termination of each said input pulse to pass current through said input winding in a direction to develop a magnetizing force tending to drive the associated magnetic core to its second stable state, an output circuit for each said magnetic core, a power source for each said output circuit, separate switching means in each said output circuit for controlling current flow therethrough, separate activating means for each said switching means operable to activate said switching means to permit current flow in said output circuit only in response to change of the associated magnetic core from its second stable state to its first stable state, means for applying input pulses to be counted to the input circuit means of a first one of said four magnetic cores, means for applying an input pulse to the input circuit means second of said four cores only in response to current flow in the output circuit of said first core, means for applying an input pulse to the input circuit means of said third core only in response to current flow in the output circuit of said second core, means to apply an input pulse to the input circuit means of said fourth core only in response to current flow in the output circuit of said third core, first and third separate control means coupled respectively to said first and third magnetic cores each for developing a magnetizing force tending to maintain the associated magnetic core in its first stable state and opposing the force developed during discharge of the capacitive storage means associated with said core only in response to current flow in the output circuit of said associated core, second control means coupled to said second magnetic core for developing a magnetizing force tending to maintain said second core in its first stable state and opposing the force developed during discharge of the capacitive storage means associated with said second core in response to current flow in the output circuit of either of the second or fourth magnetic cores, and auxiliary input means coupled to said forth magnetic core for developing a magnetizing force tending to drive said fourth core to its first stable state in response to current flow in the output circuit of the first magnetic core.

References Cited in the file of this patent UNITED STATES PATENTS 2,713,675 Schmitt July 19, 1955 2,902,609 Ostrofi Sept. 1, 1959 2,949,542 Wiseman Aug. 16, 1960 2,955,211 Ostroif Oct. 4, 1960 2,967,950 Marchand Jan. 10, 1961 2,974,311 Kaufmann Mar. 7, 1961 3,063,038 Davis et a1. Nov. 6, 1962 OTHER REFERENCES Publication: IBM Technical Disclosure Bulletin, vol. 1, No. 2, August 1958.

Claims

1. AN ELECTRICAL CIRCUIT COMPRISING A MAGNETIC CORE HAVING ALTERNATE STATES OF MAGNETIC STABILITY, INPUT MEANS COUPLED TO SAID CORE FOR ALTERING THE MAGNETIC STATE OF SAID CORE, AN OUTPUT WINDING MAGNETICALLY COUPLED TO SAID CORE WHEREIN VOLTAGE IS INDUCED UPON CHANGE OF THE CORE FROM ONE STABLE STATE TO THE OTHER, SWITCHING MEANS COUPLED TO SAID INPUT WINDING FOR PRODUCING A MANIFESTATION IN RESPONSE TO VOLTAGE OF A PREDETERMINED POLARITY INDUCED IN SAID OUTPUT WINDING, A CONTROL WINDING MAGNETICALLY COUPLED TO SAID CORE FOR AFFECTING THE MAGNETIC STATE OF THE CORE, AND STORAGE MEANS COUPLED TO SAID SWITCHING MEANS AND TO SAID CONTROL WINDING OPERABLY RESPONSIVE TO SAID MANIFESTATION FOR APPLYING CURRENT TO SAID CONTROL WINDING WHEREBY TO AFFECT THE MAGNETIC STATE OF SAID MAGNETIC CORE IN RESPONSE TO OPERATION OF SAID SWITCHING MEANS.