US3115424A - Process for the passivation of semiconductors - Google Patents

Process for the passivation of semiconductors Download PDF

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US3115424A
US3115424A US104382A US10438261A US3115424A US 3115424 A US3115424 A US 3115424A US 104382 A US104382 A US 104382A US 10438261 A US10438261 A US 10438261A US 3115424 A US3115424 A US 3115424A
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semiconductor
coating
varnish
percent
semiconductors
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US104382A
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Eannarino George
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Infineon Technologies Americas Corp
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International Rectifier Corp USA
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02041—Cleaning
    • H01L21/02043—Cleaning before device manufacture, i.e. Begin-Of-Line process
    • H01L21/02052—Wet cleaning only
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/906—Cleaning of wafer as interim step
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/958—Passivation layer

Definitions

  • This invention relates to the fabrication of semiconductors. More particularly the present invention relates to the surface treatment of semiconductor devices to effect a uniformity in the electrical characteristics thereof.
  • a solvent such as alcohol, acetone, or xylene and the like
  • an additional step comprising treatment of the semiconductor units with trichloroethylene is introduced after the washing thereof with distilled and deionized water. Oxidation of the semiconductor surfaces to provide an oxide film thereon occurs in the process herein described during the sequence of steps as recited; each of these steps being carried on in the presence of air.
  • aqueous media employed in washing the surfaces of the semiconductor devices of a solution of an aliphatic amine.
  • the preferred amine is triethylenetetramine, although alkylene diamines such as ethylene diamine, triethylene diamine, and hexylene diamine are also usefully employed in the present invention.
  • the amines are purified by distillation so that they are substantially free of metallic contaminants such as tin and 1I'OI1.
  • the metallic impurities of the amine be less than 3 parts per million (p.p.m.). Where tin and iron may be present, they are preferably reduced to amounts less than 3 p.p.m. and 2 ppm. respectively.
  • Step 1 comprises immersion of the semiconductor device or devices disposed in a chemically inert basket formed, for example, of polystyrene, into a solution of nitric acid, hydrofluoric acid, sulfuric acid, or mixtures thereof at room temperature for a brief period, normally within the range of 1 second to 60 seconds.
  • An illustrative etching solution comprises 86 percent by volume of concentrated nitric acid and 14 percent by volume of 48 percent dilute hydrofluoric acid.
  • Step 2 Etching of the semiconductor surfaces, whether of the P- on N-type, is followed by Step 2 wherein the aforesaid surfaces are rinsed with distilled water or tap water and successive rinsings with deionized water; each of these aqueous media having a pH of 5.5 to 7.2; said pH having been attained by the dissolution in the rinse water of the selected amine, e.g. triethylenetetramine, an amount by volume of .001 percent to 5.0 percent.
  • Each of these rinsings is best accomplished by immersion of the device in the aqueous bath for a period of 2 to 4 seconds; the bath temperature being maintained at a temperature of 70 C. to 90 C.
  • the elevated temperatures employed expand the junction surfaces of these semiconductor devices, thus aiding in the passivation thereof.
  • the semiconductor devices are immersed in an organic solvent for further removal of coating impurities.
  • Desirable solvents for this purpose are aromatic hydrocarbons, ketones, and alcohols.
  • Step 3 This stage in the sequence is referred to as Step 3 in the accompanying diagram and is succeeded simply by drying of the semiconductor surfaces (Step 4) at temperatures of about 100 C., although this temperature is not narrowly critical.
  • the coating of the semiconductor devices is accomplished with a suitable silicone impregnating varnish, e.g. Dow-Corning Silicone Varnish #996 and #997, employed in concentrated or dilute form and including an amount of purified triethylenetetramine within the range of .001 percent to 5 percent and most desirably about 0.1 percent by volume of said silicone varnish.
  • a suitable silicone impregnating varnish e.g. Dow-Corning Silicone Varnish #996 and #997, employed in concentrated or dilute form and including an amount of purified triethylenetetramine within the range of .001 percent to 5 percent and most desirably about 0.1 percent by volume of said silicone varnish.
  • This amine is used in this step only where an N-type surface is to be provided.
  • the particular silicone varnish herein referred to is commercially available from Dow-Corning Co. and is described in brochures Nos. 10-2681) and 10270 of that company.
  • This coating phase, Step 5 of the instant process includes subsequent to application of the coating medium in conventional manner as, for example, by immersion, or less desirably by brushing on the semiconductor surfaces, the curing of the said coating thereon by baking of the treated semiconductors in a nitrogen or an inert atmosphere such as argon in an oven or other heating zone, e.g. infrared lamp, at a temperature within the range of 50 C. to 200 C.; this range being favored where, illustratively, large diode structures are subject to the process herein described. For ordinary purposes, however, a narrow range of from 150 C. to 200 C. is considered most efiicacious. Determination of the optimum baking time can be readily determined by one skilled in the art. In a typical operation, baking would continue for 24 hours.
  • a nitrogen or an inert atmosphere such as argon in an oven or other heating zone, e.g. infrared lamp
  • the concluding phase of the sequence embodying the practice of the present invention is sealing or encapsulation of the semiconductor devices by known methods employing suitable resins standard for such purposes.
  • suitable resins for example, the polymeric polyepoxides disclosed in US. Patents 2,872,427 and 2,879,235.
  • the aliphatic amine herein contemplated is purified so as to make it substantially free of metallic impurities such as tin, iron, and lead, which may be present in the unpurified product. Purification may be eflected by various known methods. In the case of triethylenetetramine, it has been found that a triple distillation will reduce the tin content to 1.7 parts per million (p.p.m.), the iron content to about 1 p.p.m., well within the prescribed limits.
  • Semiconductor rectifiers produced in accordance with the present process show consistently low leakage values.
  • a process for passivating a semiconductor surface which comprises washing the surface in an acid solution, sequentially rinsing the surface with an aqueous solution and an organic solvent, drying and varnish-coating the surface, and curing the varnish coating to produce the passivated semiconductor, the improvement comprising rinsing said surface in an aqueous solution having a pH of from 5.5 to 7.2 and containing an aliphatic polyamine selected from the group consisting of triethylenetetramine, ethylene diamine, triethylene diamine, and hexylene diamine, said polyamine being substantially free of metallic contaminants.
  • the varnish coating is constituted of a silicone varnish having incorporated therein said aliphatic polyamine in an amount of from .001 to 5 percent by volume of the silicone.

Description

Dec. 24, 1963 G. EANNARINO PROCESS FOR THE PASSIVATION OF SEMICONDUCTORS Filed April 20, 1961 ETCH /N AC/D SOLUT/O/Vv STEP R/NSE //V WATER 8 AM/NE STEP 2 RINSE /N 8 AM/IVE STEP 20 T R/CHL OROE T H YLENE WASH //V ORGAN/C SOLVENT STEP 3 STEP 4 STEP 5 STEP 6 NV EN TOR.
I GEORGE EA N/VA R/NO BY Osfro/enk, Faber, Garb 8 .Soffen A r rag/v5 rs United States Patent 3,115,424 PROCESS FOR THE PASSIVATION OF SEMICONDUCTORS George Eannarino, Los Angeles, Calif., assignor to International Rectifier Corporation, El Segundo, Calif., a
corporation of California Filed Apr. 20, 1961, Ser. No. 104,382 5 Claims. (Cl. 117-213) This invention relates to the fabrication of semiconductors. More particularly the present invention relates to the surface treatment of semiconductor devices to effect a uniformity in the electrical characteristics thereof.
Thus, methods employed heretofore in the treatment and aging of semiconductors have been known to cause varied and uncontrolled modifications in the electrical properties thereof. This failure to fix permanently and uniformly the electrical character of semiconductor surfaces has been evident in the production of both silicon and germanium semiconductor bodies.
It is a particular objective of the present invention, therefore, to effect the passivation of semiconductor surfaces, including transistors and rectifiers, treated and aged according to the process which comprises etching of semiconductor surfaces in a solution of hydrofluoric acid, nitric acid, and/or sulfuric acid succeeded by washing with distilled or tap Water and sequential washing with distilled deionized water. In this same procedure this washing is followed by rinsing of the devices in a solvent, such as alcohol, acetone, or xylene and the like; drying; and then coating the objects with a suitable composition, such as, for example, a silicone varnish. This coated product is then baked to cure the varnish and the devices encapsulated by known methods. Where large power rectifiers are being treated, an additional step comprising treatment of the semiconductor units with trichloroethylene is introduced after the washing thereof with distilled and deionized water. Oxidation of the semiconductor surfaces to provide an oxide film thereon occurs in the process herein described during the sequence of steps as recited; each of these steps being carried on in the presence of air.
In the aforesaid procedure, surface instability occurs in the semiconductor devices by virtue of the distilled and deionized water employed wherein the amount of carbon dioxide normally varies, resulting in changes of the pH therein with consequent alterations in the consistency of the semiconductor surfaces and variations, as noted, in the electrical characteristics thereof.
It has now been discovered that these variations in electrical characteristics can be substantially obviated by inclusion in the aqueous media employed in washing the surfaces of the semiconductor devices of a solution of an aliphatic amine. The preferred amine is triethylenetetramine, although alkylene diamines such as ethylene diamine, triethylene diamine, and hexylene diamine are also usefully employed in the present invention.
The amines are purified by distillation so that they are substantially free of metallic contaminants such as tin and 1I'OI1.
It is particularly desirable that the metallic impurities of the amine be less than 3 parts per million (p.p.m.). Where tin and iron may be present, they are preferably reduced to amounts less than 3 p.p.m. and 2 ppm. respectively.
Further stabilization of the aforesaid electrical properties of the semiconductor devices is had by incorporation of the aforesaid amine constituent in the varnish coating composition; and where employed, with the trichloroethylene treatment step as well.
Further objectives and advantages of the invention will become evident from the following detailed description taken in connection with the block diagram illustrating the various steps employed in the process of the invention.
As indicated in the diagram, Step 1 comprises immersion of the semiconductor device or devices disposed in a chemically inert basket formed, for example, of polystyrene, into a solution of nitric acid, hydrofluoric acid, sulfuric acid, or mixtures thereof at room temperature for a brief period, normally within the range of 1 second to 60 seconds. An illustrative etching solution comprises 86 percent by volume of concentrated nitric acid and 14 percent by volume of 48 percent dilute hydrofluoric acid.
Etching of the semiconductor surfaces, whether of the P- on N-type, is followed by Step 2 wherein the aforesaid surfaces are rinsed with distilled water or tap water and successive rinsings with deionized water; each of these aqueous media having a pH of 5.5 to 7.2; said pH having been attained by the dissolution in the rinse water of the selected amine, e.g. triethylenetetramine, an amount by volume of .001 percent to 5.0 percent. Each of these rinsings is best accomplished by immersion of the device in the aqueous bath for a period of 2 to 4 seconds; the bath temperature being maintained at a temperature of 70 C. to 90 C.
It is noted that one of the purposes of this treatment phase which contributes to the passivation of the semiconductors effected at this stage is the neutralization and removal of residual acid present in pin-holes" distributed upon the silicon or germanium surfaces of the semiconductor devices.
An optional step, Step 2a, employed most frequently with comparatively large elements, such as power rectifier units, for example, comprises heating the unit or units to a temperature within the range of C. to 135 C. and normally about C. for a period within the range of 5 minutes to 15 minutes and preferably about 10 minutes, after and during immersion in a bath composed of trichloroethylene and .001 percent to 5 percent of one of the same amino compounds employed in the aqueous media and recited hereinabove. The elevated temperatures employed expand the junction surfaces of these semiconductor devices, thus aiding in the passivation thereof. After these washes, the semiconductor devices are immersed in an organic solvent for further removal of coating impurities. Desirable solvents for this purpose are aromatic hydrocarbons, ketones, and alcohols. Illustrative of these are benzene, xylene, ethanol, methanol and acetone. This stage in the sequence is referred to as Step 3 in the accompanying diagram and is succeeded simply by drying of the semiconductor surfaces (Step 4) at temperatures of about 100 C., although this temperature is not narrowly critical.
The coating of the semiconductor devices is accomplished with a suitable silicone impregnating varnish, e.g. Dow-Corning Silicone Varnish #996 and #997, employed in concentrated or dilute form and including an amount of purified triethylenetetramine within the range of .001 percent to 5 percent and most desirably about 0.1 percent by volume of said silicone varnish. This amine is used in this step only where an N-type surface is to be provided. The particular silicone varnish herein referred to is commercially available from Dow-Corning Co. and is described in brochures Nos. 10-2681) and 10270 of that company.
This coating phase, Step 5 of the instant process, includes subsequent to application of the coating medium in conventional manner as, for example, by immersion, or less desirably by brushing on the semiconductor surfaces, the curing of the said coating thereon by baking of the treated semiconductors in a nitrogen or an inert atmosphere such as argon in an oven or other heating zone, e.g. infrared lamp, at a temperature within the range of 50 C. to 200 C.; this range being favored where, illustratively, large diode structures are subject to the process herein described. For ordinary purposes, however, a narrow range of from 150 C. to 200 C. is considered most efiicacious. Determination of the optimum baking time can be readily determined by one skilled in the art. In a typical operation, baking would continue for 24 hours.
The concluding phase of the sequence embodying the practice of the present invention is sealing or encapsulation of the semiconductor devices by known methods employing suitable resins standard for such purposes. An illustrative class of such material is epoxy resins, for example, the polymeric polyepoxides disclosed in US. Patents 2,872,427 and 2,879,235.
The aliphatic amine herein contemplated is purified so as to make it substantially free of metallic impurities such as tin, iron, and lead, which may be present in the unpurified product. Purification may be eflected by various known methods. In the case of triethylenetetramine, it has been found that a triple distillation will reduce the tin content to 1.7 parts per million (p.p.m.), the iron content to about 1 p.p.m., well within the prescribed limits.
Semiconductor rectifiers produced in accordance with the present process show consistently low leakage values.
Although the passivating procedure of the invention has been described in terms of the foregoing specific embodiments, it will be evident that various modifications thereof may be devised by those proficient and skilled in the art which will also be encompassed Within the scope and spirit of this invention.
What is claimed is:
1. In a process for passivating a semiconductor surface which comprises washing the surface in an acid solution, sequentially rinsing the surface with an aqueous solution and an organic solvent, drying and varnish-coating the surface, and curing the varnish coating to produce the passivated semiconductor, the improvement comprising rinsing said surface in an aqueous solution having a pH of from 5.5 to 7.2 and containing an aliphatic polyamine selected from the group consisting of triethylenetetramine, ethylene diamine, triethylene diamine, and hexylene diamine, said polyamine being substantially free of metallic contaminants.
2. The process as claimed in claim 1 wherein the aliphatic polyamine contains not more than three parts per million of metallic impurities.
3. The process as claimed in claim 1, in which the aqueous solution contains said aliphatic polyamine in an amount of from .001 to 5 percent by volume of the solution.
4. The process as claimed in claim 1, in which the varnish coating is constituted of a silicone varnish having incorporated therein said aliphatic polyamine in an amount of from .001 to 5 percent by volume of the silicone.
5. The process as claimed in claim 1, in which the aqueous solution contains said aliphatic polyamine in an amount of about one percent by volume of the solution.
Gildersleeve: Surface Treatment of Transistors, R.C.A. Technical Note No. 25, August 9, 1957.

Claims (1)

1. IN A PROCESS OF PASSIVATING A SEMICONDUCTOR SURFACE WHICH COMPRISES WASHING THE SURFACE IN AN ACID SOLUTION, SEQUENTLY RINSING THE SURFACE WITH AN AQUEOUS SOLUTION AND AN ORGANIC SOLVENT, DRYING AD VARNISH-COATING THE SURFACE, AND CURING THE VARNISH COATING TO PRODUCE THE PASSIVATED SEMICONDUCTOR, THE IMPROVEMENT COMPRISING RINSING SAID SURFACE IN AN AQUEOUS SOLUTION HAVING A PH OF FROM 5.5 TO 7.2 AND CONTAINING AN ALIPHATIC POLYAMINE SELECTED FROM THE GROUP CONSISTING OF TRIETHYLENETETRAMINE, ETHYLENE DIAMINE, TRIETHYLENE DIAMINE, AND HEXYLENE
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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3212939A (en) * 1961-12-06 1965-10-19 John L Davis Method of lowering the surface recombination velocity of indium antimonide crystals
US3296503A (en) * 1962-01-17 1967-01-03 Telefunken Patent Semiconductor stabilized mechanically and electrically by a first layer of lacquer and a second layer of boric oxide
US3505181A (en) * 1963-05-29 1970-04-07 Secr Defence Brit Treatment of titanium surfaces
US3518132A (en) * 1966-07-12 1970-06-30 Us Army Corrosive vapor etching process for semiconductors using combined vapors of hydrogen fluoride and nitrous oxide
JPS5132275B1 (en) * 1969-09-30 1976-09-11
US4199649A (en) * 1978-04-12 1980-04-22 Bard Laboratories, Inc. Amorphous monomolecular surface coatings
FR2598257A1 (en) * 1986-05-05 1987-11-06 Gen Electric PROCESS FOR THE PASSIVATION OF THE REVERSE CHANNEL OF AMORPHOUS SILICON FIELD EFFECT TRANSISTORS.
US5972724A (en) * 1994-09-12 1999-10-26 Temic Telefunken Microelectronic Gmbh Process for reducing the surface recombination speed in silicon

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2874076A (en) * 1955-08-18 1959-02-17 Hughes Aircraft Co Semiconductor translating devices
US2913358A (en) * 1958-07-21 1959-11-17 Pacific Semiconductors Inc Method for forming passivation films on semiconductor bodies and articles resulting therefrom

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2874076A (en) * 1955-08-18 1959-02-17 Hughes Aircraft Co Semiconductor translating devices
US2913358A (en) * 1958-07-21 1959-11-17 Pacific Semiconductors Inc Method for forming passivation films on semiconductor bodies and articles resulting therefrom

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3212939A (en) * 1961-12-06 1965-10-19 John L Davis Method of lowering the surface recombination velocity of indium antimonide crystals
US3296503A (en) * 1962-01-17 1967-01-03 Telefunken Patent Semiconductor stabilized mechanically and electrically by a first layer of lacquer and a second layer of boric oxide
US3505181A (en) * 1963-05-29 1970-04-07 Secr Defence Brit Treatment of titanium surfaces
US3518132A (en) * 1966-07-12 1970-06-30 Us Army Corrosive vapor etching process for semiconductors using combined vapors of hydrogen fluoride and nitrous oxide
JPS5132275B1 (en) * 1969-09-30 1976-09-11
US4199649A (en) * 1978-04-12 1980-04-22 Bard Laboratories, Inc. Amorphous monomolecular surface coatings
FR2598257A1 (en) * 1986-05-05 1987-11-06 Gen Electric PROCESS FOR THE PASSIVATION OF THE REVERSE CHANNEL OF AMORPHOUS SILICON FIELD EFFECT TRANSISTORS.
US5972724A (en) * 1994-09-12 1999-10-26 Temic Telefunken Microelectronic Gmbh Process for reducing the surface recombination speed in silicon
US6340642B1 (en) 1994-09-12 2002-01-22 Temic Telefunken Microelectronics Gmbh Process for manufacturing a silicon semiconductor device having a reduced surface recombination velocity

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