US3062971A - Negative resistance diode building block for logic circuitry - Google Patents

Negative resistance diode building block for logic circuitry Download PDF

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US3062971A
US3062971A US845274A US84527459A US3062971A US 3062971 A US3062971 A US 3062971A US 845274 A US845274 A US 845274A US 84527459 A US84527459 A US 84527459A US 3062971 A US3062971 A US 3062971A
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current
voltage
diode
building block
magnitude
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Jr Robert L Wallace
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AT&T Corp
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Bell Telephone Laboratories Inc
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Priority to US845274A priority patent/US3062971A/en
Priority to DEW28507A priority patent/DE1141334B/de
Priority to FR839789A priority patent/FR1271825A/fr
Priority to GB33981/60A priority patent/GB966757A/en
Priority to BE595800A priority patent/BE595800A/fr
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/04—Control of transmission; Equalising
    • H04B3/16—Control of transmission; Equalising characterised by the negative-impedance network used
    • H04B3/18—Control of transmission; Equalising characterised by the negative-impedance network used wherein the network comprises semiconductor devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/10—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using tunnel diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/313—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductor devices with two electrodes, one or two potential barriers, and exhibiting a negative resistance characteristic
    • H03K3/315—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of semiconductor devices with two electrodes, one or two potential barriers, and exhibiting a negative resistance characteristic the devices being tunnel diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • FIG 5B INVENTOR By R. L. WALLACE, JR. T HvJ A TTORNEV Nov. 6, 1962 R. L. WALLACE, JR 3,062,971
  • This invention relates to a building block for a widespread variety of circuit configurations and has for its general object the simplification of circuit design.
  • a further object of the invention is to facilitate the construction of ultrahigh frequency devices by realizing the building block in the form of a compact integral unit. Such a unit allows ease of replacement and minimizes space and power requirements. It is advantageously employed in miniaturized digital apparatus such as computers.
  • a still further object is to increase the capability and utility of bistable and gating circuits by the novel interconnection of two or more building blocks.
  • the building block of the present invention is characterized by having only two external terminals between which are only three elements: a negative resistance, voltage-controlled crystal diode, an inductance element and a resistor.
  • the diode which is the central element of the building block has a current-voltage characteristic with three regions. In the first, which exhibits a positive resistance, an increase in voltage from zero is accom panied by an increase in current until a current maximum is reached. Then the characteristic enters its negative resistance portion so that a further increase in voltage is accompanied by a decrease in current until a current minimum is reached. At the latter point, the characteristic turns upward and thereafter, for further increase in the voltage, continuously displays a positive resistance. While a single value of current may have multiple voltages identified with it, there is but one current for a specified voltage so that the characteristic is said to be voltagecontrolled.
  • a typical and appropriate diode for the building block is composed of two semiconducting materials with a narrow junction between them. Impurities are added to dope the materials in such a way as to produce a unique voltage-controlled negative resistance characteristic.
  • the theory of the diode is more fully explained in a report of Leo Esaki in the Physical Review, 1958, vol. 109, page 603.
  • the narrow junction which makes possible the negative resistance at high frequencies has associated with it a relatively high capacitance. Nevertheless, the high frequency limit of the diode is not solely a function of the capacitance. It is dependent on the negative resistance-capacitance product which may be controlled by proper doping. Switching speeds manyfold higher than formerly possible with negative resistance devices are now attainable.
  • the integral unit of the invention is produced by placing a negative resistance diode of the Voltage-controlled type in parallel with the series combination of an inductance element and a resistive element.
  • the magnitudes of the resistive and inductive elements depend upon the particular use to which the block is put and are discussed in detail below in conjunction with the novel embodiments proposed.
  • the building block is made up of lumped circuit elements.
  • the building block is made up of lumped circuit elements.
  • it is a compo-site structure.
  • a resinous material is placed between two holders which serve as a mount for a semiconductor diode.
  • the resin is extruded from between them to form at their outer Patented Nov. 6, 1962 edges a disk-like solid of revolution.
  • the series combination of distributed resistance and inductance results from depositing on the surface of the solid of revolution a resistive layer which encircles the holders at the level of the gap between them.
  • the inductance may be altered by adjusting the geometry of the surface, or by changing the composition of the resin. It may be made variable by including magnetically polarizable ferrite elements within the resinous solids formed.
  • FIG. 1 is a diagram of a typical negative resistance, voltage-controlled diode which is a central constituent of the present invention
  • FIG. 2 is a set of curves portraying actual and idealized characteristics for the diode of FIG. 1;
  • FIG. 3 is an equivalent circuit diagram for explaining the operation of the diode of FIG. 1;
  • FIG. 4 is a schematic circuit diagram of the building block of the invention.
  • FIG. 5a is an idealized equivalent circuit diagram for the building block operated in its negative resistance condition
  • FIG. 5b is an idealized equivalent circuit diagram for the building block operated in its positive resistance condition
  • FIG. 6 is a set of curves illustrating the way in which the direct current characteristics of the building block are affected by changes in padding resistor magnitude
  • FIG. 7a is a complex frequency domain for the building block operated in its negative resistance condition and is used in explaining the functioning of the invention.
  • FIG. 7b is the time domain corresponding to the complex frequency domain of FIG. 7a;
  • FIG. 7c is a complex frequency domain for the building block operated in its positive resistance condition and is used in explaining the functioning of the invention.
  • FIG. 7d is the time domain corresponding to the complex frequency domain of FIG. 7c;
  • FIG. 8a is a symbolic representation of a circuit embodying the invention, e.g., a bistable circuit or an AND gate;
  • FIG. 8b is a characteristic curve for the bistable or AND gate circuit of FIG. 8a.
  • FIG. 9a is a set of curves demonstrating the effect on pole location in the complex frequency domain of changes in inductance when the AND gate circuit of FIG. 8a is operated in its negative resistance condition;
  • FIG. 9b is a set of curves demonstrating the effect on pole location in the complex frequency domain for changes in inductance when the AND gate circuit of FIG. 8a is operated in its positive resistance condition;
  • FIG. 96 is a time response curve of the AND gate of FIG. 8a for typical parameters
  • FIG. 10 is a symbolic representation of a circuit comprising a chain of two driving building blocks, each separately interconnected with a driven building block by a coupling impedance;
  • FIG. 11 is a schematic diagram of a bistable circuit formed by serially connecting two building blocks of the invention.
  • FIG. 12a is a composite characteristic curve for two serial-1y connected building blocks illustrating the operation of the circuit of FIG. 11;
  • FIGS. 12b and are characteristic curves for individual building blocks constituting the bistable circuit of FIG. 11;
  • FIG. 13 is a cross sectional view of a microwave embodiment of the building block of FIG. 4.
  • FIG. 14 is a cross sectional view of a microwave embodiment of the bistable circuit of FIG. 11.
  • the invention may be best understood by beginning with a consideration of the voltage-controlled negative resistance diode around which the building block is formed.
  • the illustrative diode 3 of FIG. 1 is biased in its forward direction by a battery 4, connected across terminals 1 and 2, so that a wafer 5 of n-type germanium semiconductor is at a negative potential with respect to a mesa 6 of deposited metal.
  • a narrow p-n junction 7 is formed between the mesa 6 and the body 5 of the wafer.
  • the battery 4 which supplies the voltage bias may be varied to obtain the characteristic curves of FIG. 2.
  • the first component, a of FIG. 2 is jointly attributable in part to the high field intensity associated with narrow p-n junctions and the high concentration of diode impurity atoms. It is produced by the seemingly anomalous penetration of the high energy barrier at the junction by lower energy carriers. Quantum mechanics teaches that there is always a calculable probability of finding such behavior within a restricted voltage interval. The narrower the diode junction, and the greater its impurity concentration, the higher is the probability of barrier penetration. Quantum mechanical phenomena are small scale,
  • Summation of the currents a and b gives a composite current 0 whose idealized N-shaped characteristic starts at the currentvoltage origin V I reaches a maximum V, I, turns downward to a minimum V, I and thereafter rises continuously with increasing voltage.
  • the magnitude of the positive resistance between points V I and V, I: is the reciprocal of the slope of the line segment between them. Other resistive magnitudes are similarly calculated.
  • the shape of the N and the points of maximum and minimum current may be adjusted by controlled doping of the diode materials.
  • the idealized characteristic 0 allows constructing the equivalent circuit of FIG. 3 for piece-wise linear analysis. Between break points where the slope of the characteristic c in FIG. 2 abruptly changes, linear equations apply. Switches 8-1, 8-2 and 83, respectively, control positive resistor R positive resistor R 2, and negative resistor R. In addition the condenser C represents the selfcapacitance of the diode 3 in FIG. 1 to account for the A.-C. behavior of the diode in contrast with its D.-C. behavior. If the strength of the current source 4 between terminals 1 and 2 of diode 3 in FIG. 1 is gradually increased from zero, the locus of operation in FIG.
  • the building block which lies at the root of the present invention is constructed as shown in FIG. 4.
  • Diode 3 of FIG. 1 is shunted across its terminals 1 and 2 by the series combination of a padding resistor R and an inductor L.
  • FIG. 5a The characteristic impedance 2, appears between terminals 1 and 2 of FIG. 4, and may be written:
  • C magnitude of the diode capacitance
  • R magnitude of the diode negative resistance
  • R magnitude of padding resistor
  • L magnitude of inductance
  • the condenser C Starting at quiescent voltage V the condenser C begins to charge until V is reached and only the incremental current AI is flowing through C. Thereafter, the voltage continues to increase along locus h to terminal voltage V where all of the current divides between diode positive resistor R and building block padding resistor R and C is fully charged.
  • FIG. 6 The information obtainable from FIG. 6 is primarily limited to the direct current effect of padding resistor R on the building block of FIG. 4.
  • inductor L For the influence of inductor L on the rate at which changes of voltage state take place, reference must be made to the separate domains of FIGS. 7a through 7d dealing with the operation of the building block in its conditions of positive and nega tive resistance.
  • poles designated by x's in the complex frequency domain of FIG. 7a, are determined from the roots of Equation 2.
  • the roots are in the form:
  • Equation 2 Since the mag nitude of resistor R will always be greater than that of diode resistor -R, 3 in Equation 6 will always be negative so that:
  • Equation 3 When the building block is operated in its positive resistance condition, the roots of Equation 3 give pole locations which must always lie in the left half of the complex frequency domain in FIG. 70.
  • the roots are in the form:
  • FIG. 8a illustrates a building block connected to serve as an AND gate or as a bistable network, depending on parameter selection. For AND gating a summation of input current pulses greater than a predetermined maximum causes the output voltage of the gate to suddenly change from a low to a high magnitude.
  • terminal 1 of building block 11 four distinct leads, 12, 13, 14 and 15, are connected to terminal 1 of building block 11.
  • Terminal 12 allows the application of a biasing current I from a voltage source V through a resistor R of large magnitude.
  • Terminals 13 and 14 are similarly connected to pulsing sources of current I and I respectively.
  • Output voltage V: is measured at terminal 15 across a large resistor R preferably of infinite resistance as would be provided by the input terminals of an isolation amplifier.
  • the magnitude of the biasing source I is selected to place the operation of the AND gate at a low voltage operating point V shown at an abrupt change accounting for any increased curvature in the slope of the positive resistance characteristic of FIG. 8b.
  • FIG. 8a demonstrates bistability if the activating current 1, is reduced to zero and bias current I is gradually raised to I giving the quiescent output voltage V' at terminal 15.
  • a driving current pulse of Y brings about a change of voltage state to V where it remains even after reduction of current I' to zero.
  • a negative pulse I' causes a restoration of the original equilibrium voltage V'
  • L L CR R where symbols are as for Equation 2 and L is the inductive magnitude for which 0 :0.
  • L the second derivative of the reciprocal of switching speed with respect to inductance is substantially zero.
  • n of FIG. 9a asymptotically approach a limiting value.
  • FIG. 912 for the building block in its positive resistance condition, there are two sets of negative poles in the interval:
  • FIG. 90 Another factor in the transient buildup is the size of the current pulse. It is a multiplicative coeflicient of the exponential terms making up the solution.
  • L The magnitude of L has been taken by reference to FIGS. 9:: and 9b as /2L or in a representative case 2(10 henries.
  • the coupling network is chosen to be only the coupling resistor R,, rapid switching is assured if there is a composite negative resistance R at terminals 1-2 and 1-3. Assuming that neither driving building block appreciably loads the other, this requires:
  • Equation 11 is derived by calculating the total current through a driving building block and R in terms of the input voltage V.
  • R' magnitude of composite negative resistance at terminal 1-2 or 1-3
  • R R R internal resistance of voltage sources V V V respectively.
  • an isolating intermediate amplifier A or a coupling inductor L may be chosen as the only element of the coupling network in FIG. 10.
  • An amplifier suitable for rapid switching such as a maser or similar microwave device, prevents undesirable interaction of the building blocks and allows each driving unit to activate a multiple of driven ones.
  • a coupling inductor also avoids direct current loading, though it is accompanied by a time delay in the appearance of an output voltage across driven Q building blocks, thus giving the AND gate chain the effect of a delay line.
  • the versatility of the building blocks may be further demonstrated by connecting a multiple number of them serially to produce a multistable circuit. When only two of them are placed in series the result is the bistable circuit of FIG. 11.
  • pulses in one direction only can effect an interchange of building block voltage states at the close of a switching interval.
  • the biasing resistor R taken in combination with battery E is appropriately adjusted to place the operating steady state in the middle of a composite characteristic according to techniques discussed below.
  • Capacitor C serves to bypass battery E for high frequency currents and helps maintain constant potential at the battery terminals. It is important that the source of driving pulses be placed directly across the serial combination of the building blocks in order to minimize power requirements.
  • FIGS. 12a-12c show the composite characteristic of two building blocks whose individual characteristics are represented respectively by FIG. 12b for block 111 and FIG. 12c for block 11-2.
  • Region aa of the composite characteristic applies when both blocks are in a low voltage state.
  • region bb is applicable when both blocks are in a high voltage state.
  • the narrow region cc extending between I and I is operative when one block is in its high voltage state and the other is in its low voltage state. If the building blocks were other than identical, there would be more than one region such as cc. To be bistable the circuit of FIG. 12a must have its load line dd adjusted to intersect segment cc.
  • the time sequence is approximated on the loci at five points, t through t Corresponding points are indicated on the switching patterns in FIGS. 12b and for the individual building blocks. Ideal loci are designated ff-1 and ;ff2 and the actual loci are marked gg-l and gg2.
  • the building block inductors play important parts in controlling the change of state during switching. When both diodes have been driven to their low voltage state at kk the current in L is greater than that in L because it was initially greater and the tendency of an inductor is to maintain its current flow unchanged.
  • Equation 1 the rate of voltage change as measured by the magnitude of current flowing in each diode intrinsic capacitor is intially greater in building block 111 than in building block 11-2, so that the former rapidly makes the transition to the high voltage state and constrains the latter to a low voltage equilibrium, thereb completing the switching cycle.
  • diode 3 is positioned between two holders 19-1 and 19-2 which act as terminals 1 and 2 of the building block. The diode is mounted at the base of metal pin 18-1 and the combination is inserted into a channel in the holder 19-1 until the diode mesa is in touching contact with a dia- 1 1 phragm 20 at the apex of a pin 18-2 inserted into a similar channel in the holder 192.
  • the resin is extruded from the gap between them at their outer periphery and expands into a toroidal solid of revolution which may be made as large as needed for a specific structure. It may be dissymmetrically machined to various geometries and the resin itself may have materials added to alter the electrical characteristics of the circuit. Since the toroidal surface spans from one holder to another a resistive coating deposited on it will be directly across the terminals of the building block. Each incremental arc of the coating provides part of the path for an inductive circulating current which is impeded by the resistive nature of the coating. The incremental inductance and resistance may be summed over the entire surface to produce the same effect at microwave frequencies that the series combination of an inductor and resistor has at low frequencies. It is also possible to produce a variable inductance, for example, by inserting a ferrite slab within the toroid and subjecting it to a variable magnetic bias field.
  • the high frequency embodiment of the building block is usable in a wide variety of circuits. Typical is the bistable circuit of FIG. 11 whose microwave embodiment is presented in FIG. 14 and Whose mode of operation has been discussed previously.
  • a short-circuit termination 23 caps one end of a cylindrical outer conductor 24.
  • Two building blocks 11-1 and 112 are placed in series combination by being stacked one on top of the other and are interposed between the shortcircuit termination 23 and a center conducting coaxial segment 25 of a coaxial section.
  • each building block differs from the prototype of FIG. 13 in having a toroid of rectangular, instead of elliptical, cross section. This permits a reduced diameter for the outer coaxial conductor 24.
  • the combined building blocks may be manufactured as a single unit.
  • a battery E is connected across the terminals of the feeder coaxial line 26.
  • the inner conductor of the feeder abuts an annular resistive disk 27 which serves as bias resistor R
  • the disk is co-extensive with the surface of inner conductor 25 and provides a direct current link with battery E through both building blocks.
  • Dielectric disk 28 extends between the inner and outer conductors of the feed line, and being a high frequency by-pass condenser C its axial dimension is dependent on the wall thickness of outer coaxial conductor 23.
  • the coaxial section is tapered to provide an impedance match with a source of pulsing current I which causes an interchange between the voltage states of the two building blocks after input pulses are applied and terminated.
  • Adjustments such as in the taper, may be made to offset the discontinuity effects occasioned by the presence of the annular resistive disk 27.
  • the change in voltage state produced by current pulses L is monitored across an output coaxial line 29 whose center conductor joins the serially combined building blocks between their toroidal surfaces.
  • FIG. 14 assures input pulsing, direct current bias and the availability of output directly across the diode building block 11-1 with minimum circuit complexity.
  • An electronic threshold switch responsive to signals from an excitation source and a biasing source, which comprises a first terminal and a second terminal, a first branch extending between said terminals and containing a diode having a current-voltage characteristic manifesting a region of negative resistance between first and second regions of positive resistance, a first threshold between the first region of positive resistance and said region of negative resistance, and a second threshold between said region of negative resistance and the second region of positive resistance, said diode being set by a biasing signal for bistable operation in two alternative states of stable equilibrium, whereby an excitation signal carrying the operation of said diode beyond one of the thresholds initiates a transition from one state to another, and control means extending between said terminals, said control means comprising a padding resistor connected in shunt with said diode and proportioned to have a maximum resistive magnitude greater than the minimum resistive magnitude of said negative resistance for controlling the relative displacement of said first threshold from said second threshold to regulate the magnitude of said excitation signal which effects said transition, said padding resistor unavoid
  • a logic circuit comprising the network of claim I, a source of bias current and a plurality of variable current sources connected in shunt with said network, each of said sources comprising the series combination of a resistor of large magnitude and a voltage source, said bias current source being proportioned to place said network in stable equilibrium at a low voltage operating point, said several variable current sources being so proportioned that only the simultaneous presence of all of the plurality exceeds a threshold current thereby causing a rapid transition of said network from a low voltage state to a high voltage state, and means for detecting said transition.
  • R positive resistance for building block diode
  • R magnitude of padding resistor
  • L inductive magnitude of reactive means
  • C magnitude of the diode capacitance
  • said inductive means comprises an inductor so proportioned that its inductance L is dependent upon the diode capacitance C, padding resistance R and negative resistance magnitude R in substantial accordance with the formula:
  • a circuit to perform logic functions comprising a plurality of driving components each having a network as defined in claim 1 in parallel with at least two sources of driving current, at least one driven component having a network as defined in claim 1, means for supplying bias currents to all of said components, and coupling means interconnecting each one of said driving components with said driven component whereby changes of voltage states of said driving components cause like changes of voltage state in said driven component.
  • said coupling means comprises a series resistor R of predetermined magnitude whereby a composite negative resistance is presented at the input terminals at any one of said components.
  • R magnitude of the diode negative resistance
  • R positive resistance for building block diode
  • R magnitude of padding resistor
  • each of said driving components comprises a voltage source connected in series with a resistor of magnitude R proportioned according to the relationship:
  • R magnitude of the composite negative resistance presented at the terminals of each of said driving components as loaded by every other one of said com ponents.
  • a bistable switching circuit comprising a first branch wherein first and second networks as defined in claim 1 are connected in series with each other thereby having the same current flowing through both to produce a composite characteristic with a first region of positive resistance in which both of said networks are in a low voltage state, a second region of positive resistance in which both of said networks are in a high voltage state and a third region therebetween extending between a current minimum and a current maximum in which one of said networks is in a low voltage state and the other is in a high voltage state; a second branch, in shunt with said first branch wherein a biasing resistor is connected in series with a source of bias voltage thereby causing said bistable circuit to be in equilibrium in said third region whereby said first network is in a high voltage state and said second network is in a low voltage state; and a third branch, in shunt with said first branch, having pulsing means for momentarily reducing said current in said first branch whereby said first network is driven to its low voltage state for which its inductive current exceeds
  • a switching network comprising a first terminal, a second terminal, a first branch extending between said terminals and containing only a crystal diode having a voltage-controlled region of negative resistance R between first and second regions of positive resistance R and R a current maximum between said first region of positive resistance R and said region of negative resistance R, and a current minimum between said region of negative resistance R and said second region of positive resistance R means for biasing said diode for bistable operation, whereby said diode adopts either a low voltage state of stable equilibrium in said first region of positive resistance R or a high voltage state of stable equilibrium in said second region of positive resistance R and a second branch extending between said terminals and containing a padding resistor whose resistive magnitude R is greater than that of said diode negative resistance R, thereby controlling the magnitude of the difference between said current maximum and said current minimum and regulating the magnitude of excitation current which efiects a rapid voltage transition from either one of said regions of positive resistance to the other, and means for controlling the rate of said rapid voltage transition, said means
  • T time constant of a rising exponential wave during switching through said positive resistance condition, and a" ,B'.
  • An integral high frequency building block for performing logic functions comprising a crystal diode mounted between first and second distinct terminal holders, said holders being closely spaced from each other by a dielectric film thereby to assure a minimal inductance of the distributed parameter type between said diode and the outer peripheries of said holders in the surfaces of said film, a dielectric body spanning the spacing between said holders and in touching contact therewith only at said peripheries said body being an extrusion of said film between said holders, inductive and resistive means on the surface of said body comprising a coating of the distributed parameter type whereby controlled amounts of inductance and resistance are effectively connected in series across said terminals of said building block, said controlled amount of inductance being significantly greater than said minimal inductance.
  • a high speed switching unit which comprises a crystalline wafer having a negative resistance of the voltage-controlled type, two mounting plates disposed in substantially parallel arrangement and in contact, respectively, with opposite faces of said wafer, a body of solid low-loss dielectric material surrounding said wafer, substantially filling the remaining space between said plates, and extending beyond the peripheries of said plates, the configuration of the surface of said body being that swept out by the rotation, through a full revolution about an axis perpendicular to the opposite faces of said wafer, of a key-hole shaped figure lying in a plane including said perpendicular axis, and a film of conductive material of preassigned resistivity overlying the entire surface of said body that is not included between said plates and in electrical contact, at its edges, with the peripheries of said plates, whereby said body, with its resistive film, manifests the properties of distributed resistance and inductance, connected to said plates and in parallel with said wafer.
  • a switching network which comprises two like, similarly poled, bistable circuits connected in series between a first terminal and a second terminal, each of said circuits comprising two parallel branches, the first branch of each circuit containing only a crystal diode, the second branch of each circuit containing only an inductor and a padding resistor, connected in series, each of said diodes having a current-voltage characteristic of the voltagecontrolled type, having a current maximum for a lower voltage V a current minimum for a higher voltage V a negative resistance branch joining said maximum to said minimum, a first positive resistance branch for voltages less than said lower voltage and a second positive resistance branch for voltages above said higher voltage, means for applying across said first and second terminals a bias voltage V of a magnitude substantially equal to whereby one of said diodes adopts a first stable state in which its voltage is less than V and the other diode adopts a second stable state in which its voltage is greater than V the currents flowing through said series-connected circuits being alike, each of said resistors being proportioned
  • a microwave bistable switching circuit comprising a cylindrical outer conductor, a short-circuit termination at one end thereof, the series combination of two integral high frequency building blocks as defined in claim 18 mounted coaxially with said outer conductor between said short-circuit termination and a coaxial inner conductor, a resistive disk interposed between said inner and outer conductors, a feeder coaxial line joining said cylindrical outer conductor at a right angle thereto and having its inner conductor in contact with said disk whereby a voltage source across said feeder line causes a biasing current to circulate through said series combination of building blocks thus placing one of said blocks in its high voltage state and the other in its low voltage state, a dielectric disk between the conductors of said feeder line and presenting at high frequencies a by-pass capacitance across said voltage source, a unidirectional source of current pulses between said inner and outer conductors, a tapered section of coaxial line between said source of pulses and said disk providing matching means to compensate for discontinuities occasioned by the presence of said disk, and means for utilizing the

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US845274A 1959-10-08 1959-10-08 Negative resistance diode building block for logic circuitry Expired - Lifetime US3062971A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
NL256639D NL256639A (en(2012)) 1959-10-08
US845274A US3062971A (en) 1959-10-08 1959-10-08 Negative resistance diode building block for logic circuitry
DEW28507A DE1141334B (de) 1959-10-08 1960-09-05 Elektronischer Schalter
FR839789A FR1271825A (fr) 1959-10-08 1960-09-28 Unité de montage comprenant une diode à résistance négative pour circuits logiques
GB33981/60A GB966757A (en) 1959-10-08 1960-10-04 Improvements in or relating to two terminal switching networks and logic circuits employing such networks
BE595800A BE595800A (fr) 1959-10-08 1960-10-06 Bloc de construction à diode à résistance négative pour circuits logiques

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NL (1) NL256639A (en(2012))

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3209158A (en) * 1960-02-08 1965-09-28 Ibm Tunnel diode shift registers
US3214604A (en) * 1960-06-21 1965-10-26 Gen Electric Tunnel diode-saturable reactor control circuit
US3218474A (en) * 1962-05-23 1965-11-16 Ibm Uni-directional tunnel diode circuits
US3221179A (en) * 1960-08-31 1965-11-30 Ibm Tunnel diode not circuits
US3230385A (en) * 1959-11-27 1966-01-18 Rca Corp Unidirectional signal propagation circuit including negative resistance elements
US3234398A (en) * 1960-10-03 1966-02-08 Ibm Tunnel diode binary counters
US3241009A (en) * 1961-11-06 1966-03-15 Bell Telephone Labor Inc Multiple resistance semiconductor elements
US3253156A (en) * 1962-12-26 1966-05-24 Bell Telephone Labor Inc Controlled multistate circuits
US3255449A (en) * 1961-02-17 1966-06-07 Siemens Ag Circuit arrangement for converting an analog value into an n-place binary number
US3996484A (en) * 1975-09-05 1976-12-07 The United States Of America As Represented By The Secretary Of The Navy Interactive negative resistance multiple-stable state device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2614140A (en) * 1950-05-26 1952-10-14 Bell Telephone Labor Inc Trigger circuit
US2772360A (en) * 1954-02-11 1956-11-27 Bell Telephone Labor Inc Negative resistance device
US2899646A (en) * 1959-08-11 Tread
US2986724A (en) * 1959-05-27 1961-05-30 Bell Telephone Labor Inc Negative resistance oscillator

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2899646A (en) * 1959-08-11 Tread
US2614140A (en) * 1950-05-26 1952-10-14 Bell Telephone Labor Inc Trigger circuit
US2772360A (en) * 1954-02-11 1956-11-27 Bell Telephone Labor Inc Negative resistance device
US2986724A (en) * 1959-05-27 1961-05-30 Bell Telephone Labor Inc Negative resistance oscillator

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3230385A (en) * 1959-11-27 1966-01-18 Rca Corp Unidirectional signal propagation circuit including negative resistance elements
US3209158A (en) * 1960-02-08 1965-09-28 Ibm Tunnel diode shift registers
US3214604A (en) * 1960-06-21 1965-10-26 Gen Electric Tunnel diode-saturable reactor control circuit
US3221179A (en) * 1960-08-31 1965-11-30 Ibm Tunnel diode not circuits
US3234398A (en) * 1960-10-03 1966-02-08 Ibm Tunnel diode binary counters
US3255449A (en) * 1961-02-17 1966-06-07 Siemens Ag Circuit arrangement for converting an analog value into an n-place binary number
US3241009A (en) * 1961-11-06 1966-03-15 Bell Telephone Labor Inc Multiple resistance semiconductor elements
US3218474A (en) * 1962-05-23 1965-11-16 Ibm Uni-directional tunnel diode circuits
US3253156A (en) * 1962-12-26 1966-05-24 Bell Telephone Labor Inc Controlled multistate circuits
US3996484A (en) * 1975-09-05 1976-12-07 The United States Of America As Represented By The Secretary Of The Navy Interactive negative resistance multiple-stable state device

Also Published As

Publication number Publication date
DE1141334B (de) 1962-12-20
NL256639A (en(2012))
GB966757A (en) 1964-08-12
BE595800A (fr) 1960-10-31

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