US2970228A - Timing circuit - Google Patents

Timing circuit Download PDF

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US2970228A
US2970228A US721273A US72127358A US2970228A US 2970228 A US2970228 A US 2970228A US 721273 A US721273 A US 721273A US 72127358 A US72127358 A US 72127358A US 2970228 A US2970228 A US 2970228A
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electrode
base
diode
transistor
emitter
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US721273A
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Marshall P White
Robert D Talbot
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CBS Corp
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Westinghouse Electric Corp
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/14—Modifications for compensating variations of physical values, e.g. of temperature

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  • This invention relates to timing circuits in general and in particular to static timing circuits.
  • the drawing is a schematic diagram of a static, semiconductor timing circuit which is temperature and voltage compensated, illustrating the teachings of this invention.
  • the apparatus illustrated in the drawing comprises input means 15 having terminal means and input transistor means 20, intermediate transistor means 30, double base diode means 64 voltage compensating means 40 and 7t), and output transistor means 80.
  • the input transistor means 20 comprises an emitter electrode 21, a collector electrode 22 and a base electrode 23.
  • the emitter electrode 21 is connected to a common conductor or ground.
  • the collector electrode 22 is connected through a resistance 25 and a resistance 35 to a negative or B- bias supply.
  • the base electrode 23 is connected to the input terminal 10 and to a positive or B+ bias supply through a current limiting resistor 24.
  • the intermediate transistor means 30 comprises an emitter electrode 31, a collector electrode 32, and a base electrode 33.
  • the emitter electrode 31 is connected through a resistor 34 and the resistor 35 to the B- supply.
  • the emitter electrode 31 is connected to the base electrode 33 through the resistor 34.
  • the collector electrode 32 is connected through a current limiting resistor 36 to the B+ supply.
  • the base electrode 33 is connected through the resistor 25 to the collector electrode 22 of the input .transistor 20.
  • the voltage compensating or constant voltage means all comprises a semiconductor diode connected across the collector 32-emitter 31 circuit of the intermediate transistor 3d.
  • the semiconductor diode 40 is connected to utilize its Zener type breakdown effect to maintain a constant voltage across the diode 4t) in spite of normal bias supply variation in a reverse direction.
  • a capacitive means 50 is connected through a current limiting resistor 52 and a potentiometer 53 across the collector 32-emitter 31 circuit of the transistor 3%.
  • a rectifying means 51 is connected in shunt across the resistor 52 and the potentiometer 53.
  • the double base diode or unijunction transistor means 60 comprises an emitter electrode 61, a first base electo States atent O far Q trode 62 and a second base electrode 63.
  • the capacitor 51) is connected through a resistor 54 and a rectifier 66 across the emitter 61-first base electrode 62 circuit of the double base diode 60.
  • the emitter electrode 61 of the double base diode 60 is connected through a rectifying means 65, a potentiometer 42, a resistor 41 and the resistor 36 to the 13+ supply. This applies a constant voltage from the diode 46* to the emitter 61-first base 62 circuit or" the double base diode 60.
  • the second base electrode 63 is connected through a resistor 67 and a resistor 68 to the B+ supply.
  • the first base electrode 62 is connected through a resistor 71 to the B- supply.
  • a semiconductor diode 76 similar or identical to the semiconductor diode 4%, is connected between common or ground through a resistor 71 to the B- supply.
  • the semiconductor diode 7i functions in the same fashion as the semiconductor diode 40 by means of a Zener type breakdown to hold a constant voltage across the diode 70 in a reverse direction.
  • the output transistor 1% comprises an emitter electrode 81, a collector electrode 82 and a base electrode 8.3.
  • the emitter electrode '81 is connected to ground.
  • the collector electrode 82 is connected through the output terminal lltill and a resistor $5 to the B supply.
  • the base electrode 83 is connected through the resistor 67 to the second base electrode 53 of the double base diode 6d.
  • the base electrode 83 is also connected through a rectifying means 84 to ground.
  • the transistor means 20, 3t) and 8t) utilized in the preferred embodiment of this invention are, as illustrated, of the three electrode type commonly used for switching purposes. That is the direct-current voltage to be switched is connected to two of said three electrodes. In response to a bias voltage of the proper polarity and magnitude, applied between the third and one of said two electrodes, conduction is allowed in the said two electrode circuits.
  • P-N-P or N-PN types are illustrated, N-PN and P-NP types, respectively, may be used with the proper reversal of bias supply polarity connections in a manner well known to those skilled in the art.
  • the energy storage means or capacitor 50 is fully charged with electrical energy and that the semiconductor diode do is holding its full Zener voltage thereacross.
  • a negative input signal is applied to the input terminal it Since the input transistor 2% is illustrated .to be of the P-NP type, the application of this negative'signalof the proper magnitude to the base electrode 23 will allow conduction in the emitter Iii-collector 22 circuit of the transistor 20. Conduction in the emitter Zl-collector 22 circuit of the transistor it through the resistors 25 and 35 will apply a positive bias to the base. electrode 33 of the transistor 39 with respect to the emitteriil.
  • the transistor 30 Since the transistor 30 is illustrated as the N-P-N type, the application of a positive bias of the proper magnitude to the base electrode 33 will allow conduction in the collector 32-emitter 31 circuit. Therefore the input means 15 functions to bias said intermediate transistor means 3% .to conduction.
  • the transistor 80 Since the transistor 80 is of the PNP type, the positive bias applied to the base electrode 83 thereof will stop conduction in the emitter fil-collector 32 circuit of the transistor 80, and an output will appear at the terminal 100 with respect to ground. This output for the timing circuit will be nearly the value of the B supply with no load connected to the output terminal 16%.
  • the input transistor 26 When the negative input signal at the terminal 10 is removed, the input transistor 26 is biased to cutoff by the B+ supply through the current limiting resistor 24. When the conduction through the emitter 21-collector 22 circuit of the transistor 24) ceases, the transistor 30 is biased to cutofi by the voltage drop across resistor 34.
  • the voltage across the resistor 34 is a fraction of the drop across resistor 71. This fraction is determined by the resistors 34 and 35 and the leakage of the transistor 30.
  • the resistor 34 is connected between the emitter 31 and the base electrode 33 of the transistor 30 to prevent-the base electrode 33 from becoming too negative with respect to the emitter 31.
  • the potentiometer 42 is adjusted so that the voltage appearing at the emitter electrode 61 of the double base diode 60 is slightly below the voltage necessary to fire the double base diode 60.
  • the rectifying means 66 prevents charging of the capacitor 56 through the potentiometer 4-2 whenever the voltage across the capacitor is below the voltage or potential at the emitter electrode 61 of the double base diode 60.
  • the rectifier 65 prevents current flow to the potentiometer 42 when the voltage across the capacitor it raises the potential of the emitter 61 of the double base diode 60 above the voltage already set by the potentiometer 42.
  • the capacitor 56 When the capacitor 56 charges to the firing potential of the double base diode 60, the capacitor 50 discharges through the emitter til-first base 62 circuit of the double base diode 60, and the potential at the emitter electrode 61 drops. Current then flows from the potentiometer 42 through the rectifier 65, holding the double base diode 60 in a conducting state.
  • the transistor 80 When the double base diode 60 fires the first base 62 to second base 63 impedance becomes low, allowing the application of a negative biasing potential of the base electrode 83 of the transistor 80. Therefore, the transistor 80 will conduct in its emitter 81-collector 82 circuit and will short the output at the terminal 100 or remove the output from the timing circuit as illustrated in the drawing.
  • the resistor 67 connected between the second base electrode 63 of the double base diode 60 and the base electrode 83 of the transistor 80 aids in the resetting process of the double base diode 60 When an input is applied to the terminal 10, as hereinbefore described, and the transistor 80 is desired to be cut E.
  • the function of the semiconductor diode 70 is to keep variation in the supply voltages from afiecting the firing point of the double base diode 60. If the voltage at the second base electrode 63 with respect to the emitter electrode 61 can be kept constant before firing, the voltage at which the double base diode 60 fires can be accurately reproduced and is independent of temperature.
  • the impedance 67 may be a positive coeflicient thermistor to compensate for the slight increase with temperature of the interbase impedance of the double base diode 60.
  • the circuit will oscillate unless the resistor 71 is added.
  • the resistor 71 increases the time available for the circuit to supply the current to keep the double base diode 60 conducting.
  • the rectifier 84 functions to prevent the back emitter voltage on the transistor from becoming excessive when the transistor 80 is cutoff.
  • the double base diode 60 is used as a bistable device. If the emitter 61 resistance is made too large the circuit will operate in a non-stable condition and will oscillate.
  • the resistor 41 and the potentiometer 42 may be viewed as supplying current to keep the double base diode 60 on or providing a low impedance load line after the double base diode 60 has fired to insure bistable operation. If the emitter 61 resistance was solely determined by the charging resistors 41 and 42, the charging resistance value would be limited to a maximum value determined by the value of resistance at which the operation of the double base diode 6t switched from bistable to mon0- stable operation. The timer would then have a very limited range for a given value capacitance.
  • a timing circuit has been described which is accurate, reliable and easily adjustable over a considerable timing range by the setting of the potentiometer 53. Since the circuit is comprised of static semiconductor components, it has inherent maintenancefree, long-life qualities.
  • a timing circuit in combination; input means for applying a signal to said timing circuit; intermediate and output transistor means each having three electrodes; double base diode means having an emitter electrode, a first base electrode and a second base electrode; electrical energy storage means; and means connecting bias supply means to said timing circuit; said energy storage means being connected to charge from said bias supply means; said intermediate transistor means having two of its said three electrodes connected to discharge said energy storage means in response to a signal applied to said input means; said energy storage means upon discharge being connected through isolating rectifier means to regulate conduction between said first and second base electrodes of said double base diode means; said output transistor means being connected to said first and second base electrodes of said double base diode so that conduction therethrough controls the output state of said output transistor means; said bias supply being connected to supply bias potential to said intermediate transistor means, said output transistor means, and said double base diode means; said bias supply means being connected between said emitter and first base electrode means of said double base diode means through isolating rectifier means.
  • a timing circuit in combination; input means for applying a signal to said timing circuit; intermediate and output transistor means each having three electrodes; double base diode means having an emitter electrode, a first base electrode and a second base electrode; electrical energy storage means; and means connecting bias supply means to said timing circuit; said energy storage means being connected to charge from said bias supply means through constant voltage means; said intermediate transistor means having two of its said three electrodes connected to discharge said energy storage means in response to a signal applied to said input means; said energy storage means upon discharge being connected through isolating rectifier means to regulate conduction between said first and second base electrodes of said double base diode means; said output transistor means being connected to said first and second base electrodes of said double base diode so that conduction therethrcugh controls the output state of said output transistor means; said bias supply being connected to supply bias potential to said intermediate transistor means, said output transistor means, and said double base diode means; said bias supply means being connected between said emitter and first base electrode means of said double base diode means through isol
  • input means comprising input switching transistor means for applying a signal to said timing circuit; intermediate and out put transistor means each having three electrodes; double base diode means having an emitter electrode, a fir t base electrode and a second base electrode; electrical energy storage means; and means connecting bias supply means to said timing circuit; said energy storage means being connected to charge from said bias supply means through constant voltage means; said intermediate transistor means having two of its said three electrodes connected to discharge said energy storage means through isolating rectifier means shunting charging resistor means for said energy storage means in response to a signal applied to said input means; said energy storage means upon discharge being connected through isolating rectifier means to regulate conduction between said first and second base electrodes of said double base diode means; said output transistor means being connected to said first and second base electrodes of said double base diode so that conduction therethrough controls the output stage of said output transistor means; said bias supply being connected to supply bias potential to said intermediate transistor means, said output transistor means, and said double base diode means

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Description

Jan. 31, 1961 M. P. WHITE ET AL 2,970,228
TIMING CIRCUIT Filed March 13, 1958 CD to 4% WITNESSES INVENTORS Marshall P. White 8\ Robert D. Talbot Maw... El. QSLJQQJ ATTORNEY T G CIRCUIT Marshall P. White, Grand Haven, Mich, and Robert D. Talbot, Hamburg, N.Y., assignors to Westinghouse Electric Corporation, East Pittsburgh, Pa., a corpora tion of Pennsylvania Filed Mar. 13, 1958, Ser. No. 721,273
'5 Claims. (Cl. 307-885) This invention relates to timing circuits in general and in particular to static timing circuits.
It is an object of this invention to provide an improved static timing circuit.
it is another object of this invention to provide an improved static timing circuit which is accurate, very reliable and easily adjustable over a considerable timing range.
It is still another object of this invention to provide an improved static timing circuit which is temperature and voltage compensated.
Further objects of this invention will become apparent from the following description when taken in conjunction with the accompanying drawing. In said drawing, for illustrative purposes only, there is shown a preferred embodiment of the invention.
The drawing is a schematic diagram of a static, semiconductor timing circuit which is temperature and voltage compensated, illustrating the teachings of this invention.
In general, the apparatus illustrated in the drawing comprises input means 15 having terminal means and input transistor means 20, intermediate transistor means 30, double base diode means 64 voltage compensating means 40 and 7t), and output transistor means 80.
The input transistor means 20 comprises an emitter electrode 21, a collector electrode 22 and a base electrode 23. The emitter electrode 21 is connected to a common conductor or ground. The collector electrode 22 is connected through a resistance 25 and a resistance 35 to a negative or B- bias supply. The base electrode 23 is connected to the input terminal 10 and to a positive or B+ bias supply through a current limiting resistor 24.
The intermediate transistor means 30 comprises an emitter electrode 31, a collector electrode 32, and a base electrode 33. The emitter electrode 31 is connected through a resistor 34 and the resistor 35 to the B- supply. The emitter electrode 31 is connected to the base electrode 33 through the resistor 34. The collector electrode 32 is connected through a current limiting resistor 36 to the B+ supply. The base electrode 33 is connected through the resistor 25 to the collector electrode 22 of the input .transistor 20.
The voltage compensating or constant voltage means all comprises a semiconductor diode connected across the collector 32-emitter 31 circuit of the intermediate transistor 3d. The semiconductor diode 40 is connected to utilize its Zener type breakdown effect to maintain a constant voltage across the diode 4t) in spite of normal bias supply variation in a reverse direction. A capacitive means 50 is connected through a current limiting resistor 52 and a potentiometer 53 across the collector 32-emitter 31 circuit of the transistor 3%. A rectifying means 51 is connected in shunt across the resistor 52 and the potentiometer 53.
The double base diode or unijunction transistor means 60 comprises an emitter electrode 61, a first base electo States atent O far Q trode 62 and a second base electrode 63. The capacitor 51) is connected through a resistor 54 and a rectifier 66 across the emitter 61-first base electrode 62 circuit of the double base diode 60. The emitter electrode 61 of the double base diode 60 is connected through a rectifying means 65, a potentiometer 42, a resistor 41 and the resistor 36 to the 13+ supply. This applies a constant voltage from the diode 46* to the emitter 61-first base 62 circuit or" the double base diode 60. The second base electrode 63 is connected through a resistor 67 and a resistor 68 to the B+ supply. The first base electrode 62 is connected through a resistor 71 to the B- supply. A semiconductor diode 76, similar or identical to the semiconductor diode 4%, is connected between common or ground through a resistor 71 to the B- supply. The semiconductor diode 7i functions in the same fashion as the semiconductor diode 40 by means of a Zener type breakdown to hold a constant voltage across the diode 70 in a reverse direction.
The output transistor 1% comprises an emitter electrode 81, a collector electrode 82 and a base electrode 8.3. The emitter electrode '81 is connected to ground. The collector electrode 82 is connected through the output terminal lltill and a resistor $5 to the B supply. The base electrode 83 is connected through the resistor 67 to the second base electrode 53 of the double base diode 6d. The base electrode 83 is also connected through a rectifying means 84 to ground.
The transistor means 20, 3t) and 8t) utilized in the preferred embodiment of this invention are, as illustrated, of the three electrode type commonly used for switching purposes. That is the direct-current voltage to be switched is connected to two of said three electrodes. In response to a bias voltage of the proper polarity and magnitude, applied between the third and one of said two electrodes, conduction is allowed in the said two electrode circuits. Although P-N-P or N-PN types are illustrated, N-PN and P-NP types, respectively, may be used with the proper reversal of bias supply polarity connections in a manner well known to those skilled in the art.
Assume that .the energy storage means or capacitor 50 is fully charged with electrical energy and that the semiconductor diode do is holding its full Zener voltage thereacross. A negative input signal is applied to the input terminal it Since the input transistor 2% is illustrated .to be of the P-NP type, the application of this negative'signalof the proper magnitude to the base electrode 23 will allow conduction in the emitter Iii-collector 22 circuit of the transistor 20. Conduction in the emitter Zl-collector 22 circuit of the transistor it through the resistors 25 and 35 will apply a positive bias to the base. electrode 33 of the transistor 39 with respect to the emitteriil. Since the transistor 30 is illustrated as the N-P-N type, the application of a positive bias of the proper magnitude to the base electrode 33 will allow conduction in the collector 32-emitter 31 circuit. Therefore the input means 15 functions to bias said intermediate transistor means 3% .to conduction.
Conduction in the collector 32-emitter 3i circuit of the transistor 3d will short the Zener voltage from the semiconductor diode and allow instantaneous discharge of the stored electrical energy of the capacitor 50 through the rectifying means 51. The discharge of the capacitor $4 resets the double base diode by placing the emitter electrode 61 and the first base electrode 62 of the double base diode 6d at the same potential. Therefore, the first base 62 to second base 63 impedance of the double base diode 60 will increase and decrease conduction therethrough. The non-conduction of the double base diode 63 places a positive bias of the proper magnitude on the base electrode 83 with respect to the emitter 81 of the transistor 80. Since the transistor 80 is of the PNP type, the positive bias applied to the base electrode 83 thereof will stop conduction in the emitter fil-collector 32 circuit of the transistor 80, and an output will appear at the terminal 100 with respect to ground. This output for the timing circuit will be nearly the value of the B supply with no load connected to the output terminal 16%.
When the negative input signal at the terminal 10 is removed, the input transistor 26 is biased to cutoff by the B+ supply through the current limiting resistor 24. When the conduction through the emitter 21-collector 22 circuit of the transistor 24) ceases, the transistor 30 is biased to cutofi by the voltage drop across resistor 34. The voltage across the resistor 34 is a fraction of the drop across resistor 71. This fraction is determined by the resistors 34 and 35 and the leakage of the transistor 30. The resistor 34 is connected between the emitter 31 and the base electrode 33 of the transistor 30 to prevent-the base electrode 33 from becoming too negative with respect to the emitter 31.
When conduction stops in the collector 32-emitter 31 circuit of the intermediate transistor 30, voltage from the B+ supply is again applied across the semiconductor diode 40 in the reverse direction, and the capacitor 50 starts to charge through the potentiometer 53 and the current limiting resistor 52..
The potentiometer 42 is adjusted so that the voltage appearing at the emitter electrode 61 of the double base diode 60 is slightly below the voltage necessary to fire the double base diode 60. The rectifying means 66 prevents charging of the capacitor 56 through the potentiometer 4-2 whenever the voltage across the capacitor is below the voltage or potential at the emitter electrode 61 of the double base diode 60. The rectifier 65 prevents current flow to the potentiometer 42 when the voltage across the capacitor it raises the potential of the emitter 61 of the double base diode 60 above the voltage already set by the potentiometer 42.
When the capacitor 56 charges to the firing potential of the double base diode 60, the capacitor 50 discharges through the emitter til-first base 62 circuit of the double base diode 60, and the potential at the emitter electrode 61 drops. Current then flows from the potentiometer 42 through the rectifier 65, holding the double base diode 60 in a conducting state.
When the double base diode 60 fires the first base 62 to second base 63 impedance becomes low, allowing the application of a negative biasing potential of the base electrode 83 of the transistor 80. Therefore, the transistor 80 will conduct in its emitter 81-collector 82 circuit and will short the output at the terminal 100 or remove the output from the timing circuit as illustrated in the drawing.
For a more detailed description of the construction, operation and characteristics of a double base diode which may be utilized in this invention, reference is made to An Introduction to Semiconductors, by W. C. Dunlap, Jr., pp. 365-367, published by John Wiley and Sons, Inc., New York, 1957.
The resistor 67 connected between the second base electrode 63 of the double base diode 60 and the base electrode 83 of the transistor 80 aids in the resetting process of the double base diode 60 When an input is applied to the terminal 10, as hereinbefore described, and the transistor 80 is desired to be cut E.
The function of the semiconductor diode 70 is to keep variation in the supply voltages from afiecting the firing point of the double base diode 60. If the voltage at the second base electrode 63 with respect to the emitter electrode 61 can be kept constant before firing, the voltage at which the double base diode 60 fires can be accurately reproduced and is independent of temperature. The impedance 67 may be a positive coeflicient thermistor to compensate for the slight increase with temperature of the interbase impedance of the double base diode 60.
For certainvalues of the capacitor 50 the circuit will oscillate unless the resistor 71 is added. The resistor 71 increases the time available for the circuit to supply the current to keep the double base diode 60 conducting.
The rectifier 84 functions to prevent the back emitter voltage on the transistor from becoming excessive when the transistor 80 is cutoff.
The double base diode 60 is used as a bistable device. If the emitter 61 resistance is made too large the circuit will operate in a non-stable condition and will oscillate. The resistor 41 and the potentiometer 42 may be viewed as supplying current to keep the double base diode 60 on or providing a low impedance load line after the double base diode 60 has fired to insure bistable operation. If the emitter 61 resistance was solely determined by the charging resistors 41 and 42, the charging resistance value would be limited to a maximum value determined by the value of resistance at which the operation of the double base diode 6t switched from bistable to mon0- stable operation. The timer would then have a very limited range for a given value capacitance.
A timing circuit has been described which is accurate, reliable and easily adjustable over a considerable timing range by the setting of the potentiometer 53. Since the circuit is comprised of static semiconductor components, it has inherent maintenancefree, long-life qualities.
In conclusion, it is to be noted that while the illustrated example constitutes a practical embodiment of our invention, we do not limit ourselves to the exact details shown, since modification of the same may be varied without departing from the spirit and scope of this invention.
We claim as our invention:
1. In a timing circuit, in combination; input means for applying a signal to said timing circuit; intermediate and output transistor means each having three electrodes; double base diode means having an emitter electrode, a first base electrode and a second base electrode; electrical energy storage means; and means connecting bias supply means to said timing circuit; said energy storage means being connected to charge from said bias supply means; said intermediate transistor means having two of its said three electrodes connected to discharge said energy storage means in response to a signal applied to said input means; said energy storage means upon discharge being connected through isolating rectifier means to regulate conduction between said first and second base electrodes of said double base diode means; said output transistor means being connected to said first and second base electrodes of said double base diode so that conduction therethrough controls the output state of said output transistor means; said bias supply being connected to supply bias potential to said intermediate transistor means, said output transistor means, and said double base diode means; said bias supply means being connected between said emitter and first base electrode means of said double base diode means through isolating rectifier means.
2. In a timing circuit, in combination; input means for applying a signal to said timing circuit; intermediate and output transistor means each having three electrodes; double base diode means having an emitter electrode, a first base electrode and a second base electrode; electrical energy storage means; and means connecting bias supply means to said timing circuit; said energy storage means being connected to charge from said bias supply means through constant voltage means; said intermediate transistor means having two of its said three electrodes connected to discharge said energy storage means in response to a signal applied to said input means; said energy storage means upon discharge being connected through isolating rectifier means to regulate conduction between said first and second base electrodes of said double base diode means; said output transistor means being connected to said first and second base electrodes of said double base diode so that conduction therethrcugh controls the output state of said output transistor means; said bias supply being connected to supply bias potential to said intermediate transistor means, said output transistor means, and said double base diode means; said bias supply means being connected between said emitter and first base electrode means of said double base diode means through isolating rectifier means.
3. in a timing circuit, in combination; input means for applying a signal to said timing circuit; intermediate and output transistor means each having three electrodes; double base diode means having an emitter electrode, a first base electrode and a second base electrode; electrical energy storage means; and means connecting bias supply means to said timing circuit; said energy storage means being connected to charge from said bias supply means through constant voltage means; said intermediate transistor means having two of its said three electrodes connected to discharge said energy storage means through isolating rectifier means shunting charging resistor means for said energy storage means in response to a signal applied to said input means; said energy storage means upon discharge being connected through isolating rectifier means to regulate conduction between said first and second base electrodes of said double base diode means; said output transistor means being connected to said first and second base electrodes of said double base diode so that conduction therethrough controls the output stage of said output transistor means; said bias supply being connected to supply bias potential to said intermediate transistor means, said output transistor means, and said double base diode means; said bias supply means being connected between said emitter and first base electrode means of said double base diode means through isolating rectifier means.
4. In a timing circuit, in combination; input means comprising input switching transistor means for applying a signal to said timing circuit; intermediate and out put transistor means each having three electrodes; double base diode means having an emitter electrode, a fir t base electrode and a second base electrode; electrical energy storage means; and means connecting bias supply means to said timing circuit; said energy storage means being connected to charge from said bias supply means through constant voltage means; said intermediate transistor means having two of its said three electrodes connected to discharge said energy storage means through isolating rectifier means shunting charging resistor means for said energy storage means in response to a signal applied to said input means; said energy storage means upon discharge being connected through isolating rectifier means to regulate conduction between said first and second base electrodes of said double base diode means; said output transistor means being connected to said first and second base electrodes of said double base diode so that conduction therethrough controls the output stage of said output transistor means; said bias supply being connected to supply bias potential to said intermediate transistor means, said output transistor means, and said double base diode means: said bias supply means being applied between said emitter and first base electrode means of said double base diode means through isolating rectifier means.
5. In a timing circuit, in combination; input means comprising input switching transistor means for applying a signal to said timing circuit; intermediate and output transistor means each having three electrodes; double base diode means having an emitter electrode, a first base electrode and a second base electrode; electrical energy storage means; and means connecting bias supply means to said timing circuit; said energy storage means being connected to charge from said bias supply means through constant voltage means; said intermediate transistor means having two of its said three electrodes connected to discharge said energy storage means through isolating rectifier means shunting charging resistor means for said energy storage means in response to a signal applied to said input means; said energy storage means upon discharge being connected through isolating rectifier means to regulate conduction between said first and second base electrodes of said double base diode means; said output transistor means being connected to said first and second base electrodes of said double base diode so that conduction therethrough controls the output stage of said output transistor means; said bias supply being connected to supply bias potential to said intermediate transistor means, said output transistor means, and said double base diode means; said bias supply means being connected between said emitter and first base electrode means of said double base diode means through isolating rectifier means; the value of said bias applied to said emitter and first base electrode means of said double base diode means being less than the firing voltage of said double base diode means.
References Cited in the file of this patent UNITED STATES PATENTS 2,801,338 Keller July 30, 1957 2,801,340 Keonjian et a1 July 30, 1957 2,833,938 Pinckaers May 6, 1958 2,840,727 Guggi June 24, 1958 2,845,548 Silliman et al July 29, 1958 2,878,440 Jones Mar. 17, 1959 2,892,101 Bright June 23, 1959
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US3109125A (en) * 1961-06-29 1963-10-29 Ncr Co Electrical control circuit
US3113250A (en) * 1960-07-28 1963-12-03 Morton Salt Co Transistor control circuit
US3125707A (en) * 1964-03-17 culbertson
US3142004A (en) * 1960-08-24 1964-07-21 Theodore W Hallerberg Transistor timing device
US3204153A (en) * 1962-05-15 1965-08-31 Lockheed Aircraft Corp Relaxation divider
US3244991A (en) * 1962-12-07 1966-04-05 Cons Electrodynamics Corp Demodulator for fm signals utilizing pulse forming circuitry
US3284788A (en) * 1964-02-17 1966-11-08 Elastic Stop Nut Corp Flow rate monitoring systems
US3315246A (en) * 1964-01-20 1967-04-18 Gen Signal Corp Signal absence detection circuit
US3319127A (en) * 1964-10-12 1967-05-09 Ite Circuit Breaker Ltd Static overcurrent relay
US3351811A (en) * 1962-01-15 1967-11-07 Bendix Corp Speed responsive apparatus
US3454794A (en) * 1967-01-30 1969-07-08 Honeywell Inc Timing circuit employing variable offset linear ramp generating means
US3461325A (en) * 1966-12-07 1969-08-12 Litton Systems Inc Switching apparatus for measuring an atmospheric variable
US3852646A (en) * 1970-12-28 1974-12-03 Design Elements Inc Solenoid drive circuit
FR2456429A1 (en) * 1979-05-10 1980-12-05 Sony Corp TIMING CIRCUIT
US4542284A (en) * 1983-01-07 1985-09-17 Windmere Corporation Electrical appliance with delayed warning alarm

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Cited By (17)

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US3125707A (en) * 1964-03-17 culbertson
US3106666A (en) * 1959-09-23 1963-10-08 Kuckens Electrical time switching apparatus
US3018384A (en) * 1960-06-13 1962-01-23 William E Zrubek Transistor circuit for converting pulse information into bistable information
US3113250A (en) * 1960-07-28 1963-12-03 Morton Salt Co Transistor control circuit
US3142004A (en) * 1960-08-24 1964-07-21 Theodore W Hallerberg Transistor timing device
US3109125A (en) * 1961-06-29 1963-10-29 Ncr Co Electrical control circuit
US3351811A (en) * 1962-01-15 1967-11-07 Bendix Corp Speed responsive apparatus
US3204153A (en) * 1962-05-15 1965-08-31 Lockheed Aircraft Corp Relaxation divider
US3244991A (en) * 1962-12-07 1966-04-05 Cons Electrodynamics Corp Demodulator for fm signals utilizing pulse forming circuitry
US3315246A (en) * 1964-01-20 1967-04-18 Gen Signal Corp Signal absence detection circuit
US3284788A (en) * 1964-02-17 1966-11-08 Elastic Stop Nut Corp Flow rate monitoring systems
US3319127A (en) * 1964-10-12 1967-05-09 Ite Circuit Breaker Ltd Static overcurrent relay
US3461325A (en) * 1966-12-07 1969-08-12 Litton Systems Inc Switching apparatus for measuring an atmospheric variable
US3454794A (en) * 1967-01-30 1969-07-08 Honeywell Inc Timing circuit employing variable offset linear ramp generating means
US3852646A (en) * 1970-12-28 1974-12-03 Design Elements Inc Solenoid drive circuit
FR2456429A1 (en) * 1979-05-10 1980-12-05 Sony Corp TIMING CIRCUIT
US4542284A (en) * 1983-01-07 1985-09-17 Windmere Corporation Electrical appliance with delayed warning alarm

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