US2935732A - Sorting apparatus - Google Patents

Sorting apparatus Download PDF

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US2935732A
US2935732A US427167A US42716754A US2935732A US 2935732 A US2935732 A US 2935732A US 427167 A US427167 A US 427167A US 42716754 A US42716754 A US 42716754A US 2935732 A US2935732 A US 2935732A
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input
output
tape
gate
messages
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Howard P Guerber
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RCA Corp
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RCA Corp
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Priority to BE537869D priority Critical patent/BE537869A/xx
Priority to NL196972D priority patent/NL196972A/xx
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Priority to US427167A priority patent/US2935732A/en
Priority to US440692A priority patent/US2907003A/en
Priority to GB12684/55A priority patent/GB772274A/en
Priority to FR1130250D priority patent/FR1130250A/fr
Priority to CH347031D priority patent/CH347031A/de
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
    • G06F7/24—Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers sorting methods in general
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S707/00—Data processing: database and file management or data structures
    • Y10S707/99931—Database or file accessing
    • Y10S707/99937—Sorting

Definitions

  • H. P. GUERER somma APPARATUS Filed may :5. 1954
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  • the information stored on the tapes is in random order. It is often desired to sort this information into some predetermined sequence. For example, in many of the automatic billing and inventory Systems a continuous record of tne transactions occurring during a designated ⁇ billing period is maintained as they occur, The transactions herein termed messages may consist of remittances from customers, changes in customer address, additional purchases made by the customer, etc. Each message is identified ⁇ by a code symbol which may be alphabetic or numeric or both. The sorting of the messages into an orderly arrangement can be an expensive and time consuming operation.
  • a prior art method of sorting the stored messages comprised the steps of successively subdividing the messages into a plurality of groups. The groups are then subdivided into a number of smaller groups until finally each group consists of a single message. This method requires a large number of input-output media for the sorting operation.
  • a complete regrouping of all the messages appearing on the input tapes is herein termed a pass
  • the messages are sorted into groups of two; on the second pass, the messages are sorted into groups of four; on the third pass, into groups of eight, ctc.
  • the number of passes required before sorting is completely assured varies with the number of messages appearing on the primary tape and may be determined from the expression 2m1 n 21n where m represents the number of passes and n represents the number of messages.
  • the Strings of Two method of sorting requires the use of two input tapes which together are passed through the device and two output tapes on which the messages appear in a rearranged grouping. Before sorting is started the messages recorded on the primary tape are transferred to two input tapes, each input tape receiving one half of the messages.
  • the messages are regrouped in groups of two on the output tapes.
  • Each group of two messages is composed of one message from each of the input tapes. Odd groups are recorded on the first of the output tapes, and even groups are recorded on the second of the output tapes.
  • the output tapes are used as the input tapes.
  • the groups of two messages are regrouped into groups of four on two output tapes. Each group of four messages is composed of two messages from each of the input tapes. Again, odd groups are recorded on the first of the output tapes, and even groups are recorded on the second of the output tapes.
  • the messages are regrouped into groups of eight on the output tapes, and so on. The messages of a group are maintained in sequential order within the group in which they are located.
  • serial number 23 is compared with serial number 24, and the rnessages are then transferred to tape D appearing in sequence as 23, 24.
  • the reading, comparing, and transferring of two messages at each step is continued during the first pass until all the messages have been recorded in groups of two alternately appearing on tapes C and l) as shown in Table III.
  • the two output tapes C and D become the input tapes.
  • the original input tapes A and B if suitably erased may be used as the output tapes.
  • the erasing heads may be placed either on the input tapes or on the output tapes.
  • serial number 2 of tape C is compared with serial number 23 of tape D. As serial number 2 is the smaller, the message thus identified on tape C is transferred to one of the output tapes, for instance, tape A, of Table IV below. However, unlike the first pass. the message designated by serial number 23 of tape D is not then transferred. Instead, tape C is advanced one position and serial number 7 is compared with serial number 23. As 7 is the smaller of the two, the message thus identied on tape C will also be transferred to tape A1. Operation of tape C is then stopped because the output group ou the second pass is to be composed of two messages from each of the input tapes.
  • serial numbers 23 and 24 of tape D are then transferred one after the other to the output tape A1.
  • the four messages recorded on tape A1 are recorded in numerical order.
  • serial number ll of tape C is compared with serial number 6 of tape D.
  • the message thus identified on tape D is transferred to the second of the output tapes, for instance B1 of Table lV below.
  • Tape D is then advanced one position and serial number l7 of tape D compared with serial number 1l of tape C.
  • serial number 11 is the smaller, the message thus identified on tape C is transferred to tape B1.
  • Tape C is then advanced one position and serial number 17 is compared with serial number ⁇ l8.
  • serial number i7 As serial number i7 is the smaller, the message thus identified on tape D is transferred to tape B1. Operation of tape D is then stopped as two messages appearing thereon have been transferred to the output tape B1. At the same time, tape C is advanced one position and the message identified by serial number i8 is transferred to output tape B1. The procedure of sorting the groups of two messages appearing on each of the input tapes into a single sequential group of four alternately on one or the other of the output tapes is continued until the second pass is completed. The resorted messages appear on output tapes A1 and B1 as indicated by Table IV below.
  • tapes A1 and B become the input tapes.
  • tapes C and D if suitably erased. ⁇ may be used as the output tapes.
  • the messages are regrouped alternately on the output tapes in groups of eight. Each group of eight messages is composed of four messages from each of the input tapes. The procedure of comparing the serial numbers and transferring the message identified by the smaller is carried out as explained in the description of the second pass except that four messages are transferred from each input tape to a single output tape. The messages appear on the output tapes designated as tape C, and tape D1 of Table V below TABLE V Tape C; Tape Dt During the fourth pass, the messages are regrouped on the output tapes in groups of 16. The above described procedure of comparing and transferring is followed on the fourth pass except that eight messages are transferred from each input tape to a single output tape. Thus, the sixteen messages selected for the example appear in numerical sequence on one of the output tapes.
  • the messages may be grouped in descending order by selecting the message identified by the larger serial number for transfer to the output tape.
  • a group end code may be provided to insure against a possibility of missorting which may occur due to the malfunctioning of the input tape advance mechanism.
  • the group end code serves to identify each pass and insures that the proper number of messages are transferred from each input tape during the particular pass.
  • the group end code would cause the input tapes to advance in a staggered fashion one message position at a time.
  • the group end code would not allow the input tapes to advance more than two message positions at a time and so on.
  • Progressive Sorting takes advantage of the high probability that small groups of the messages will have been initially recorded in sequential order oa the primnrv tape. Thus, some saving in time can be made by exploiting the initial order of the groups of messages during the sorting process. Also, progressive sorting may commence either with the two input tapes or with the primary tape.
  • the serial number of the first message on tape A is compared with the serial number of the first message on tape B.
  • the smaller of the two causes its tape (assume tape A) to be ad vanced one position and the first message is transferred to one of the output tapes.
  • the smaller serial number is transferred to a third memory or register of any suitable type.
  • the second message of tape A is now in position to be compared with the first message of tape B because only tape A advanced after the first cornparison.
  • c is the serial number of the message stored in the memory
  • a is the larger of the serial numbers of the input messages
  • the Progressive Sorting method is self correcting. Thus, if one of the serial numbers should happen to appear out of order on an output tape due to a malfunction, it starts a new sequence during the next assembling operation. The error is not repeated, as in the case in the Strings of Two method.
  • a detailed example of Progressive Sorting is provided in the diagram of Fig. 6 which is self-explanatory.
  • CODING Presently known machines and computers of the digital type usually change information which is being supplied to the machine or computer from the form in which it is customarily handled, namely, alphabetic and/or numerio to a code which may be more conveniently handled by the machine.
  • the code presently preferred is a binary type because the binary digits zero and one are easily represented by the condition of an element which has two distinct stable states. Commonly used binary elements are relays and flip-flop circuits. Accordingly in the present invention, the messages may be encoded on the tape in the binary system of notation.
  • Either paper or magnetic tape may be used. If paper tape is used, a binary one may be represented by a perforation in the paper and a binary zero may be represented by the absence of a perforation. lf magnetic tape is used, the so-called non-return-to-zero method of recording may be employed. This method represents a binary one by the presence of a magnetized spot on the tape and a binary zero by the absence of a magnetized spot.
  • Magnetic tape is preferred in the present instance because the input tapes may then readily be erased and re-used as the output tapes on the next succeeding pass.
  • a group of characters arranged in series upon the tape may represent a word, a multi-digit number or special informative symbols herein termed an item.
  • a message may be represented by a group of one or more items which in turn may consist of a group of one or more characters.
  • a start message and end message symbol may be recorded at the beginning and the end of each message.
  • Another object of the present invention is to provide an improved electronic apparatus for sorting messages which are stored on magnetic or perforated tape into some predetermined sequence.
  • Still another object of this invention is the provision of an etcient sorting apparatus wherein only a portion of a message need be read into a storage register.
  • a still further object of the present invention is to provide a rapid sorting apparatus which causes a selected one of the messages encoded on each of two input tapes to be transferred to one of two output tapes.
  • Yet another object of the present invention is to provide a novel apparatus which maintains the messages in sequential groups on the output tapes.
  • Still another object of the present invention is to provide a novel means for sorting serially stored messages appearing on each of two input tapes into sequential groups in alphabetical or numerical sequence on each of two output tapes and repeatedly merging each of the output groups into still larger sequential groups during subsequent passes, until all of the messages finally appear in a single sequential group on one of the output tapes.
  • An additional object of the present invention is to provide an improved electronic sorting apparatus which operates asynchronously to sort messages recorded on two input tapes into a predetermined sequence on one or more output tapes.
  • each storage register may have a capacity sutilcient to store any desired portion of the message.
  • the sorting criterion is set out in the first eight characters of each message.
  • the sorting criterion may be alphabetic or numeric and is referred to hereinafter as the serial number of the message. Therefore, the capacity of the register need be only as great as the Serial number of a message. Because each character is composed of six bits, each storage register is arranged to store forty-eight bits.
  • the storage registers are connected to a comparator wherein the serial numbers of the messages are compared one with the other. Because the characters are to be arranged on the tape in order ot decreasing rank. the characters within the serial number are compared serially, and the bits within the characters are compared in parallel. Thus, the iirst characters of the serial nurnbers are brought out from the registers to the comparator. The highest ranking bits of these iirst characters are compared; if they are equal. the next two bits are compared; and so on.
  • the comparator sends an appropriate signal to condition one of two gates, upon the receipt of the eighth character of the serial number being read, the gate thus conditioned sends a signal to reset the appropriate register and to the appropriate tape advance mechanism to cause the corresponding input tape to advance.
  • the message is brought under the second of the reading heads individual to the advancing tape and is read out to one of the output tapes.
  • the Strings of Two sorting method requires that the messages be retained in groups on the output tapes. Proper grouping of the messages is insured by two predetermined message counters.
  • the predetermined counters are advanced one power of. two for each pass. Thus, on the first pass, the counters allow only one message to be read from each of the input tapes, on the second pass two messages, etc.
  • each of the predetermined counters is connected to an and gate. Upon the completion of each group, the and gate actuates a switch thereby causing the next group to be recorded on the other of the output tapes.
  • the output of the and" gate also serves to reset the predetermined counters.
  • FIG. 1 is a schematic diagram, in block form, of the general arrangement of an apparatus according to the invention
  • Fig. 2 is a schematic diagram of the arrangement of an input matrix 38a in block form. The components associated with input matrix 38a are also indicated in the drawing;
  • Fig. 3 is a schematic diagram of the arrangement of a storage register 46a in block form
  • Fig. 4 is a schematic diagram of the arrangement of an array of output gates 48a;
  • Fig. 5 is a symbolic illustration of the arrangement of the messages on an input tape
  • Fig. 6 shows an example of the progressive sorting" method
  • Fig. 7 is a schematic diagram of one comparator useful in the apparatus of Fig. l.
  • Each character of the message is defined by a combination of bits in channels 14h-g.
  • Channel 14a is provided for recording an odd-even check bit which is used for error checking purposes.
  • the first character of each message is a start message symbol which is widely used in the telegraph art to condition the apparatus for further operation.
  • a sorting zone may be defined as the length of tape allotted to the number of characters which are set aside for purposes of identifying a particular message.
  • the sorting zone 12 of Fig. 5 is comprised of a start message symbol and the iirst eight characters following thereafter. More or less than eight characters can be set aside for the serial number of the message depending on the number of messages which are to be sorted.
  • the message identifying characters may be alphabetic or numeric or some other arbitrary ordered symbols. However, in the present instance, the binary numbers assigned to the alphabetic characters are larger in binary notation than the binary numbers as signed to the numerical digits 0 to 9.
  • a message which has an alphabetic serial number always has a corresponding binary value which is larger than that 0f a message which has a numerical serial number.
  • An eight character sorting zone allows for the recordation of all serial numbers equal to or less than eight digits or letters.
  • the encoding procedure varies somewhat depending on whether thc serial number is alphabetic or numeric.
  • the serial number is alphabetic, it is encoded on the tape beginning with the rst letter in the name or word. If the name or word is composed of less than eight letters, the unused characters remaining in the sorting zone are filled in with blank symbols or nulls which may be represented by a character having one or more bits.
  • the serial number is numerical, it is increased to au eight digit ruunber by adding su. appropriate number of null symbols to the left of the most significant digit. The number is then encoded on the tape beginning with the first digit on the left.
  • the rst character recorded in the sorting zone is the order determining character of the serial number followed by the remaining characters in order of precedence.
  • the message proper may have any number of characters.
  • the last character of the message proper may be followed by a stop message symbol.
  • the stop message symbol may be omitted in the present embodiment because the tape advance is automatically stopped after the eighth character of the serial designation has been read out by the first reading head 16.
  • Reading head 18 is located a suitable distance beyond reading head 16 in the direction of tape motion.
  • the spacing between the two reading heads is a function of the stop-start characteristic of the tape driving mechanism and the length of the sorting zone. This spacing is employed because during the operation, the apparatus reads the eight characters representing the serial number of a message encoded on input tape before the tape advance is stopped. iowever, the tape driving mechanism cannot be stopped instantly. and therefore continues to move the tape a small distance after the stop signal is received. lf the second reading head were located too close to the first reading head, a portion of the message might come under the second reading head during the stopping interval.
  • the second reading head (18) is always conditioned to read out to the output tape any characters which come beneath it.
  • the drive mechanism cannot immediately bring the tape movement up to the proper recordiny speed because of the inertia of the tape drive mechanism.
  • the necessary start interval is likewise compensated for in the spacing of the second reading head 18. Therefore, the second reading head 18 is located beyond the first reading head 16 in the direction of tape motion and at a distance 24 which is equal to the distance set aside for the sorting zone 12, plus the distance required to bring the tape to a complete stop 20, plus a distance 22 necessary to bring the tape up to a proper recording speed.
  • a portion of tape 1S between the end of one message and the start of the next message is left blank to allow for the spacing between the alpha and beta reading heads.
  • a suitable precision stop-start mechanism is described in copending application Serial No. 248,767 filed by Joseph M. Uritis on September 28, 1951, entitled Valve Actuating Mechanism, now Patent No. 2,750,961, issued .Tune 19, 1956.
  • This mechanism is capable of bringing a tape moving at a velocity of 100 linear inches per second to a complete stop in 5 milliseconds or less.
  • the mechanism described can also bring a tape from cornplete stop to full speed in the same time interval.
  • the mechanism described in the said copending application starts or stops the tape in response to a suitable start or stop pulse respectively.
  • the manner of connection to receive the start or stop pulse of Fig. 1 for the tape drive mechanism will be obvious to those skilled in the art.
  • Figs. la and lb The system shown in Fig. l of the drawings is a generalized block digaram of a preferred apparatus for sorting messages according to the Strings of Two method.
  • the components associated with tape A are designated by a numeral followed by the subscript a.
  • These components which are associated with tape B which are similar and perform similar functions are designated by the same numeral used to denote the corresponding component associated with tape A, but followed by the subscript b.
  • the components which are common to both tape A and tape B are designated by a numeral without any subscript.
  • the arrangement of Fig. l is symmetrical, that is, there are like A and B components, and certain components in common, the latter having no subscripts.
  • the first character of the serial designation is the start message symbol.
  • the rst reading head 16a is a 6 channel reading head and detects the magnetized spots in channels 14b-g of Fig. 5.
  • the magnetized spot which may be present in channel 14a is for oddeven parity check purposes, but a parity check spot is not necessary to the sorting operation, and therefore is not difficult further hereinafter.
  • the connections between the various components are shown as a single line although a plurality of leads may interconnect the various components. The situation where a line represents more than one lead is indicated by the interposed subscripts in the line.
  • the six channels of the first multiple reading head 16a are connected to the inputs of six pulse amplifiers 28a.
  • pulse amplifiers 28a are represented in the schematic drawing of Fig. l as a single block, it is to be understood that the block contains six identical pulse amplifiers, one amplifier being furnished for each of the information channels 14h-g which are encoded on the magnetic tape a.
  • the six channels of the first reading head 16a are connected respectively to the inputs of the six pulse amplifiers 28a.
  • the outputs of the six pulse amplifiers 28a are applied respectively to the inputs of six pulse shapers 40a.
  • Pulse amplifiers and pulse Shapers are well known to those versed in the art and need not be described in detail here.
  • the rounded pulse outputs from the reading heads are converted by the pulse amplifiers 28a and Shapers, 40a to a rectangular waveform. Further information regarding conventional pulse circuits may be obtained by referring to a standard textboel; sach as IWaveforms by Chance et al. infra.
  • the outputs of the pulse Shapers 40a are connected to the inputs of or gate 42a and to the inputs of code recognition gate 26.
  • the code recognition gate 26 may be of the general type described in Patent No. 2,648,829 entitled Code Recognition System issued to William R. Ayres, August ll, 1953.
  • the code recognition gate 26 may be set to respond to any given combination of pulses appearing on the input leads.
  • the code recognition gate 26 is set to respond to the start message symbol, which, for example, may consist of a pulse in each of the six input leads.
  • the output of the code recognition gate 26 is connected via conductor 31 to delay unit 30.
  • the delay unit 30 and the other delay units referred to herein may be of the ⁇ type described in Chapter 22 of Waveforms by Chance et al., published by McGraw- Hill Book Co. or alternatively a delay type multivibrator may be employed.
  • the output of the delay unit 3Q is applied to the set input of Hip-flop 32.
  • Flip-flop 32 and the other bistable flip-flops employed herein may be the well known Eccles-Jordan type or any other suitable bistable state circuits known as triggers or bistable multivibrators.
  • the output lead may be connected to the tube associated with the set input.
  • the flip-flop is shifted to its other stable state and an appropriate output signal is generated.
  • a Subsequent signal applied to the set input is ineffective to produce an appropriate output signal unless the flip-flop has been shifted back to its first stable state by a suitable signal applied to its reset input.
  • the set input is labeled with an S and the reset input is labeled with an R.
  • a suitable flip-Hop arrangement is described in an article by C. H. Page entitled "Digital Computer Switching Circuits, published in Electronics Magazine, September 1948 at page lll.
  • An and gate is one of the logical coincidence circuits which are well known in the electronic computer art. ln the present embodiment, the logical circuits employed are "and gates, or gates, and an and-not gate.
  • An and gate is an electronic circuit which provides an output signal only upon the coincidence of a predetermined number of input signals.
  • An or" gate is an electronic circuit which provides an output signal upon stimulation by one or more input signals. Suitable and gates and or gates are described in an aforementioned article by C. H. Page, supra.
  • the output of and gate 34 is applied to the input of character counter 36.
  • the character counter 36 may be, for example, the "ring counter” which is described in chapter 3 of High Speed Computing Devices, supra.
  • the ring counter is advanced one count for each pulse received at the input.
  • Counter 36 has eight stages, one stage per character of the serial number. Each output of the eight stages is connected to input matrix 38a.
  • Activation of or gate 42a by one or more input pulses from the pulse Shapers 42a results in a single output pulse.
  • This output pulse is conducted to one of the inputs of and gate 34. If and gate 34 has been previously conditioned by the output of ip-op 32, it supplies an output pulse to character counter 36.
  • the output pulses of pulse shapers 40a are also supplied in parallel tc the second input grids of input matrix 38a.
  • input matrix 38u is furnished hereinafter in connection with Fig. 2. Briefly, thc input matrix con sists of an array of 48 and" gates arranged in six rows and eight columns. Each one of the six pulse Shapers 40a is connected to the second input grids of a diderent row of eight and gates.
  • Each stage of the character counter 36 is connected to the first input grids of a column of six and gates. Therefore, only one column of and gates are conditioned at any one time to fus-ni Ei w. output signal.
  • the output of the character counters 31e is also connected to delay lines 49a as hereinafter dcscribed.
  • the outputs of the and gates of the input matrix 38a are connected to the 48 inputs of storage register 46u.
  • the storage register 46a is composed of an array of 4S ilip-llops- The 48 flipdlops are arranged in six rows and eight columns corresponding to the arrangement of the and gates of the input matrix 33a.
  • the storage register may be of the well known stnticizer type which is described in an article by A. D. Booth entitled "The Physical Realization of an Electronic Digiital Computer, published in Electronic Engineering, December 1950, at pp. 492-498.
  • Each output of the and gates of input matrix 38a is connected to the set input or the flip-op of storage register 4dr: to which it corresponds by row and column.
  • the outputs of the ilip-ops of the storage register 46a are similarly connected to the lirst input grids of a siX row, eight column array of output and" gates 48a.
  • the second input grids of each column of the output and gates 43a are connected to the outputs of eight conventional pulse delay lines 49u.
  • the input to each of the delay lines 49a is respectively connected to a different one of thc eight out put stages of the character counter 36.
  • the outputs of each column of the array of output and" gates 48a are connected to six inputs of a comvparutor l).
  • the comparator S0 may be the electronic comparator shown in 4 of the copcnding application Ser. No. 375.?569 entitled Electronic Comparator, tiled hy P. Cheilili on August 24, 1953.
  • the comparator compares the outputs of and" gates 8u and 4Gb and furnishes a signal signifying which of the characters from these two output and gates is the larger.
  • an output signal (B A) is furnished at lead 52a.
  • Lead 52a is connected both to an input of or gate 4S and to one of the inputs of a two input and gate 53a. Conversely, the output signal (A B is furnished at lead 52h of comparator 50.
  • Lead 5211 is connected both to a second input of or gate 45 and to one of the inputs or" a two input and gate 53b.
  • the output or" or gate 45 is connected to the reset input of llip-liop 55.
  • the output of flip-Hop 55 is connected to the second inputs of both two-input and gates 53a and 53h.
  • the output signal of and gate 53a is applied to one of the inputs of a two input or gate 54a.
  • the output of the or gate 54a is connected to the set input of flip-flop 35a and to an input of or" gate 57h.
  • the output of or" gate 57h is in turn connected to the reset input R of a ip-ilop 35h.
  • the output signal of and" gate 53h operates to set flip-flop 3511 and to reset dip-hop 35a.
  • the output of flip-liep 35a is connected to one of the inputs of and gate 59a.
  • the output of and gate 59a is connected to the start input of an A tape drive mechanism 56a and to the stop input of a B tape drive mechanism 56h.
  • the tape drive mechanisms may be the aforementioned mechanism described in connection with Fig. 5.
  • the output of and gate 59a is also connected through delay line 61a to the input of predetermined counter 58a.
  • the predetermined counters ⁇ 58a and 53h may be of the type described by John I. Wild in an article entitled Predetermined Counters published in Electronics, vol. 20, No. 3, pp. 121-123, March 1947. Such a counter operaates to furnish an output pulse only after preset number of pulses have been received at its input.
  • the output of predetermined counter 58o is connected to an input of "and gates 63a (Fig. la) and 6l) (Fig. lb).
  • the output of and gate is applied to the input of a Schmitt trigger 69.
  • the output of the Schmitt trigger 69 is ap plied to the reset input of predetermined counters 58a and 58! (Fig. la), and also to the input lead of flip-flop :32. tfiig. liti.
  • Flip -f1op 62 is a conventional bistable device described in chaper 3 of Thompkins and Wakelin supra. Successive signals applied to the single input lead reverses the operating state of the circuit.
  • the plate of one of the tubes (assume that left-hand tube (L) as marked on the drawing) is connected to an input of and gate 74a.
  • the plate of the other of the tubes (assume the right-hand tube (R) as marked on the drawing) is connected to an input of and gate 74b.
  • the ouutput of and gate 74a is connected to the set input of a ilip-llop 73, and the output of and" gate 74b is connected to the reset input of tlip-tiop 73.
  • Flipflop 73 is provided with two output leads 71a and 71b. If we assume that conduction is shifted from the lefthand tube (L) (as marked in the drawing) to the right hand tube (R) (as marked in the drawing) when a set signal is received, then an appropriate output signal will appear on output lead 71a. Conversely, when conduction is shifted back due to a reset signal, then an appropriate output signal will appear on output lead 71b.
  • Output lead 71a is connected to the rst input grids of a first group of seven and" gates 64a; output lead '11b is connected to the rst input grids of a second group of and gates 64b.
  • the output of and gate 74a also is connected to the start input of output tape C drive mechanism 70a and to the stop input of output tape D drive mechanism 70b.
  • the output of and gate 7 4b is likewise connected to the start input of output tape D drive mechanism 7019 and to the stop input of output tape C drive mechanism.
  • the outputs of the set of and gates 64a is connected to a seven channel recording head 65a of output tape C.
  • the outputs of the set of and gates 64b is connected to a seven channel recording head 65b of output tape D.
  • the second input grids of both sets of and gates 64a and 64b are connected to the seven outputs of a fourteen input or" gate 66. Seven of the inputs of or gate 66 are connected to the second reading head 18a (Fig. la) of input tape A.
  • the other seven inputs are connected to the second reading head 18h of input tape B.
  • the output tapes C and D (Fig. lb) are driven respectively by drive mechanism a and 7Gb in the directions indicated by the arrows.
  • Erase heads 67a and 6'7b are provided in the path of each output tape.
  • the erase heads are conventional units in the magnetic recording art, and are used to remove the present recording from the tape and to condition the tape to receive a new recording.
  • the last stage of character counter 36 (Fig. la) is connected to the input of a Schmitt trigger 37.
  • the undelayed output of the Schmitt trigger 37 is connected to an input of and" gate 63a and to an input of and gate 63h.
  • the undelayed output of the Schmitt trigger 37 is connected to the ser input of Hip-flop 55.
  • the output of Schmitt trigger 37 is also connected to delay lines 39, 4l, and 43.
  • the output signal of delay line 39 is applied to an input of and-not gate 51.
  • One of the inputs of and-not gate 51 is also connected to the output of llip-llop 35a; the third input of and-not gate 51 is likewise connected to the output of llip-ilop 35h.
  • the output of and-not gate 51 is connected to an input of or gate 54a.
  • the output of delay line 41 is applied via the initiate conductor to an input of and gates 59a and 59h and also to an input of and gates 74a 1 and 74b (Fig. lb).
  • the output of delay line 43 is applied to the reset of inputs of ip-ops 35a, 35b, and 32.
  • the output of delay line 43 is also applied to the reset input of character counter 36.
  • a common ground (not shown) is also connected to the individual circuits shown in the drawing.
  • Fig. 2 is a block diagram of the arrangement of the input matrix 38a.
  • the arangement of input matrix 38h is similar.
  • These associated components are also shown which are essential for clarity. Where the components are the same as those shown in Fig. l, they are given the same designation.
  • One of the blocks 78a is detailed in order to show the connection of a conventional and gate circuit.
  • a suitable and gate may be a multiple-input vacuum tube such as a pentode 76a.
  • a typical and gate is described by C. H. Page in an article entitled Digital Computer Switching Circuits, supra. Briey, both of the input grids 81a and 83a are normally biased below their cut of point. In order to obtain an output 84a, both of the input grids must be driven above the cut oif points at the same time.
  • Each of the blocks 78a contains a similar and gate.
  • the and gates are arrayed in eight columns 80a and six rows 82a.
  • the outputs of the six channels of the first reading head 16a is applied to the inputs of pulse amplier 28a and the output of these pulse amplifiers 28a is applied to the inputs of pulse Shapers 40a.
  • Each of the pulse Shapers 40a is connected to all the second input grids 33a of the and gates 78a in a different one of the rows 82a.
  • Each of the pulse Shapers is also connected to one of the inputs of or gate 42a.
  • the output of or gate 42a is also connected to one of the inputs of or gate 47 which output in turn is connected to one of the inputs of and gate 34.
  • the output of and gate 34 is applied to the eight stages of character counter 36.
  • Each of the stages of the character counter is connected to the first grid 81a of the and gates 78a.
  • the character counter may be one of the well known ring-type counters which is widely used in the multiplex telegraph art as an electronic distributor. Due to the internal connections of the ring counter, only one stage at a time is operating. The operating stage conditions the next succeeding stage for operation. Thus, the operation of the character counter 36 is shifted one stage each time an input signal is received. The operating stage of the ring counter thus conditions one column 80a of the input matrix 38a each time an input signal from and gate 34 is received.
  • the outputs 84a of the and gates 78a are applied to the corresponding inputs of the storage register 46a of Figure la.
  • the eighth stage output (on lead 86a) of character counter 36 is applied to the input of Schmitt trigger 37 of Fig. la.
  • Each output of the eight stages of the character counter 36 is also applied in similar fashion to the eight-columns of input matrix 38h.
  • Each of the six rows of input matrix 38b is also connected in like fashion respectively to the output of an individual one of the pulse Shapers 4Gb.
  • Fig. 3 which shows in greater detail the arrangement of the storage register 46a of Fig. l
  • the forty-eight flip-flops 88a are arranged in an array of eight columns 90a and six rows 92a.
  • the outputs 84a of each of the and" gates 78a of the input matrix 38a are applied individually to the set input of a corresponding ip-op 88a.
  • Conductor 94a is connected to the reset input of each one of the ip-flops 88a.
  • the reset signal applied to the Hip-flops 88a by conductor 94a is received from the output of and gate 59a.
  • a signal furnished at the output of and gate 59a operates to reset all of the flip-flops 88a of the storage register 46a to their inidit 14 tial condition.
  • the output of each of the ip-llops 88a appears on conductors 96a.
  • the arrangement of the storage register 4Gb is identical except that the reset signal is received from the output of and gate 59h.
  • Fig. 4 is a more detailed schematic drawing of the arrangement of the output and" gates 48a.
  • the output and" gates are arranged in an array of eight columns ta and six rows 102a similar to the input matrix and storage register arrays.
  • Each of the blocks 98a represents a two input and gate similar to and" gate 78a previously described in connection with Figure 3.
  • the second grid of each and gate 98a (Fig. 4) is connected to the output of the corresponding dip-flop 88a of the storage register 46a shown in Fig. 1a and Fig. 3.
  • the first grid of the and gates of each of the eight columns 10011 is connected respectively to each of the eight delay lines 49a.
  • the inputs to each delay line 49a is connected respectively to each of the output stages of the character counter 36a of Fig. 2.
  • the outputs of each row 102e of and gates 98a are connected in parallel respectively to the conductors 106416.
  • the output conductors 106- r 116 are connected respectively to one of the sets
  • the comparator 50 includes six separate stages, a different one of each of the six binary digits in a character. Signals representing the highest order digits (25) of the a and b characters are coupled from the output gates 48a and 48b (Fig. 2a) to the highest order stage 25 of the comparator 50 (Fig. 7). Signals representing the 24 digits of the a and b characters are coupled to the stage 24 of the comparator 50, and so on.
  • the stage 25 of the comparator 50 includes a pair of amplifiers 120a and 120i), responsive to the 25 signals of the a and b characters, and a pair of pulse transformers e and 140b respectively coupled to the amplifiers 120e and 120b.
  • Each of the pulse transformers 140.1 and 140b provides a relatively high-level output a5 and b5 when the 25 signals represent a binary one," and relatively high-level outputs :15, 55 when the 25 signals represent a binary zero.
  • the first of the and" gates G-SS has one input coupled to the a5 output of the pulse transformer 140a, and another input coupled to the b5 output of the transformer 1402:.
  • the and gate G-Ss provides an output signal when the 25 signal of the a character is a one and the 25 signal of the b character is a zero.
  • the second and gate G-ST has one input coupled to the b5 output of the transformer 140b, and another input coupled to the (t5 output of the transformer 140e.
  • the and gate G-ST provides an output signal when the 25 signal of the b character is a one and the 25 signal of the a character is a zero.
  • the third and gate G-SP of the and gates 240 has one input coupled to the a5 output of the pulse transformer 140a, and a second input coupled to the b5 output of the pulse transformer l40b.
  • the and" gate G-SP provides an output when the 25 signals of both the a and b characters are binary ones
  • the fourth and gate G-SR has one input coupled to the E5 output of the transformer 140b, and a second input coupled to the output of the transformer 140a.
  • the "and gate G--SRI provides an output when both the 2 signals of the a and b characters are binary zeros.
  • the outputs of the third and fourth and gates G-SP and G-SR are coupled to the inputs of a two-input or" circuit 340.
  • the output of the or circuit 340 is coupled to the input of an amplifier 120e which has its output connected to a third input of the 24 stage of the comparator.
  • Each of the other stages 24 through 2o of the comparator 50 is similar to the 25 stage except that each of the four and gates 240 is a three-input and gate having its third input connected to the output of an amplifier 120C.
  • Each of the outputs of the and" gates G-SS of the six stages is connected to a different one of the six inputs of an or circuit 360a.
  • the output of the or gate 360o represents the A B signal on the output lcad 52.1 (Fig. 1b).
  • the outputs of the and gates G-ST (Fig. 7) of the six comparator stages are each connected to a different one of six inputs of an or circuit 360b.
  • the output of the "or circuit 360b supplies the A B signal on the lead 521: of Fig. lb.
  • the most significant digits 25 of both the a and b characters are compared with each other. If an inequality occurs between these digits, one of the output leads 52a or 52h receives an output signal. If both these bits are either ones" or zeros, the 24 bits of the a and b characters are compared. If the 24 bits are unequal, an appropriate signal is supplied to one of the output leads 52a or 52h.
  • the terminal 440 is not employed in the present sorting apparatus, since the absence of an A B and A B indicates that the a and b characters are equal.
  • each sequential group recorded on an output tape is composed of two messages, one of which is transferred from input tape A and the otherof which is transferred from input tape B.
  • This sorting condition is taken care of by manually presetting each of the predetermined counters 58a and 58h to produce an output after one input pulse.
  • the preliminary sorting operation is commenced by starting input tape A.
  • the start message symbol of the first message passesV beneath reading head 16a.
  • the bits representing the startV message symbol are detected by the reading head 16a and a corresponding output signal is furnished in parallel to the inputs of amplifiers 28a.
  • the output signals of amplifiers 28a are applied to the inputs of pulse shapers 40a.
  • the output signals of pulse shapers 40a are rectangular shaped pulses of approximately 2O microseconds duration.
  • the output signals of pulse shapers 40a are applied to the inputs of code recognition gate 26, the second input grids of each of the and gates of the input matrix 38a, and the inputs of or gate 42a.
  • gate 42a furnishes an output signal which is passed through or gate 47 to an input grid of and gate 34.
  • gate 34 is not primed as explained hereinafter, and therefore is not responsive to the first signals received at its inputs.
  • the start message signal is recognized by code recogni tion gate 26, and an output signal is furnished to delay line 30.
  • the delayed output signal of the code recog nition gate is applied to the set input of fiip-fiop 32.
  • the output signal of fiip-fiop 32 is a DC. level voltage which is applied to one of the input grids of and gate 34 priming and gate 34 to respond to signals applied at the second of its inputs.
  • the and gates of input matrix 38a are not responsive to the signals received from pulse Shapers 40a because the second input signal supplied by character counter 36 is not present.
  • the second character detected by the first reading head 16a is the highest order-determinative character of the serial number.
  • This second character now represented by pulses in the appropriate channels of the reading head 16a is applied to the pulse amplifiers 28a and to the pulse Shapers 40a.
  • the output pulses suitably amplified and shaped are applied to the second input grids of the input matrix 38a.
  • These output pulses of pulse Shapers 4tlg have a duration of approximately 20 microseconds.
  • the output pulses of pulse Shapers 40a are applied to the inputs of the or gate 42a which, in turn, furnishes an output pulse which is applied to one of the inputs of or gate 47.
  • the output signal of or gate 47 is applied to the second input of and" gate 34 now primed by the start message signal.
  • the output signal of and gate 34 is applied to the input of character counter 36, thereby rendering the first stage of character counter 36 operative.
  • the output of the first stage of the character counter 36 is applied to the first input grids of the first column of and gates of the input matrix 38a. Therefore, because the delay caused by the "or gates 42a and 47 and the and gate 34 is only of the order of 2 microseconds, the input pulses received from the pulse shaper 4ila and the pulses received from the first stage of the character counter 36 substantially coincide in the first column of the input matrix 38a.
  • the and gates of the first column of the input matrix 38a are made conductive.
  • the outputs of the first column of the input matrix 33a are connected to the set inputs of the first column of fiip-fiops of storage register 46a.
  • the iiip-iiops of the first column of the storage register 46a are set up to correspond to the first character of the serial number.
  • the outputs of the rst column of the storage register 46u are connected to the second input grids of the first column of the output and gates 48a. Since the tiip-fiops will remain in one or the other stable condition, the storage register 46a continues to condition the first column of the output and gates 48a until the fiip-iiops are reset to their zero condition.
  • the output of. the first stage of character counter 36 is also applied to delay lines 49a.
  • delay lines 49a The purpose of delay lines 49a is to allow for the small interval of time (approximately 2 microseconds) which is required to set up the fiip-fiops of the storage register 46a.
  • the outputs of delay lines 49a are applied to the first input grids of the first column of the output and gates 48a.
  • the signal from the fiip-fiops of the storage register 46a and the pulses from the delay lines 49a substantially coincide in the first column of the output and gates 48a. Therefore, an output signal representative of the first character of the serial number is applied to one of the inputs (6 leads) of the comparator 50.
  • the succeeding characters of the serial number of the first message encoded on tape A are detected by the first reading head 16a and switched through the input matrix 38a to the storage register 46a.
  • One character of the serial number is stored in nach column of the storage register 46a.
  • the outputs ot ⁇ each of the columns of the storage register 46a remain impressed on the second grids of the output and gates 48a thereby priming the and" gates for subsequent operation.
  • the output and" gates 48a are gated column by column by the output pulses of the delay lines 49a.
  • the serial number is switched into the comparator 50, character by character.
  • the B tape storage register Before the start of the sorting o-peration, the B tape storage register is set to zero condition. Therefore, the result of the first comparison in the comparator 50 indicates that the serial number of the A message is greater than the serial number of the B message.
  • the comparator indicates this inequality by an appropriate signal at its A B output 521i. This signal is passed over conductor 52h to or gate 45 and to one of the first inputs of the two-input and gate 53b. The output of or gate 45 is applied to the reset input of llip-op 5S. Because flip-flop 55 is initially in a set condition, both and gates 53a and 53b are primed for operation. Therefore, the signal applied at the second of the inputs of and gate 53b is passed to an input of or gate 54b. The priming signal applied to both and gates 53a and 53b is removed due to the reset signal applied to flip-flop 55, thus subsequent inequality signals are not passed through and gates 53a and 53b until ipop 55 is again placed in its set condition.
  • the output signal of or gate 54b is applied to the set input of rlip-op 35b, and through or gate 57a to the reset input R of Hip-op 35a.
  • the eighth character of the serial number causes the character counter 36 to furnish D.C. output voltage to Schmitt trigger 37.
  • Schmitt trigger 37 transforms the D.C. voltage of the last stage of the character counter 36 to a voltage pulse. This pulse is applied to one of the inputs of and gates 63a and 63h.
  • gate 63a Because and gate 63a has already been primed by presetting predetermined counter 58a, and gate 63a furnishes an output pulse to the set input of flip-Hop 35b ⁇ and through or gate 57a to the reset input of ip-iiop 35a.
  • the previous comparator 50 signal has already conditioned the flip-flops 35a and 35b, as described above, so the output pulse of and gate 63a which is passed through or gate 54h is not necessary during the preliminary sorting operation. This is so because the function of and gates 63a and 63h is concerned with grouping the messages on an output tape as described hereinafter.
  • the output pulse of Schmitt trigger 37 is also applied to delay line 39, and after being delayed a suitable interval, the output pulse of delay line 39 is applied to one of the inputs of and-not gate 51.
  • the and-not circuit is well-known in the art. For example, one arrangement of an and-not gate is described at page 272 of High-Speed Computing Devices, supra.
  • the andnot gate will pass the signal applied from the output of delay line 39 unless la prior signal has been received from one or the other of the ilip-iiops 35a or 35b.
  • the and-not circuit is provided to cause the A message tape to arbitrarily advance in case both the serial numbers of the messages read from the A tape and the B tape are equal.
  • the output pulse of delay line 39 is also applied to the input of delay line 41, and after being suitably delayed by delay line 41, the pulse is applied w'a the initiate conductor to an gates 59a, 59h (Fig. la) and 74a and 74b (Fig. 1b).
  • Flip-nop 35a is in its reset position, and thus the initiation pulse has no eiect on and gate 59a which is connected to the output of ipilop 35u.
  • flip-Hop 35h is in its set position, therefore, "and" gate 59h responds to the initiation pulse.
  • the output signal of "and” gate 59h is applied to the start input of tape B drive mechanism 561) and to the stop input of tape A drive mechanism 56a.
  • the eighth character of the serial number of the rst message recorded on tape A causes tape A to be stopped and tape B to be started.
  • the output pulse of and" gate 59h is applied via delay line 61b to the input of predeter mined counter 58h advancing this counter one position. Because predetermined counter 58b had been initially set to respond to one input pulse, an output signal is furnished to and gates 63h of Fig. la and 60 of Fig. lb. The output signal has no effect on and gate 63b of Fig. la because no pulse is present at the input connected to the output of Schmitt trigger 37. However, "and" gate 60 (of Fig. lb) becomes operative because of the presence of the output signals of both predetermined counters 58a and 58h of Fig. la. Predetermined counter 53a was initially set with the count of one at the start of the sorting operation.
  • gate 60 furnishes an output signal to Schmitt trigger 69.
  • the output pulse of Schmitt trigger 69 is applied to the reset inputs of both predetermined counters 58a and 58b of Fig. la, resetting both these counters to their zero condition.
  • the output pulse of Schmitt trigger 69 of Fig. lb is also applied to the set input of ilip-ilop 62.
  • the output signal of the flip-op 62 is applied to and" gates '74a and 7411, however, the output signal of the Hip-flop 62 does not pass either of the last mentioned and gates 74a or 74b because the initiation impulse is not present at this time.
  • the initiation pulse is also applied to delay line 43 of Fig. la, and after being suitably delayed is applied as a reset impulse through or gates 57a and 57b to the reset inputs R of flip-hops 35a and 3511.
  • both of the ip-ops 35a and 35b are reset whereby, neither of the and gates 59a and 59b is primed for operation.
  • the reset impulse from delay line 43 is also applied to the reset inputs of character counter 36 returning it to its zero condition and, in addition, the reset impulse from delay line 43 is applied to the reset input R of flip-Hop 32.
  • each of the predetermined counters 58a and S8b off Fig. la have been unloaded by the reset impulse received from Schmitt trigger 69 of Fig. lb. Nevertheless, it should be pointed out that the predetermined setting of each of the predetermined counters remains at one count so that each predetermined counter will furnish an output signal upon the receipt of one input pulse.
  • the first character of the first message encoded on the B tape is the sau message symbol. This symbol is detected by first reading head 16h and passed through amplifiers 28h and pulse Shapers 38a to the inputs of code recognition gate 26. The output signal of code recognition gate 26 is passed through delay line 30 to the set inputs of flip-flop 32 which in turn primes and gate 34.
  • the highest order determining character of the first message encoded on the B tape is next detected by reading head 16h, and passed through pulse amplifiers 28h and pulse shapcrs 46h.
  • the output signals of pulse shapers 40b are passed in parallel to the inputs of "or gate 42h and also to the second input grids of input matrix 38b.
  • the output signal of "or gate 42h is passed through or gate 47 to the other input of and" gate 34, which has already been primed by the start message symbol, to the input of character counter 36, which, in tura furnishes an output signal at its first stage.
  • the output signal of the character counter is applied to the second input grids of the first column of and gates of the input matrix 38h.
  • the output signal of the lirst stage of character counter 36 is also applied in parallel to the inputs of delay lines 49a and 49b. After a suitable delay, the output signals of delay lines 49a and 49h are applied to the first input grids of the first column of output and gates 48a and 48b. Both first columns of output and gates 8a and 48b are presently conditioned by their respective first column flip-flops of storage registers 46a and 461). Therefore, the outputs of both irst columns of output and gates 48a and 48b are applied to separate inputs of comparator 50. Since each of the iirst columns of output and" gates 48a and 4Sb are representative of the binary value of the first character encoded on the A tape and the B tape respectively, the comparator Si? now operates to determine which of the characters has the greater' binary value.
  • the comparator 5t furnishes an output signal at its B A output 52a.
  • the output signal on lead 52a is applied to an input of or gate 45 and also ⁇ to an input of and" gate 53a. Because, both and gates 53u and 53b are primed by the output signal of flip-flop 55, the output signal on lead. 52a is passed through and gate 53a to an input of or gate 54u.
  • the output signal of "or gate 45 is applied to the reset input of flip-flop 55.
  • gates 53a annd SSb are unresponsive to further output signals from comparator 50 until ip-flop S5 is again placed in its set position.
  • the output signal of -or" gate Sdn is applied ⁇ to the set input of iiip-tlop 35a whose output signal then primes and gate 59a.
  • the output ot ⁇ "or gate 54a also passes through or gate 57h to the reset input of flip-nop 35b. However, it does not affect flip-liep 3511 because the tlipflop is already in its reset condition as explained previously.
  • the output signal of ip-tiop 35a is applied to an input of and-not" gate 51 priming this gate against further operation.
  • the remaining characters of the serial number of the first message encoded on the B tape are passed one after the other through pulse amplifiers 231i, and pulse Shapers 40h, to the second input grids of the and gates of input matrix 38h.
  • the outputs of pulse Shapers b are applied to the inputs of or gate 42h.
  • the output signal of or gate 42h is passed through or gate 47 and primed and gate 34 to the input of character counter 36.
  • the character counter 36 is advanced one count for each of the remaining characters of the B message serial number.
  • the output signal of each stage of the character counter 36 is applied in turn to the first input grids of the second through eighth column of the and gates of the input matrix 38b.
  • the output 20 signals of each column of and gates of the input matrix 38h in turn are applied to the set inputs of the corresponding ip-iiops of storage register 46b.
  • the eight characters of the serial number of the first message encoded on input tape B are stored in the eight columns of storage register 46b.
  • the character counter 36 Upon receipt of the eighth impulse at its input, the character counter 36 furnishes an output signal to Schmitt trigger 57.
  • the output pulse of Schmitt trigger 37 is apnlird to an input of both and gates 63a and 63h and the stt input of ip-op 55.
  • "and" gates 63a and 63b are not responsive to this signal since neither of the predetermined counters 58a and 531') have primed the and gates 63a or 63h for operation.
  • Fliptlop 55 thus primes and gates 53a and 5315 for operation.
  • the output pulse of Schmitt trigger 37 also passes through delay line 39, and after being suitably delayed, is applied to an input of and-not gate 51 and delay line 41.
  • Delay line 41 further delays the output of Schmitt trigger 37 and, in turn, the output of delay line 41 is applied as an initiate signal to and gates 59a, and 59h of Fig. ln and 74a and 7411 of Fig. lb.
  • And gate 59a of Fig. la is primed by tlip-op 35a and therefore furnishes an output to the start tape input of the tape A drive mechanism 56a and to the stop tape input of tape B drive mechanism 56b, causing input tape A to start advancing and stopping the advance of input tape B.
  • the output signal of and gate 59a is also applied to thc reset inputs of the tiip-iiops of storage register 46a resetting these flip-hops to their initial or zero condition.
  • the output signal of and" gate 59a is applied through delay line 61a to the input of predetermined counter 58a.
  • /xs predetermined counter 58a has been set to furnish an output signal in response to one input pulse, its output signal is applied to one of the inputs of and gates 63a (of Fig. lu) and 60 (of Fig. 1b) priming both these gates for further operation.
  • the output pulse of Schmitt ⁇ trigger 37 is further delayed by delay line 43 and applied as a reset impulse to the reset inputs of character counter 36, flip-flop 32 and, in addition, the reset output of delay line 43 is passed through or gates 57a and 57b to the reset inputs of dip-hops 35a and 35b respectively.
  • the output pulse of Schmitt trigger 69 was applied at the input of Flip-flop 62.
  • This input pulse operates to shift conduction from one of the stable states of Hip-liep 62 to the other.
  • the left-hand tube as described above of flipliop 62 is conducting. Therefore, and gate 74a to which the left-hand tube anode is connected is held well below its cutoff bias.
  • the initiation impulse generated by Schmitt trigger 37 is applied to both and gates 74a and 74b. However, only "and gate 74h is primed to pass the initiate signal.
  • the output signal of and gate 74b is applied to the reset input of ip-op 73, which has the right-hand tube conducting as described above, thereby shifting conduction from the right-hand tube to the left-hand tube of flip-op 73.
  • the output signal taken from the anode of the right-hand tube of flip-op 73 is applied via lead 71b to the second input grids of an gates 64b and hence and gates 64b are primed for operation.
  • the output signal taken from the anode of the left-hand tube of ip-op 73 is applied via lead 71a to the second input grids of and gates 64a and hence and gates 64a are well below their cuto bias.
  • the seven output signals of or gate 66 are applied to the first input grids of and gates 64a and 64b. Because and gates 64b have been primed, the input signals from or gate 66 pass through and gates 64b to recording head 65h of output tape D.
  • the first message encoded on input tape A is determined to be the smaller by comparator 50, storage register 46a is reset to its zero or initial condition by the output signal from and" gate 59a.
  • Character counter 36 and p-fiop 32 as Well as flip-hops 35a ⁇ and 35b are reset to their initial condition.
  • Flip-flop S is in its set condition thereby priming and" gates 53a and 53h.
  • Predetermined counter 58a registers one count and primes and gates 63a (Fig. 1a) and 60 (Fig. 1b).
  • Input tape A now continues to advance and each of the characters of the first message is transferred one by one to output tape D.
  • the last character of the first message encoded on input tape A is followed by the start message symbol of the second message.
  • the start message symbol of the second message of input tape A is detected by reading head 16a and causes and gate 34 to be primed as was explained in connection with the first message.
  • the following eight characters of the serial number are also detected and stored in storage register 46a as was the case with the first message.
  • the first message encoded on the B input tape is required to be recorded on output tape D immediately following the recording on output tape D of the rst message encoded on the A tape.
  • the eighth character of the serial number of the second message encoded on input tape A causes the last stage of the character counter 36 to furnish an output signal which is applied to the input of Schmitt trigger 37.
  • the undelayed output pulse of Schmitt trigger 37 is applied to the second input grid of and gates 63a and 63b. But and gate 63a is primed to pass the undelayed output signal of Schmitt trigger 37 because of the priming voltage previously applied by predetermined counter 58a to the first of its inputs.
  • the output signal of and" gate 63a is applied to and passes through or" gate 54b to the set input S of flip-hop 35b and through or gate 57a to the reset input R of ip-iiop 35a.
  • ip-op 35b primes and gate 59b for further operation regardless of the results of the comparison.
  • the output signal of Schmitt trigger 37 is also applied to the input of delay line 39.
  • the signal from delay line 39 is applied to an input of and-not" gate 51, however, this input signal is ineffective to cause and-not gate 51 to furnish an output signal because it has been inhibited due to the receipt of the output signal furnished by flip-flop 35h.
  • the output of Schmitt trigger 37 is applied as an initiation impulse to and" gates 59a and 59b.
  • gate S9b is responsive to the initiate signal due to its having been conditioned by the output signal of fiip-op 35b.
  • the output signal of and" gate 59b is applied to the start input of B tape advance mechanism 56b and to the stop input of A tape advance mechanism causing input tape A to stop and input tape B to begin advancing.
  • the output signal of and" gate 59b is applied to the reset inputs of storage register 46b resetting the tiip-tiops to their zero or initial condition.
  • the output signal of and gate 59b is applied through delay line 61b to the input of predetermined counter 58b. Because predetermined counter 58b has been set to respond to one impulse received at its input, an output signal is now supplied to and gates 63b of Fig. la, and also to and gate 60 of Fig. lb.
  • the impulse received by "and" gate 63b of Fig. 1a is ineffective to cause an output because of lack of coincidence with the undelayed signal from Schmitt trigger 37.
  • lb is conditioned by the output signal from predetermined counter SSa of Fig. la, hence the output signal of predetermined counter 58h of Fig. la causes an gate 60 of Fig. lb to furnish an output signal which is applied to Schmitt trigger 69 of Fig. lb.
  • the output signal of Schmitt trigger 69 is applied to the reset inputs R of predetermined counters 58a and 58b of Fig. la, resetting them to their initial or zero condition.
  • the output pulse of Schmitt trigger 69 of Fig. 1b is also applied to the input of ip-op 62 of Fig. lb causing the conduction to shift from the left-hand tube, as described above, to the right-hand tube.
  • the output signal taken from the anode of the left-hand tube of iiip-fiop 62 is applied to an input of and gate 74a priming this and gate for further operation.
  • the output voltage of the right-hand side of flip-hop 62 is applied to and gate 74b bringing the bias of this latter and gate well below cutoff.
  • liip-fiop 73 remains in the state with its left hand tube conducting, as described above, because no output signal has passsed through and gate 74a and 74b due to the lack of coincidence between the initiation impulse and the output signal of the left-hand tube of flip-hopI 62 which is applied to and gate 74a. Therefore, output tape D continues to advance and output tape C remains stopped.
  • the first input message encoded on the A tape is determined to be the lesser by comparator S0 of Fig. la.
  • a signal is applied to the start input of tape A drive mechanism 56a by and" gate 59a.
  • the signal from and" gate 59a resets the storage register 46a and advances predetermined counter 58a one count.
  • the first message encoded on the A tape is then transferred to output tape D.
  • the first eight characters of the second message encoded on the A tape are stored in storage register 46a.
  • a pulse is generated by Schmitt trigger 37 and applied to an input of and gate 63a, which and gate is primed by predetermined counter 58a.
  • the output of the and gate 63a is applied to the set input of hip-flop 35b which in turn conditions and gate 59b.
  • the initiation impulse passes through and gate 59b to stop tape A and start tape B.
  • the rst message encoded on tape B is then detected by reading head 18b character by character and transferred through and gate 64b of Fig. lb to output tape D.
  • the first message encoded on input tape A is transferred to output tape D
  • the first message encoded on tape B is also transferred to output tape D following the first message transferred from tape A.
  • the predetermined counters 53a and 58h are set to furnish an output pulse upon the receipt of two impulses, that is, a count of two at their respective inputs. This count of two is required because on the second pass, according to the strings of two method. Two messages are transferred from each of the input tapes to a single output tape.
  • a preliminary sorting operation similar to the one described, is carried out during the second pass, with the exception that a count of two is placed in predetermined counter SSa, for example, by a manual switch (not shown); and a count of one is placed in a predetermined counter SSb also, for example, by a manual switch (not shown).
  • predetermined counter 58b is also advanced one count due to the output of and gate 5911 passing through delay line 6lb to the input of predetermined counter 58h, Input tape B1 advances until the tirst eight characters ofthe first message are counted by character counter 36.
  • the undelayed output signal of Schmitt trigger 37 is passed through both and gates 63o and 64! which are respectivciy primed by the outputs of both predetermined counters 58a and 5851.
  • Coincidence of the output signals of and gates 63a and 63h at the inputs of and gate 60 cause and gate 60 to send a. reset impulse to predetermined counters 58a and 58h (Fig. la) resetting both predetermined counters to a zero count condition.
  • the sorting operation of the second pass continues just as in the rst pass with the exception that ip-op 73 is switched over after exactly four messages have been transh ferred from the input tapes, at which time the predetermined counters 58a and 58h furnish an output signal when two counts have been received by each predetermined counter 58a and 58b.
  • the predetermined counter 58a is first set to respond to the number of messages required to be transferred from input tape A during a particular pass; then, a count equal to the preset number is placed therein. for example, by a manual switch (not shown), in order to prime and gate 63a and thereby cause and gate 60 (Fig. 1b) to furnish a reset signal to both predetermined counters SSa and 58.5 (Fig. la) after the first eight characters of the first message encoded on input tape B are read into the storage register 4Gb.
  • the predetermined counter 58h is set to respond to the number of messages required to be transferred from tape B during the pass; then, a count one less than the present number is placed therein, for example, by a manual switch (not shown), in order that an output signal is furnished to and gate 60 only after the serial number of the first message encoded on input tape B has been read into storage register 45h. Both predetermined counters are then reset to a zero count condition by the output signal from and" gate 60. Sorting is then commenced and the input messages are rearranged on the output tapes in sequential groups.
  • any of the well-known transducing means used in tape transport mechanisms may be used to sense the messages encoded on the tapes so long as a suitable signal is furnished to the amplifiers associated therewith.
  • An apparatus for sorting messages encoded on each of two input tapes into a logical sequence on at least one output tape comprising in combination, a different pair of transducing means adjacent the path of each of said input tapes, storage means coupled respectively to one of each pair of said transducing means, comparing means coupled to said storage means, transfer means responsive to said comparing means for transferring said messages encoded on said input tapes to one of said output tapes, and means coupled to said transfer means for maintaining the messages in groups ordered internally in :1 logical sequence on said output tape.
  • An apparatus for sorting messages encoded on a first input tape and second input tape into a desired se quence on at least one output tape, wherein each of the messages is preceded by an order determining portion comprising in combination, a pair of transducing means, each adjacent the path of a diiierent one of said input tapes, a pair of storage means coupled to said transducing means for respectively storing the order determining portions of a message encoded on said tirst input tape and of a message encoded on said second input tape, comparing means coupled to said storage means for determining the relative order of said stored portions, transfer means responsive to said comparing means for transferring said messages encoded on said input tapes to one of said output tapes, and means coupled to said transfer means for maintaining said messages in a sequential group on said output tape.
  • An apparatus for sorting messages encoded on each of two input tapes into a predetermined logical sequence on at least one of a plurality of output tapes, said messages being preceded by a plurality of characters denoting an order determining portion comprising in combination, two pairs of transducing means each adjacent the path of a different one of said input tapes, a pair of storage means coupled respectively to one of each pair of said two pairs of said transducing means for storing said order determining portions of a message encoded on said first input tape and a message encoded on said second input tape, comparing means coupled to said pair of storage means for comparing said order determining portions, distributing means coupled to said transducing means for switching said stored order determining portions into said comparing means character by character, transfer means coupled to one of said output tapes, and means coupled to said transfer means for maintaining the messages in groups ordered within each group in accordance with the said order determining portions ot the mcssages on said output tapes.
  • each of said columns being respectively coupled to said distributing means whereby said distributing means activates a corresponding columnY of each of said plurality of gates subsequent to the detection of a character of said order determining portion.
  • the combination cornprising a first pair of transducing means rcspectvety nd- ]'acent the path of said input tapes, a pair of storage means connected respectively to each of said first transducing means, comparing means connected to both said storage means, a second pair of transducing means respectively adjacent the path of each input tape and each spaced from the first transducing means adjacent the same said paths, transfer means connected to said comparing means for causing one of said messages at a time to be read out by said second transducing means to one of said output tapes, and means connected to said transfer means for maintaining the messages in groups ordered within each group in accordance with the said order determining portions of the messages on said output tapes ⁇ 6.
  • an apparatus for sorting messages encoded on a first and a second input tape into one or more sequential groups on at least one output tape, each message being preceded by an order determining portion comprising a rst input tape start and stop means, a second input tape start and stop means, and means including distributing means responsive to the occurrence of the last character of an order determining portion for starting one of said input tapes and stopping the other of said input tapes.
  • a sorting apparatus for sorting messages encoded on each of two input tapes into a predetermined sequence on at least one output tape
  • an electronic distributor responsive to an input signal
  • separate transdueing means for each of said input tapes located adjacent the path of each of said input tapes, each of said transducing means furnishing output signals, means to convert said plurality of output signals into a single signal, and means to apply said single signal to the input of said electronic distributor.
  • a sorting apparatus for sorting messages encoded on each of two input tapes into a predetermined sequence on at least one output tape
  • the combination comprising an electronic distributor having an input and a plurality of outputs, a pair of storage means each having a plurality of inputs and a plurality of outputs, two arrays of output gates, each array being connected respectively to the output side of one of said pair of storage means, delay means connected between said distributor outputs and said arrays of output gates, separate transducing means for each of said input tapes and located adjacent the path thereof, means coupling each of said transducing means respectively to each of said plurality of storage means inputs, an or gate, having a plurality of inputs and a single output, means coupling said transducing means of the inputs of said or gate, and means coupling the output of said or gate to the input of said electronic distributor.
  • the cornbination comprising a first and a second counting means operative to respectively count each message transferred from said first and said second input tape, transfer means coupled to said first and said second means and responsive thereto to automatically transfer at least one message from said second input tape when said first counting means indicates that the number of messages required by a given pass have been transferred from said first input tape.
  • said transfer means comprises a first eoincident circuit connected to said first counting means, a second coincident circuit connected to said second counting means, a first switch having a first position and a second position, a second switch having a first position and a second position, means coupling said first coincident circuit to the first position of said first switch and to the second position of said second switch, and means coupling said second coincident circuit to the second position of seid tiri: switch and to the first position of said second switch.
  • an apparatus for sorting messages encoded on a first input tape and a second input tape into sequential groups on a first output tape and a second output tape by a series of passes wherein the number of messages in a sequential group is a function of a given pass the combination comprising a first counting means operative to count the number of messages transferred from said first input tape and responsive thereto to furnish an output signal after a predetermined number of messages have been counted, a second counting means operative to count the number of messages transferred from said second input tape and responsive thereto to furnish an output signal after a predetermined number of messages have been transferred, coincident means coupled to said first and said second counting means, switching means coupled to said coincident means and responsive thereto, means coupled to said switching means to start one of said output tapes and to stop the other of said output tapes.
  • transducing means adjacent the path of said first input tape, and means operatively connected to said transducing means and responsive to signals corresponding to the last order determining character of said first message of said first input tape to stop said rst input tape and start said second input tape.
  • each of said messages having a plurality of characters denoting a serial number
  • the combination comprising means for comparing the serial number of a message encoded on said first input tape with the serial number of a message encoded on said second input tape in a comparing means, means operatively connected with and responsive to said comparing means and responsive to signals from said comparing means to advance one of said input tapes in accordance with an equality indication from said comparing means.
  • each of said messages having a fixed plurality of order determining characters denoting a serial number, wherein said messages are transferred to and arranged upon at least one output tape in sequential groups, each said sequential group having a predetermined number of messages transferred from said first input tape and a predetermined number of messages transferred from said second input tape, and said sequential order is determined by the comparison of the serial number of a message encoded on said first input tape with the serial number of a message encoded on said second input tape, the combination cornprising first counting means associated with said first input tape, second counting means associated with said second input tape, a first switch means having a first position and a second position, a second switch means having a first position and a second position, means coupling said first counting means to the second position of said first switch

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US427167A 1954-05-03 1954-05-03 Sorting apparatus Expired - Lifetime US2935732A (en)

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BE537869D BE537869A (de) 1954-05-03
NL196972D NL196972A (de) 1954-05-03
US427167A US2935732A (en) 1954-05-03 1954-05-03 Sorting apparatus
US440692A US2907003A (en) 1954-05-03 1954-07-01 Information handling system
GB12684/55A GB772274A (en) 1954-05-03 1955-05-02 Data processing apparatus
FR1130250D FR1130250A (fr) 1954-05-03 1955-05-03 Appareil de triage électronique
CH347031D CH347031A (de) 1954-05-03 1955-05-03 Apparatur für die Verwendung mindestens einer Speichervorrichtung

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US427167A US2935732A (en) 1954-05-03 1954-05-03 Sorting apparatus
US440692A US2907003A (en) 1954-05-03 1954-07-01 Information handling system

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US3104380A (en) * 1959-11-27 1963-09-17 Ibm Memory system
US3221158A (en) * 1961-06-28 1965-11-30 Ibm Combinatorial word analyzer
US3311892A (en) * 1963-09-30 1967-03-28 Gen Precision Inc Sorting system with two-line sorting switch
US3380029A (en) * 1965-04-09 1968-04-23 Applied Data Res Inc Sorting system
US3444523A (en) * 1959-02-02 1969-05-13 Gerhard Dirks Apparatus for sorting of recorded digital data
US4089028A (en) * 1975-03-20 1978-05-09 United Audio Visual Corporation Method and apparatus for controlling external devices and for transferring information
US20050060297A1 (en) * 2003-09-16 2005-03-17 Microsoft Corporation Systems and methods for ranking documents based upon structurally interrelated information

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NL202021A (de) * 1954-12-09
DE1069406B (de) * 1956-03-14 1959-11-19 IBM Deutschland Internationale Büro-Maschinen Gesellschaft m.b.H., Sinddfingen (Württ.) Imtpuilsgruppensortierung
US2991456A (en) * 1956-10-18 1961-07-04 Lab For Electronics Inc Directional data transfer apparatus
US2978679A (en) * 1957-01-07 1961-04-04 Honeywell Regulator Co Electrical information processing apparatus
US3020525A (en) * 1958-04-04 1962-02-06 American Telephone & Telegraph Record controlled translator
US3081445A (en) * 1959-01-05 1963-03-12 Universal Controls Inc Automatic data sorting devices
US3133279A (en) * 1959-04-13 1964-05-12 Datex Corp Code converter control
US3045186A (en) * 1959-04-14 1962-07-17 Int Standard Electric Corp Associated circuit for electrical comparator
US3128452A (en) * 1959-05-22 1964-04-07 Bell Telephone Labor Inc Magnetic storage circuits
US3221306A (en) * 1959-06-02 1965-11-30 Magnovox Company Card processing system
US3098995A (en) * 1959-08-14 1963-07-23 Hycon Mfg Company Servo system and comparator
US3130297A (en) * 1961-11-06 1964-04-21 Douglas A Venn Digital clock system
US3274379A (en) * 1963-04-15 1966-09-20 Beckman Instruments Inc Digital data correlator
US3713107A (en) * 1972-04-03 1973-01-23 Ncr Firmware sort processor system
JPS5413306B2 (de) * 1974-01-24 1979-05-30
US4131947A (en) * 1976-08-06 1978-12-26 Armstrong Philip N Random access digital sorter
US4361896A (en) * 1979-09-12 1982-11-30 General Electric Company Binary detecting and threshold circuit

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US2617704A (en) * 1947-07-15 1952-11-11 Bell Telephone Labor Inc Recording system
US2674733A (en) * 1952-12-02 1954-04-06 Hughes Tool Co Electronic sorting system
US2690299A (en) * 1948-08-13 1954-09-28 Bell Telephone Labor Inc Testing system
US2708267A (en) * 1953-12-31 1955-05-10 Ibm Record conversion system
US2798216A (en) * 1954-04-16 1957-07-02 Goldberg Jacob Data sorting system
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US2690299A (en) * 1948-08-13 1954-09-28 Bell Telephone Labor Inc Testing system
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US2818322A (en) * 1953-05-26 1957-12-31 Ibm Sorter for tape recorded data
US2708267A (en) * 1953-12-31 1955-05-10 Ibm Record conversion system
US2798216A (en) * 1954-04-16 1957-07-02 Goldberg Jacob Data sorting system

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2991452A (en) * 1956-03-02 1961-07-04 Sperry Rand Corp Pulse group synchronizers
US3444523A (en) * 1959-02-02 1969-05-13 Gerhard Dirks Apparatus for sorting of recorded digital data
US3104380A (en) * 1959-11-27 1963-09-17 Ibm Memory system
US3221158A (en) * 1961-06-28 1965-11-30 Ibm Combinatorial word analyzer
US3311892A (en) * 1963-09-30 1967-03-28 Gen Precision Inc Sorting system with two-line sorting switch
US3380029A (en) * 1965-04-09 1968-04-23 Applied Data Res Inc Sorting system
US4089028A (en) * 1975-03-20 1978-05-09 United Audio Visual Corporation Method and apparatus for controlling external devices and for transferring information
US20050060297A1 (en) * 2003-09-16 2005-03-17 Microsoft Corporation Systems and methods for ranking documents based upon structurally interrelated information
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CH347031A (de) 1960-06-15
GB772274A (en) 1957-04-10
NL196972A (de)
BE537869A (de)
US2907003A (en) 1959-09-29
FR1130250A (fr) 1957-02-01

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