US2895673A - Transistor binary adder - Google Patents

Transistor binary adder Download PDF

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Publication number
US2895673A
US2895673A US375265A US37526553A US2895673A US 2895673 A US2895673 A US 2895673A US 375265 A US375265 A US 375265A US 37526553 A US37526553 A US 37526553A US 2895673 A US2895673 A US 2895673A
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United States
Prior art keywords
current
transistor
potential
collector
digit
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Expired - Lifetime
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US375265A
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English (en)
Inventor
Williams Frederic Calland
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National Research Development Corp UK
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National Research Development Corp UK
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/501—Half or full adders, i.e. basic adder cells for one denomination
    • G06F7/5013—Half or full adders, i.e. basic adder cells for one denomination using algebraic addition of the input signals, e.g. Kirchhoff adders
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/084—Diode-transistor logic

Definitions

  • This invention relates to electrical circuits employing transistors.
  • transistors When two conductors are contacted at closely adjacent points to the surface of certain semi-conducting materials such as, for example, germanium, which have the property that when suitably contacted a current flows across the contact more readily in one direction than the other, and a back voltage (Le. a voltage with respect to the material in the sense corresponding with its higher resistance to current flow) is applied to one of these conductors, known as the collector, the amount of current which flows therein increases with increases of the current flowing in the opposite direction relative to the said material in the other conductor, known as the emitter.
  • a back voltage Le. a voltage with respect to the material in the sense corresponding with its higher resistance to current flow
  • the back voltage is in the sense that the collector is negative with respect to the base, with the result that in order that the collector current may be increased from its back or cutoff value, the emitter must be at a positive potential with respect to the base, so that current can flow from the emitter to the base, giving rise to an increased current from the base to the collector.
  • the transistor can be made to function in a manner resembling a thermionic valve, the base of the transistor being analogous to the cathode, the collector to the anode, and the emitter to the control grid.
  • An important difference lies in the fact that it is the emitter current rather than the emitter potential which must be regarded as analogous to the grid voltage of the valve.
  • Figure 1 of the accompanying drawings shows a family of representative characteristic curves of a transistor in which the collector current i is plotted against the collector potential v relative to the base at diiferent values of the emitter current i Each curve has a steeply sloping portion P and a relatively fiat portion Q joined by a knee.
  • At least one adder When it is desired in adigital computing machine to add two numbers at least one adder must be provided which is capable of adding two digits (A and B) together with any carry digit (C resulting from the addition of the next less significant pair of digits.
  • the adder must have two outputs, one signifying the sum- (S) in the digital place in question and the other the carry digit (C) to be carried to the next more significant place.
  • S sum-
  • C carry digit
  • the present invention provides an adder of the latter type, hereinafter called analogue adders. It will be understood that the input signals in this type of adder are analogous to the digit combinations in the sense that as the sum A+B+C increases, the magnitude of the input signal increases.
  • the circuit according to the invention comprises a first and a second transistor having their emitters connected in parallel to an input terminal, means for feeding to this terminal a current I I 1;, or 1 in ascending order of magnitude according as A-f-B+C has the value 0, 1, 2 or 3 respectively, means for holding the base of the first transistor at a potential such that this transistor is in the off condition Whenever the input current has the value I means for holding the base of the second transistor at a potential below that of the base of the first transistor whenever the input current has the value I and means for extracting substantially constant currents from the collectors of the transistors and for feeding a substantially constant current to the base of the second transistor, the currents being such that the collector current of the first transistor is greater than 1 -1 the collector current minus the base current of the second transistor is greater than 1 -1 and the sum of the said collector current minus the said base current is greater than I I and that the transistors bottom when in the on condition, whereby when the current fed to the input terminal has the value I both transistors are off,
  • A-l-B-l-C' may conveniently be made zero.
  • Figure 2 shows a binary adding circuit according to the invention
  • Figures 2A and 2B are diagrams illustrating the action of the circuit of Figure 2, and
  • Figure 3 shows a circuit whereby the carry digit generated in the circuit of Figure 2 may be fed to the adding circuit associated with the next more significant digit place.
  • Figure 4 shows a binary adding circuit comprising a plurality of circuits according to the invention.
  • the circuit of Figure 2 comprises two transistors T1 and T2 each consisting of a layer G1 or G2 of semi-conducting material, for example germanium, an emitter electrode E1 or E2, a collector electrode C1 or C2 and a base electrode B1 or B2.
  • the various electrodes are connected with diodes as shown. These diodes, here and throughout the drawings, are shown as thermionic diodes for convenience, although they may in fact be crystal diodes. Their function is to limit the potentials on the electrodes with which they are connected.
  • the voltage sources are indicated by voltage values such as 100 v., and are of substantially constant potential.
  • the emitters of the two transistors are connected in parallel to aninput terminal Q, which isitself connected in parallel to the cathodes of the right-hand diodes D7, D9 and D11 of three double diode gates.
  • the cathodes of the left-hand diodes D6, D8 and D ofthese diode pairs are connected to input leads to which are applied potentials significant of the digits A, B and C respectively, in the sense that a potential of 2 volts or less is significant of the digit value 0 while a potential of +2 volts or more is significant of the digit value 1.
  • the anodes of all the diodes D6D11 are connected to a potential source of +100 volts through resistors such that a current of 2 ma.
  • any lead or leads to which the potential corresponding with a digit value 0 is applied If, on the other hand, a potential corresponding with a digit value 1 is applied to any one of the leads, the diode in the corresponding lead is cut off and a current of 2 ma. (I is fed to the input terminal Q; likewise if such a potential is applied to any two or to all three of the leads, a current of 4 ma. (I or 6 ma. (I is fed to terminal Q, while if a potential corresponding with a digit value 0 is applied to all three leads, zero current (I is fed to terminal Q.
  • both transistors remain in the off condition, with only the small back or cut-off current flowing from the base to the collector.
  • this current is supplied through diode D1 and holds the base at earth potential.
  • the cut off current is supplied from I (which it will be understood is substantially greater than the cutofi current), the remainder of I flowing through D2 and thus holding the base at a potential of +1 volt.
  • the collector potentials are both held at -12 volts by diodes D4 and D5 respectively.
  • Fig. 2A shows the variation of the potentials of C1 (full lines and C2 (broken lines) as a function of the current fed to the emitters. It will be seen that the changes of state occur midway between the current values corresponding with the four possible inputs. The changes are reversible.
  • Fig. 2B shows the variations of the collector potentials with time when a 5 microsecond current pulse is applied to terminal Q, the current having the value I at (a), I at (b), I at (c) and I at (d).
  • the 'output at C will normally have to be fed to the input lead C of an adding circuit associated with the digit place of next higher significance, or through a delay circuit back to lead C of Fig. 2.
  • Means for bringing the output at C to the correct voltage levels for effecting this are shown in Fig. 3.
  • This figure shows the collector C of transistor T2 of one stage coupled to the C input of the next stage through a diode D12.
  • the C input of the next stage is taken from the junction of two resistors forming a potentiometer chain from the 100 volt positive supply to a bias of -3 volts through a further diode D13.
  • the collector C is at -12 volts so that D5 and D12 are conducting while D13 is cut ofl". This produces a negative potential of 2 volts at C so that D will also conduct.
  • T2 is on, the collector rises to 1 volt or earth so that D5 and D12 are cut off, D13 will conduct and the potential at C will rise to +2 volts.
  • the potential at C is suitable as an input at the lead C of the next stage.
  • An adding circuit can thus be provided in which a stage such as that illustrated in Figs. 2 and 3 is allotted to each digit of a multi-digit number, so that signals representing all the digits of two multi-digit numbers to be added may be fed in parallel to the respective stages, the inputs to each stage thus being the corresponding digits of the two numbers and a carry input from the previous stage.
  • An adding circuit for producing sum and carry binary digit output signals in response to analogue input signals comprising a first transistor having an emitter,
  • a base and a collector a diode connecting said base to a fixed potential, a high impedance connecting said collector to a low voltage supply, a diode connecting said collector to a small negative bias voltage, a second transistor having an emitter, a base and a collector, a high impedance connecting the latter base to a high voltage supply, diodes connecting said latter base to small positive and small negative bias voltages to restrict the voltage excursions of said latter base between said bias voltages,
  • said small negative bias being lower than said fixed potential, a high impedance connecting the latter collector to a low voltage supply, the latter higher impedance being of smaller value than the high impedance connected to the first transistor collector whereby said second transis tor will carry more current than said first transistor, a sum output lead connected directly to the first transistor collector, a carry output lead connected directly to the second transistor collector, and an input terminal connected directly to the emitters of both said transistors for the application of input current signals of the analogue type representing the sum of three binary digit signals A, B and C 2.
  • a circuit according to claim 1 comprising three diodes, input leads connected directly to the cathodes of said diodes for the application of the binary digit signals A, B, and C to difierent ones of said diodes, three high impedances connecting the respective anodes of said three diodes to a common high voltage supply, three further diodes having their anodes connected directly to the respective anodes of the first-mentioned three diodes to form three diode pairs and having their cathodes connected directly to said input terminal, the different ones of said first-mentioned three diodes being conductive only in response to the appropriate binary digit signal representing a 1, and the different ones of said further three diodes being conductive only when the associated diode of the appropriate diode pair is nonconductive.
  • a circuit according to claim 2 comprising a first diode having its cathode connected directly to said carry output lead, a second diode having its cathode connected to a small negative bias voltage, a potentiometer chain connected directly to the anodes of said first and second diodes at one end and to a high voltage supply at the other end, and a further carry output lead connected to an intermediate point on said potentiometer chain, said first diode being non-conductive and said second diode being conductive only when the output from said second transistor collector represents a I carry digit.
  • An adding circuit comprising a plurality of circuits as claimed in claim 3 wherein the further carry output lead of each circuit is connected to the digit signal C input lead of the circuit of next highest significance.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Analysis (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Optimization (AREA)
  • Computational Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Algebra (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
US375265A 1952-07-28 1953-07-24 Transistor binary adder Expired - Lifetime US2895673A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB19063/52A GB748546A (en) 1952-07-28 1952-07-28 Electrical calculating circuits employing transistors

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US2895673A true US2895673A (en) 1959-07-21

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DE (1) DE1086923B (xx)
FR (1) FR1086474A (xx)
GB (1) GB748546A (xx)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2971696A (en) * 1954-02-26 1961-02-14 Ibm Binary adder circuit
US2999637A (en) * 1959-04-29 1961-09-12 Hughes Aircraft Co Transistor majority logic adder
US3014663A (en) * 1955-12-28 1961-12-26 Ibm Binary full adders
US3023965A (en) * 1959-02-27 1962-03-06 Burroughs Corp Semi-conductor adder
US3047733A (en) * 1957-03-12 1962-07-31 Ibm Multiple output semiconductor logical device
US3077303A (en) * 1958-05-26 1963-02-12 Packard Bell Comp Corp Data converter

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2453454A (en) * 1946-08-31 1948-11-09 Bell Telephone Labor Inc Coder for code modulation transmission
US2533001A (en) * 1949-04-30 1950-12-05 Rca Corp Flip-flop counter circuit
US2557729A (en) * 1948-07-30 1951-06-19 Eckert Mauchly Comp Corp Impulse responsive network
US2591961A (en) * 1950-11-28 1952-04-08 Rca Corp Transistor ring counter
US2712065A (en) * 1951-08-30 1955-06-28 Robert D Elbourn Gate circuitry for electronic computers

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2453454A (en) * 1946-08-31 1948-11-09 Bell Telephone Labor Inc Coder for code modulation transmission
US2557729A (en) * 1948-07-30 1951-06-19 Eckert Mauchly Comp Corp Impulse responsive network
US2533001A (en) * 1949-04-30 1950-12-05 Rca Corp Flip-flop counter circuit
US2591961A (en) * 1950-11-28 1952-04-08 Rca Corp Transistor ring counter
US2712065A (en) * 1951-08-30 1955-06-28 Robert D Elbourn Gate circuitry for electronic computers

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2971696A (en) * 1954-02-26 1961-02-14 Ibm Binary adder circuit
US3014663A (en) * 1955-12-28 1961-12-26 Ibm Binary full adders
US3047733A (en) * 1957-03-12 1962-07-31 Ibm Multiple output semiconductor logical device
US3077303A (en) * 1958-05-26 1963-02-12 Packard Bell Comp Corp Data converter
US3023965A (en) * 1959-02-27 1962-03-06 Burroughs Corp Semi-conductor adder
US2999637A (en) * 1959-04-29 1961-09-12 Hughes Aircraft Co Transistor majority logic adder

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Publication number Publication date
DE1086923B (de) 1960-08-11
GB748546A (en) 1956-05-02
FR1086474A (xx)

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