US2802052A - Regenerative telegraph repeaters - Google Patents

Regenerative telegraph repeaters Download PDF

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US2802052A
US2802052A US496276A US49627655A US2802052A US 2802052 A US2802052 A US 2802052A US 496276 A US496276 A US 496276A US 49627655 A US49627655 A US 49627655A US 2802052 A US2802052 A US 2802052A
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pulse
conductor
condition
potential
counter
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Brewster Arthur Edward
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International Standard Electric Corp
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International Standard Electric Corp
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/248—Distortion measuring systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/20—Repeater circuits; Relay circuits
    • H04L25/24—Relay circuits using discharge tubes or semiconductor devices
    • H04L25/242—Relay circuits using discharge tubes or semiconductor devices with retiming
    • H04L25/245—Relay circuits using discharge tubes or semiconductor devices with retiming for start-stop signals

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  • the present invention relates to electric telegraph regenerative repeaters of the kind which does not employ mechanical devices for regenerating the telegraph signals.
  • crystal triodes which have proved to be particularly suitable for use as trigger devices, has opened up the possibility of making economies in the design and operation of telegraph regenerative repeaters, as a result of the small size of crystal triodes, and the low currents and voltages required for their operation.
  • the invention accordingly provides an electric telegraph regenerative repeater for telegraph signal combinations consisting of marking and spacing signal elements, comprising a plurality of crystal triode trigger devices arranged in a counting chain, means for periodically triggering the said trigger devices in order to produce regularly repeated triggering pulses for timing the intervals occupied by the elements of a signal combination, conditioning means jointly controlled by the said pulses and by the received signal for conditioning a transmitting device to transmit a signal element of the same kind (marking or spacing) las the corresponding received element, and means for holding the said transmitting device in a condition to transmit a signal element of one kind until re-conditioned to transmit a signal element of the opposite kind.
  • the invention further provides an electric. telegraph regenerative repeater for start-stop code combinations of signal elements comprising a master oscillator, a crystal triode counter device controlled thereby for generating a train of short timing pulses having a repetition period equal to a signal element period said counter device being normally inoperative, starting means operated in response to a start transition for rendering said counter device operative, terminating means operative upon the lapse from the commencement of a retransmitted start element of a period at least equal to the combined 'durations of ICC said start element and the code combination immediately following for rendering said counter device again inoperative, and a dip-flop device for retransmitting the received signal elements under control of said timing pulses.
  • Fig. 1 shows a block schematic circuit diagram of an example of a telegraph regenerative repeater according to the invention
  • Fig. 2 shows graphical diagrams used to explain the operation of the repeater
  • Figs. 3 to 7 show examples of circuit details of the block elements of Fig. l.
  • the invention will be illustrated by an embodiment comprising a regenerative repeater for a teleprinter start stop system of the usual type, and providing facilities similar to those provided by the repeater described in British Patent No. 692,411 already referred to. It will be understood, however, that the invention is also applicable to other systems employing a binary (markspace) code, such as that covered by said U. S. Patent 2,749,386 already referred to, or a Baudot multiplex system. l
  • the telegraph regenerative repeater circuit shown'in Fig. l is intended for a teleprinter start-stop five-element code operating at a speed of 50 bauds. Only minor modications which will be obvious to those skilled in the art, will be necessary to adapt the circuit ⁇ for a code with a different number of elements or for a diierent speed.
  • a start-stop signal element code combination consists of a number of equal fixed periods during which the telegraph circuit can be in the marking or 4spacing condition. Each such period or condition is called a signal element, and the fixed period is called the element period.
  • the group commences with a start transition from the idle or waiting condition to the opposite condition,.and the rst element period following the start transition is called the start period or element. Every two adjacent signal elements of opposite kind (mark or space) are separated by a transition. The group is terminated by the stop transition to the idle or waiting condition.
  • the combination In the case of a live element code, the combination consists of a start element followed by five code elements, and when undistorted these six elements are of the same duration (20 milliseconds for a speed of 50 bauds).
  • the period after the stop transition, which lasts until the next start transition, is of variable duration and is called the stop element or period.
  • the minimum duration of the stop element is one element period, but in some systems itis 11/2 element periods (30 milliseconds).
  • the idle or waiting condition is the marking condition. It should be mentioned, however, that in some telegraph exchange systems a permanent spacing condition may exist before the line is seized at the exchange, the normal idle or marking condition being resumed after the line has been seized. This special unseized condition is dealt with in the circuit of Fig. l in a manner which will be explained later, and it will for the present be assumed that the normal idle condition of the circuit is the marking condition.
  • the distorted telegraph signals representing a code group are applied in some suitable way not indicated to a receiving relay 1, the contacts of which are in the position shown for the marking condition.
  • the ixed contacts are respectively connected to two conductors 2, 3 a designated mark and space.
  • These conductors are connected to a trigger pulse generator 4, to which is connected a direct current sourcehaving its positive terminal connected to ground, and having a potential of 15 volts.
  • the relay 1 connects the mark conductor 2 to ground, and the' circuit of the trigger pulse generator 4 is such that the space conductor 3 is at a negative potential of about 15 volts.
  • the regenerated signals are lsupplied to anout'putconductor 7 from a transmitting 'relay- 8 controlled by a pair of bi.stable two-condition trigger devices9, 1li-which are interconnected in such a way that they form an arrangement similar to a ilin-op circuit, so that they are always in opposite conditions.
  • the triggering ofthe flip-flop devices 9, 10 is timed Vby short timing pulses, according to the condition of conductors 2 and 3, as will be explained later.
  • the relay 8 applies a neoative marking potential to the conductor 7.
  • the timing of the whole circuit is controlledrby ya master oscillator 11 connected to a chain of counter circuits 12, 13, 14.
  • the oscillator 11 should preferably be crystal controlled, and in the presentrexamole generates sine-waves having a stable frequencyof 5.4 kilocycles per second.
  • the counters 12, 13 and 14 divide respectively by 54, 2 and 6, and each may consist of any convenient number of dividing stages, Preferably these counters are of the kind described in the specification of mv co-pending patent, Serial No. 433,397, tiled .Tune l, 1954, and the counters 12 and 13 together may consist of three stages each dividing by three, and two stages each dividing by two. like those shown Vin Fig. 9 of the last-mentioned specification (with a slight modication to bevexplained later). Similarly the counter 14 may consist of two such slightly modiiied stages dividing respectively by three and two.
  • the counters 12 and 14 are controlled by two correspending bi-stable vtwo-condition trigger devices 15, 16 which will be respectively called the primary and secondary reset devices. Briefly, their function is to prevent the counters from operating until the arrival of a start transition, and to block and restore the counters to a standard condition after the stop transition. Their action will be explained more fully later on.
  • the counter 13 iscontrolled by a two-condition trigger device 17, called the false start reset device.
  • the action of device 17 is slightly ditterent from that of devices and 16 in that'its function is to restore the counter 13 quickly to the normal or standard condition without at Vthe same time blocking it.
  • a monostable two-condition trigger circuit 18, called the short stop corrector, is provided to prevent the operation of the reset device 15 if a fresh start transition is received too quickly after a stop transition as will be eX- plained later.
  • the counter 13 When the counters 12 and 13 are operating, the counter 13 generates short positive timing pulses at 20 millisecond intervals which control the operation of the ilipop devices 9 and 10 as already mentioned.
  • all the trigger devices 9, 1@ and 15 to 1S comprise crystal triodes which can Vassume a blocked condition (the off condition) in which the emitter and collector currents are small or Zero, or an unblocked condition (the on condition) in which the emitter and collector currents have moderate values.
  • all the said trigger devices except 9 are on.
  • the application of a positive triggering pulse will trigger any such circuit from on to 011, while the application of a negative triggering pulse will trigger any bi-stable device from off to 011.
  • the reset devices 15 and 16 when on, apply negative potentials of 15 volts respectively to the counters 12 and 14, which prevent them from operating. When either of these devices is triggered oth the applied negative potential is changed to about 3 volts, and the counters will then be released, and can operate.
  • the mark conductor When the relay 1 is in the marking condition, the mark conductor has zero potential applied to it, which vblocks the ip-tlop device 10, and the secondary reset device 16, so that they cannot be triggered oli
  • the space conductor When the relay 1 is in the spacing condition, the space conductor has zero potential applied to it, which blocks the flip-flop device 9, and also blocks or shuts a gating circuit 19 (called a gate) through which (when unblocked or open) anegative pulse ⁇ is applied from the counter 13 to trigger the primary reset device 15 on A separate blocking potential is also applied to the gate 19 from the secondary reset device 16 when it is triggered oli
  • a triggering pulse can only reach the primary reset device 15 from'the counter 13 through the gate 19 if the relay 1 is in the marking condition and if at the same time the secondary reset device 16 is 011.
  • the flip-ilop'devices 9 and 10 are so arranged that a positive timing Vpulse from the counter 13 will trigger olf whichever of the devices 9 and 16 happens to be on, provided that it is not blocked over conductor 3 or 2. Furthermore, devices 9 and 10 are connected by a conductor 20 in such a manner that whenever one of the devices 9 or ⁇ 10 is triggered oli it triggers the other one on over conductor 2t). By this means, the marking'or spacing condition of the dip-flop devices 9 and 1t) is onlyv reversed by aparticular timing pulse if after the arrival of the preceding timing pulse the relay 1 has changed over.
  • the short stop corrector 18 (which, as already stated, is normally on) when triggered oit by a positive pulse from the counter 14 after the whole of a code combinationv has been received, applies a blocking pulse to the primary reset device 15 which lasts until the device 18 has restored itself to oi This blocking pulse prevents the reset device "15 from being triggered on if a new start signal arrives too soon. This will be explained more fully later.
  • the primary reset device 15 When the primary reset device 15 is triggered from off to on, it supplies a short negative triggering pulse over ⁇ conducto 21 to trigger oit the false start reset device 17, which then'supplies a short resetting pulse to restore the counter 13 quickly to normal.
  • conductors which supply triggering pulses are provided with single arrowheads,'and the designation offV or ong isV added to signify which way the corresponding device is triggered by the pulse.
  • Conductors which supply controlling potentials or pulses are provided with double arrow-heads.
  • Device 10 being n'ow no longer blocked, will be triggered olf by the timing pulse, device 9 being triggered on atthe sameV timeoverconductor 20.
  • Relay 8 is Vtherefore changed over and applies a positive spacing potential to theoutput conductor 7. I 1 Y' j 4 Vif the signals are undistorted.
  • the counting chain consisting of elements 11,12 and 13 then continues to operate, and a regular series of timing -puls'es at 20 millisecond intervals is applied to the devices 9 and 10.
  • the irst timing pulse is generated by the counter ⁇ 13 at the moment when it is rst triggered by a pulse from the counter 12, that is at 'milliseconds after zero time. Timing pulses then follow at 30, 50, 70, 90, 110 and 130 milliseconds.
  • the ilip-op devices 9 and 10 will be changed over by the first timing pulse, kand will operate the relay 8 to space. Any subsequent timing pulse will reverse or not reverse, ⁇ the condition lof the ⁇ flip-flop devices 9 and 10 depending 'upon the conditions of the conductors 2 and 3 at that time.
  • Graph B shows an example of the manner in which'the signal group of graph A may actually arrive in distorted form.
  • Graph B indicates the operations of the moving contact spring of the relay 1 (Fig. l) and not the received ⁇ waveform applied to the relay 1, which will usually be of a rounded and irregular character. In graph B some of the transitions after the start transition are too early and some too late.
  • Graph C shows the timing pulses applied to the flip-dop devices 9 and 10 (Fig. 1').
  • Graph D shows the regenerated signal group and indicates the operations Vof the moving contact spring of the relay 8 (Fig. 11).
  • the next timing pulse 27 has no effect because there is no change in graph B during the period 30 to 50 milliseconds, so that the mark conductor 2 (Fig. 1) is at earth potential and blocks the ip-op device 10, thus preventing the pulses 27 from having any effect, as already explained.
  • the nextV timing pulse 28 arrives after the transition 29 ⁇ to space in graph B, and therefore it can operate the flip-flop devices 9 and 10 and the relay 8 (Fig. l) to vproduce the corresponding transition 30 at 70 milliseconds shownin graph D. It will be clear that the next two timing pulses 31 and 32 will produce transitions 33 and 34 yin graph D corresponding to the transitions 35 and 36 in ,graph'B.
  • the lastspaceto-mark transition ⁇ 37 -of graph lB-* is the Y v15 milliseconds.
  • the counter 14 counts six periods of .20 milliseconds after the first timing pulse (23, Fig. 2)
  • the false start reset device 17 is at the same time triggered oif by a pulse from the primary reset device 15 over conductor 21, as already explained, and-restores the counter 13 quickly to the standard condition. The circuit is now back to normal and ready to receive another code combination, which it deals with in the manner described.
  • the counter 14 delivers a negative stop pulse over conductor 40, it also delivers a short positive pulse 41 (graph E, Fig. 2) over conductor 42, which triggers the short stop corrector 18 o
  • This device then generates a rectangular blocking pulse V43 (graph E, Fig. 2) the duration of Vwhich can be adjusted between limits of, say 8 and 118 milliseconds (as indicated by the dotted lines lin graph E) and applies this pulse to block the .
  • primary reset device 15 cannot be triggered off by any pulse arriving over conductor V6 until the blocking pulse 43 has terminated.
  • the circuit of Fig. 1 should ⁇ not respond to false start signals, that is, to start conditions lasting for less than l0 milliseconds, which may be due to interference or other accidental causes.
  • the gate 19 and its connections are provided for this purpose. Suppose, for example, that a false start condition of duration about 7 milliseconds is received. The return to the marking condition at 7 milliseconds is indicated by the dotted line 22A in graph B.
  • the start transition at Zero time switches oit the primary reset device 15, which allows the counter 12 to start operating.
  • the counter 13 At l0 milliseconds the counter 13 generates the timing Vpulse 23 (graph C, Fig. 2), but since owing to the transition 22A at 7 milliseconds the circuit is back in the marking condition, the ip-op device 10 is blocked, and so the timing pulse has no effect. Fui-ther, the secondary reset device 16 is ,also blocked and cannot be triggered by the timing pulse.
  • the gate 19 is now unblocked (or open) because it receives no blocking potential either from the conductor 3 or from the device 16, which is 011.
  • a negative pulse generated by the counter 13 at the same time as the timing pulse 23 can now pass through the gate 19 and trigger the primary reset device 15 back again to on
  • device 15 is triggered to on it generates a short pulse over conductor 21 which operates the false start reset ⁇ device 17 to olf thereby restoring to normal counter 13.
  • the restoration of the device 15 to on also blocks and restores the counter 12. The circuit is therefore again in the normal condition without having produced any output transition corresponding to the false start transition.
  • the gate 19 is unblocked only during the period between the transitions 22A and 22 (graph B, Fig. 2).
  • TheV repeater of Fig. 1 also deals with the permanent space condition. After the transmission of a series of characters, the repeater'resumes the normal idle condition with the contacts of the relays 1 and 8 in the position shown, and the counters 12, 13 and 14 are all blocked and inoperative. Now, if the circuit is broken down at the exchange, so that a permanent spacing condition is produced, the relay 1changes over to space and the repeater operates as described, as though all the code elements were spacing elements. Relay 8 will accordingly be changed over to space. However, at 130 milliseconds after the transition to the permanent spacing condition, the counter 14 applies the negative stop pulse over conductor 40 to switch on lthe reset devices 15 and 16 as already described, whereupon the counters 12, 13 and 14 are all stopped.
  • the repeater now waits in the spacing condition until the telegraph circuit is seized again, whereupon a marking condition is produced and the relay 1 changes over to mark.
  • This causes the generator 4 to generate a trigger pulse which starts up the counters 12 and 13, as before, and the repeater circuit behaves in the manner described for the false start condition, except that, since the flip-op devices 9 and 10 are in this case in the spacing condition, the first timing pulse from the counter 13 is able to change them over to mark.
  • the gate 19 is open to allow the primary reset device 15 to be switched back to on at 10 milliseconds because the secondary reset device 16 is held blocked in the on condition, and the repeater circuit is again in the normal idle (or marking) condition ready to accept a series of code signals as already described. It will be seen that the space-to-mark transition which occurred on the seizure of the telegraph circuit is transmitted to the output line 7 after the standard delay of 10 milliseconds.
  • the trigger pulse generator 4 comprises a resistor 47 having one terminal connected to the negative terminal of the direct current source (also shown in Fig. l) and the other terminal connected to the output conductor 6, and to the mark 'and space conductors Zand 3 respectively through two identical circuits comprising resistors 43, 49 and resistors 50, 51 equal in resistance value respectively to resistors '48 and 49. Resistors 4S and 50 are shunted by equal capacitors 52 and 53. The contacts of relay 1 are shown connected to conductors 2, 3 and to ground, as in Fig. l.
  • the source 5 is connected across the series connection of resistors 47, 48 and 49, and the capacitor 52 is charged, and the capacitor 53 is discharged.
  • the potential of the conductor 6 is where R1, R2 and R3 are the resistances of resistors'47, 48 and 49 respectively, and V is the potential of the source 5 (15 volts).
  • the conductor 2 is at ground potential, and the conductor 3 is a negative potential of V, since substantially no current flows in conductor in this condition.
  • T he oscillator 11 comprises a crystal triode 54 having an emitter electrode 55 shown with an arrowhead, a collector electrode 56 shown without an arrowhead, and a base electrode shown as a plate 57. All crystal triodes in the circuits to be described below will be shown in the same way,and it will not ,therefore be necessary to designate the electrode in future.
  • the frequency is determined by a piezo-electric crystal 58 connecting the vemitter and collector electrodes, and tuned to 5.4 kilocycles per second.
  • the base electrode 57 is connected to ground, and the emitter and collector electrodes 55, 56 are connected to ground through parallel resonant circuits 59, 66 tuned to the same frequency as the crystal 58.
  • the emitter electrode is connected to a tapping point on the inductor of the resonant circuit 59 in order to match the rather low impedance of the emitter circuit to the series resonance impedance of the crystal, which is rather high on account of the low resonance frequency.
  • the emitter electrode is polarised from a positive direct current source 61, having a potential of volts, through a resistor 62.
  • the collector electrode is likewise polarised from a negative direct current source 63, having a potential of 15 volts, through a resistor 64.
  • the counters 12 and 13 of Fig. 1 comprise tive counting stages as shown in Fig. 4 consisting of crystal triodes 65 to 69. These are arranged in substantially the same manner as the four counting stages illustarted in Fig. 9 of the specification of my co-pending application No. 433,397, with one additional intermediate stage, except that the holding rectifiers 72 to 75 of the first four stages are connected to a common control conductor 76, which comes from the primary reset device 15 of Fig, l, instead of the negative end of a voltage source.
  • the holding rectifier 70 of the last stage-69 is, however, connected as described in the last-mentioned specification to a 3-volt negative source 71.
  • the first three stages 65 to 67 are each designed to divide by 3, while the stages 68 'and 69 divide by 2.
  • the operation of these counting stages is fully described in the prior specification just referred to, and it will be explained here that each stage is normally in the ott condition with the emitter electrode negative to the base electrode.
  • the primary reset device 15 (Fig. 1) is on, the emitter electrode of each of the stages 65 to 68 has a potential of 15 volts applied to it over conductor 76, so that the stage cannot be triggered,
  • the stage can be made to respond only to every nth triggering pulse when it is desired to divide by n.
  • the collector electrode When any stage is triggered, the collector electrode generates a short positive output which is applied to the emitter electrode of ⁇ the following stage.
  • the stage 69 differs from the other four stages only in that the initial potential of the emitter electrode is always -3 volts as determined by the source 71. lt is therefore triggered by the first pulse from stage 68, while stages 65 1068 are not triggered until the arrival of the n+1 vpulse .fromthe previous stage. Stage 69 is then subsequently-triggered by every other pulse from stage 68.
  • the collector electrode 56 ofthe crystal triode 54 in the oscillator ⁇ 11 is connected through a blocking capac itor 77 and a rectifier 78 tothe base electrode of the crystal triode 65 in the first counting stage.
  • a shunt resistor 79 connects the junction point of the elements 77 and 78 to ground.
  • the rectifier 78 isdirected so that it will pass only the negative half-waves of the generated oscillations to the base electrode of the crystal triode 65 for triggering this counting stage.
  • the final output of short positive pulses spaced at 20 milliseconds intervals is taken from the output resistor 80 connected in series with the collector electrode of the crystal triode 69 in the last stage, which last stage corresponds to the counter 13 of Fig. l.
  • Positive pulses for triggering the counter 14 (Fig. l) are supplied to an output conductor 81 connected to a tapping point on the resistor 80.
  • Positive pulses of rather larger amplitude are supplied to an output conductor 82 connected to the upper end of resistor 80.
  • These pulses are the timing pulses used for triggering the fiip-fiop devices 9 and 10 and for triggering off the secondary reset device 16 of Fig. 1. Since negative pulses are required for triggering on the primary reset device 15 of Fig.
  • a transformer 83 is provided in Fig. 4 with its primary winding connected across the output resistor 80, and with its secondary winding having one terminal connected to ground and the other connected to an output conductor 84 connected to the gate 19, Fig. l, the transformer being so connected as to supply negative pulses to conductor 84.
  • the capacitor ⁇ 85connected to the emitter electrode starts to charge up and the emitter potential s lowly rises towards -3 volts.
  • the first two negative-half waves after the triggering ofi of the reset device 15 are unable to trigger the first counter stage, but by the time of arrival of the third negative half wave, the potential of the emitter electrode has risen sufficiently to allow the stage to be triggered, whereupon -its potential falls again to -15 volts and the process is repeated.
  • the first counter stage will be 'first triggered approximately three periods of the oscillator 11 after being released and then every third period thereafter.
  • the other counter stages behave in like manner.
  • the fifth counting stage 69 whichcorresponds toth'e counter 13, Fig. 1, isnot affected by the primary Areset device 15, and because its emitter electrode'is normally held at -3 volts, it will be triggered by the first pulse generated by the stage 68, and thereafter every 20'mi11iseconds. In this it differs from any earlier stages which cannot be triggered by the first pulse from the preceding stage.
  • Stage 69 is however reset by a trigger circuit comprising the crystal triode 86, which corresponds to the false start reset device 17, Fig. l.
  • the ernitter'and base electrodes of the crystal triode 86 are connected to the positive terminal of the source 61 through respective resistors 87 and 88, and the collector electrode is connected to the negative terminal of the source ⁇ 63.
  • the base electrode is connected through a rectifier 89 to a negative direct current source 90 whose potential is v3 volts.
  • the rectifier 89 is connected so that it would be in the conducting condition if it were disconnected from the base electrode, and thus substantially prevents the potential of the base electrode from rising above - ⁇ 3 volts.
  • the emitter electrode is connected through a rectifier 91 to the tapping point of the load resistor 92 of the emitter electrode of the stage 69, to which tapping point the rectifier 70 is also connected.
  • the input-conductor 21 leading from the primary reset device 15 (Fig. l) is connected to the emitter electrode of the stage 86 through a capacitor 93 and a rectifier 94, which should be directed so that it will pass negative pulses to the emitter electrode.
  • a resistor 95 connects the junction point of elements 93 and 94 to the negative terminal of source 63.
  • the capacitor 93 and resistor 95 act to differentiate the pulse generated by the device.
  • the trailing edge differential pulse (which is negative) is passed to the emitter electrode by the rectifier 94.
  • the crystal triode 86 is normally on, which means that moderate emitter and collector currents are flowing, so the three electrodes are all at potentials not much different from -l5 volts. Rectifier 89 will be blocked in this condition, and rectifier 91 should be directed so that it is also blocked in this condition.
  • the crystal triode 86 (which is the false start reset device 17 of Fig. l) is triggered substantially at the same time as a pulse is generated by the stage 69 (counter 13 of Fig.
  • the potential of the emitter electrode of stage 69 will have just started rising from about -15 volts and so
  • the rectifier 91 becomes unblocked by the current through the resistor 87.
  • the emitter electrode of the crystal triode 86 then assumes practically the same potential as that of the crystal triode 69 and thus remains blocked because the base potential has risen to -3 volts as already explained.
  • the unblocking of the rectifier 91 effectively connects the resistor 87 in parallel with the upper part of resistor 92, and accordingly the charging rate of the capacitor 96 is increased.
  • the resistance values it can be arranged so that the potential of the emitter electrode of the crystal triode 69 reaches the holding Value of about -3 volts in less than l0 milliseconds instead of the usual 20 milliseconds.
  • the crystal triode 86 becomes unblocked and it resumes the on condition with the potentials of all electrodes at nearly -15 volts, the rectifiers 89 and 91 being then blocked.
  • Fig. shows the arrangement of the counter 14 of Fig. 1, which consists of two crystal triode stages 97, 98 dividing by 3 and 2, respectively, arranged substantially in the same way as the stages 67 and 68 of Fig. 4,
  • Fig. 6 shows circuit details of the primary reset device 15, the short stop corrector 1S, and the gate 19 of Fig. 1. Since the circuit of the secondary reset device 16 is the same as that of the device 15, only the external connections being different, in Fig. 6 the connections for the secondary reset device 16 are indicated by the bracketed references.
  • the primary reset device employs a triggering arrangement which is the subject of my co-pending Patent Application No. 495,993, tiled March 22, 1955. It comprises a crystal triode 102, having the emitter and base electrodes connected to the positive terminal of the source 61 through respective resistors 103 and 104.
  • the collector electrode is connected to conductor 6 which leads from the trigger pulse generator 4 (Fig. 1).
  • Conductor 40 which leads from the counter 14 (Fig. l) is connected to the base electrode through a rectifier 105 directed so that it will pass negative pulses to the base electrode.
  • the base electrode is also connected over conductor 106 to the output of the gate 19, the circuit of which is shown in the dotted outline, and conductor 84 leading from the counter 13 (Fig. 1) is connected to the input of the gate.
  • the outputconductor 21 leading to the false start reset device 17 (Fig. l) is connected to the base electrode.
  • the emitter electrode is connected through a rectier 107 to a 3-volt negative source 108, and through a rectifier 109 and resistor 110 shunted by a capacitor 111 to the negative terminal of the source 63. Rectitiers 107 and 109 are directed to be conducting when the emitter electrode is less negative than 3 or l5 volts, respectively.
  • the emitter electrode is also connected to a conductor 112 leading to the counter 12 (Fig. l).
  • the crystal triode 102 In the initial condition, the crystal triode 102 is on, and all the electrodes are substantially at l5 volts.
  • a positive trigger pulse arrives from the generator 4 (Fig. l) over conductor 6, it causes a practically instantaneous rise in the base potential above -15 volts and a corresponding rise in the emitter potential also begins, but on account of the capacitor 111, the rate of rise of the emitter potential is relatively slow.
  • the potential of the base electrode rises to ground potential where it is held by the rectifier 105 which is connected to ground over conductor 40 and the secondary winding'of the transformer 99 (see Fig. 5).
  • the crystal triode 102 remains cut off with the base electrode at ground potential and the emitter electrode potential rising from -15 volts at a rate determined chiey by the time constant of the elements 103, and 111. The rise of emitter potential continues until it reaches -3 volts where it is held by the source 108. The crystal triode therefore remains cut 01T.
  • the rate at which the emitter potential can rise should be less than the rate of rise of the leading edge of the triggering pulse, but the time constant of the elements 103, 110 and 111 should be as small as possible consistent with this requirement in order that the emitter potential may reach -3 volts without undue delay.
  • a negative pulse is applied from counter 14 (Fig. l) over conductor 40 through rectifier 105.
  • This unblocks the crystal triode by reducing the base potential below the potential at which the emitter electrode is held (-3 volts) and all the electrodes then resume potentials near to l5 volts.
  • the sudden fall in base potential is communicated over conductor 21 to the false start reset circuit 17 (Fig. l) and is differentiated by the elements 93, 95 (see Fig. 4) to produce the short negative pulse required for triggering the crystal triode 86.
  • the corresponding short positive pulse produced by triggering off the crystal triode 102 (Fig. 6) will be blocked by the rectifier 94 (Fig. 4), and so will have no effect.
  • the crystal triode 102 is sometimes triggered from off to on by negative pulses from the counter 13 (Fig. l) arriving over conductor 84, which is connected to the base electrode of the crystal triode 102 through the gate 19 and conductor 106.
  • the gate 19 comprises four rectitiers 113, 114, 115 and 116, the same electrode of each being connected to a common point which is connected through a resistor 117 to the negative terminal of the source 63.
  • the rectifiers are so directed that all will conduct if a suiciently large negative potential is applied to the common point.
  • the rectiiiers 113 and 114 are connected in series between the conductors 106 and 84.
  • a conductor 118 from the space conductor 3 (Fig. 1) is connected through the rectiiier 115 to the comm-on point, and a conductor 119 from the secondary reset device 16 (Fig. l) is connected through the rectifier 116 to the common point.
  • relay 1 (Fig. l) is in the marking position, and accordingly conductors 3 and 118 will be at approximately -15 volts.
  • the secondary reset device 16 (Fig. l) will be ,blocked by the ground potential from the mark conductor 2 and so it cannot be triggered off by the first timing pulse from counter 13. It therefore applies approximately -15 volts to the gate 19 (Fig. 6) over conductor 119.
  • the common point of the four rectiers is initially held at ground potential over conductor 84, so both rectiiiers 115 and 116 are blocked, the gate 19 is open, and the negative pulse which is generated by the transformer 83 (Fig.
  • any gnegative pulses applied inver conductor -84 cannot reach nthe primary,resetdevice .15 :toqtrigger :it fonf it will be seen ⁇ that the gate ;19 is :only open vduring .the fperiod between ythea'terminationof the false start sigsnal-element at 22A .,(Fig. .2 graph B) and the end 22 of the normal ⁇ start element period. ⁇
  • the -circuitof the short -stop corrector 18 of Fig. 1 is shown in the dotted outline designated 18 in Fig. 6.
  • :llt comprises a crystal .triode ⁇ $120 having y.the fbase elecr trode connected toygroundthrough a frectiter -121 and -to the positive terminal of '-the .source V61 through .a ⁇ re- ⁇ -sistor ⁇ 122.
  • the rectifier -121 is-directed so that rit ⁇ conr-.ducts-when the ibase electrodeispositive .to ground.
  • the semitter electrode . is connectedgthrough asmall current- ⁇ limiting vresistor .123 ,to ,the junction point ofan fadjustablefresistorr1f24 Yand a-capacitor ⁇ 125 Vconnected in series between ⁇ .the positive terminal of Athe source 61 and the ⁇ negative'terminal-of rthelsotlrce 63.
  • the conductor 42 ⁇ leadingpirom. the counter ,-14, Fig. 1 ,.is-connected ⁇ to the ⁇ collector .electrodevoffthe crystal triode 120.
  • the crystal triode 120 is on and all the electrodes are 7at potentials .near .-15 volts 1because lthe ⁇ conductor 42 ,isnormally ⁇ at .-y-.lS .voltstsee Fig. 15.).
  • the ycapacitor 125 will be v,practically discharged in this condition.
  • the base electrode is at..ground potential and unblocks -the .recti- Qer ⁇ 1l26.
  • the junction point .of elements 109 and 110 is now held. lsubstantially at .ground potential, and this blocks .the rectifier/109. (since .the ,emitter electrode of .the-crystal triode 1'02.is at [15 volts when the latter is ,.on.-).
  • the circuit of the lsecondary ⁇ resetdevice 16 (Fig. l) is the same as that of the device I5 shown in Fig. 6 in which the short -stop ⁇ corrector -1-8, thefgate 19 andthe conductor 21 are now supposed to be omitted.
  • Conductor 6 is replaced by conductor 82 leading from the counter 13 (Figs. 1 and 4);
  • conductor 112 is replaced by the conductor 100 leading to the counter 14; and the rectifier 126 is connected to conductor 2 (Fig. l) instead of'to the short stop corrector 13.
  • the conductor 119 which leads from the secondary reset device 16 t-o the gate 19 (Figs. l and 6) and has no equivalent in the primary reset device 15, is connected to a tapping point on the resistor 103, as shown .dotted lin Fig. 6.
  • This tapping point is chosen jso ythat when the crystal triode Y102is otff .the Ypotential apiplied to conductor 119.is substantially equal to ground potential, instead of to -3 volts, Vwhich'is -requiredfor conductor 112 or 100.
  • Fig. 7 shows details of the dip-flop devices 9 and 10 of Fig. 1.
  • the arrangement comprisestwo similarly connected crystal triodes 127, 128 .the emitter electrodes -of which are connected through equal individual ⁇ resistors 129, and a common resistor 131 to the-positive ⁇ terminal of the source l61.
  • the base electrodes are connected to ground through rectiiiers 132, 133 and tothe conductor 82 which leadsfrom the counter 13 l(Fig.-1
  • the base electrodes are connected to the positive terminal of the source 61 through resistors 146 and 147.
  • the circuits'of crystal triodes 127 and 128 correspond respectively to the ip-op devices 9 and 10 of Fig. 1.
  • the ycrystal ⁇ triode 128 is onj with all electrodesv at potentials near -15 volts and a relativelylarge gcollector current.
  • Crystal triode 127 is oth with the base electrode at ground potential and .the emitter at a 4negative potential of about 3 volts as determined by the resistors 129, 131 and 140, so that the lcollector current is -ver-y small.
  • the two windings of the relay 8 are so connected in series with the two collector circuits that the collector currents produce opposing iluXes in the relay core. In the marking condition the collector current of crystal triode 128 predominates and operates the .moving contact-spring of the relay 8 to the position shown.
  • the connections of the emitter electrodes will be seen to be substantially the same as those of the emitter electrode the crystal triode 102 of Fig. 6, and the circuits behave in the same way because in the marking condition there is ground potential on the conductor 2, the crystal triode 128 cannot be triggered ott by a timing pulse arriving over conductor 82 because the capacitor 143 is effectively disconnected by the blocking of the rectifier 139.
  • the pulse also can have no elect on the crystal triode 127 which is already oli However, if relay 1 (Fig. 1) changes over to the spacing condition, conductor 2 will ybe at a potential of -15 volts, and now capacitor 139 is unblocked Vand the capacitor 143 is eiectively reconnected.
  • the -timing pulse raises the potential of the base electrodeof the crystal triode 128, and the potential of the emitter electrode attempts to follow, but -is delayed by the charging of the capacitor 143, vas before described, so thecrystal triode 128 is left in the 01T condition or the disappearance vo'f'the timing pulse, with the base electrode at ground potential and the emitter electrode at about 3 volts, and a Very small collector current.
  • 'Ihe cutting off of the emitter current when the crystal triode is 128 is triggered oli raises the potential of the conductor 20 connecting the upper ends of resistors 129 and 130, and this triggers on the crystal triode 127 by unblocking the emitter con tact. It is to be noted that after the relay 1 (Fig.
  • Figs. 3 to 7 give practical examples of crystal triode circuits for the elements of Fig. 1, various other circuits are possible for carrying out similar functions.
  • the invention is not restricted to regenerative repeaters for start stop systems, but is applicable to other binary code systems, such as the Baudot multiplex system, which employ a succession of signal elements separated by transitions.
  • the start-stop arrangements are usually replaced by synchronising means wherebyv synchronising signals are periodically transmitted with the code signals for maintaining the receiver in step with the transmitter.
  • the arrangements described with reference to Fig. l will of course need modification for such a system, and such modification can readily be made by anyone skilled in the art when the conditions which have to be met are specified.
  • the counting chain employing crystal triodes such as that shown in Fig. l will be synchronised or controlled by the synchronising signals.
  • An electric telegraph regenerative repeater for startstop code combinations of signal elements comprising a master oscillator, a Vcrystal triode counting device controlled thereby for generating a train of short timing pulses having a repetition period equal to a signal ele# ment period, said counter device being normally inoperative, starting means operated in response to a start transition for rendering said counter device operative, terminating means operative upon the lapse from the commencement of a retransmitted start element of a period -at least equal to the combined durations of said start element and the code combination immediately following for rendering said counter device again inoperative and a flip-Hop device for retransmitting the received signal elements under control of said timing pulses.
  • the said starting means comprises a first two-condition trigger device adapted to apply a blocking potential to the said counter device or part thereof, means for generating a short trigger pulse in response to each received transition, and means for applying the trigger pulse generated in response to the start transition to trigger the said first trigger device to the opposite condition in such manner as to remove the blocking potential, thereby rendering the said counter device operative.
  • a repeater according to claim 3 in which the said second counter device is normally held inoperative by a blocking potential derived from a second two-condition trigger device when in a first condition, and in which the first timing pulse following upon the start transition is applied to trigger the second trigger device to the second condition whereby the blocking potential is removed from the second counter device thereby rendering it operative.
  • a repeater according to claim 5 further comprising inhibiting means for preventing the said repeater from responding to a falsev start element'whose duration is less than half an element period.
  • a repeater according to claim 6 in which the said inhibiting means comprises means for examining the incoming signal condition at the time o f the first timingpulse following upon a start transition, means responsive to that condition being then marking for preventing the said flip-liep device or the second trigger -device from being triggered, and means for applying a pulse from the said counter device to restore the first trigger device to the first condition, thereby rendering the said counter device again inoperative.
  • said crystal triode counting device comprises va first series of crystal triode trigger circuits connected to said master oscillator to produce an output pulse upon every nth cycle of said oscillator and a second crystal triode trigger counting device connected to said first series to produce an output pulse upon every nth pulse from the output .of said first series, means responsive to a start transition to render, the connections of said first series to said oscillator effective and to render said second counting device effective to produce. a pulse upon the first pulse from said first series.
  • a repeater according to claim 9 further comprising delaying means for preventing the first trigger device from being triggered to the second condition for a specified period after the receipt of the stop transition.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Power Engineering (AREA)
  • Relay Circuits (AREA)
  • Burglar Alarm Systems (AREA)
US496276A 1954-04-06 1955-03-23 Regenerative telegraph repeaters Expired - Lifetime US2802052A (en)

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GB10033/54A GB754206A (en) 1954-04-06 1954-04-06 Improvements in or relating to regenerative telegraph repeaters

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3072744A (en) * 1959-07-16 1963-01-08 Vitro Corp Of America Pulse transmission system
US3207916A (en) * 1960-02-10 1965-09-21 British Telecomm Res Ltd Electrical pulse distributor for connecting potential to a plurality of leads
US3240955A (en) * 1959-10-05 1966-03-15 Beckman Instruments Inc Bistable electronic circuit having oscillatory and non-oscillatory stable states

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2513525A (en) * 1944-12-01 1950-07-04 Rca Corp Locking circuit with double signal control
CA466427A (en) * 1950-07-04 T. Rea Wilton Regenerative telegraph repeater utilizing impulse generator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA466427A (en) * 1950-07-04 T. Rea Wilton Regenerative telegraph repeater utilizing impulse generator
US2513525A (en) * 1944-12-01 1950-07-04 Rca Corp Locking circuit with double signal control

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3072744A (en) * 1959-07-16 1963-01-08 Vitro Corp Of America Pulse transmission system
US3240955A (en) * 1959-10-05 1966-03-15 Beckman Instruments Inc Bistable electronic circuit having oscillatory and non-oscillatory stable states
US3207916A (en) * 1960-02-10 1965-09-21 British Telecomm Res Ltd Electrical pulse distributor for connecting potential to a plurality of leads

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GB754206A (en) 1956-08-01
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