US2429227A

US2429227A - Electronic computing system

Info

Publication number: US2429227A
Application number: US598701A
Authority: US
Inventors: Philip J Herbst
Original assignee: RCA Corp
Current assignee: RCA Corp
Priority date: 1945-06-11
Filing date: 1945-06-11
Publication date: 1947-10-21
Anticipated expiration: 1964-10-21

Description

Oct. 21, 1947. P. J. HERBST 2,429,227

ELECTRONIC COMPUTING SYSTEM Filed June 11, 1945 3 Sheets-Sheet 1 -Illllk +2 (2f) I I I I I I I I I I (dy/c) /Mfelz' 1Mo 17545350 (2 g) LllV-'U'LI'U-(e) .pinyin INVENTOR P/f/z /P Hisr B* @QM ATTORNEY Oct. 21, 1947. P. J. HERBST 2,429,227

ELECTRONIC c oMEuTING SYSTEM Filed June l1, 1945 3 Sheets-Sheet 2 I FIAT! VOL75 OUTPUT' PZA TE @Ufff/V7' l 4 i0 2 VOLTS o l l l l 7 5 lo* BY @ml/a ATTORN EY Oct. 21, 1947.

N NIH P. J. HERBST 2,429,227

ELECTRONIC COMPUTING SYSTEM Filed June 1l, 1945 3 Sheets-Sheet 3 d (murio) d.

CZPPER afl/4V (6c) UHU-UHT fa): (x+y)+ (d) rafa fw/#mwen (d) DEZ/175D knuf ATTORNEY Patented Oct. 21, 1947 i ELECTRONIC COMPUTING SYSTEM Philipv J. Herbst. Princeton, N. J., assigner to Radio Corporation of America, a corporation of Delaware Application June 11, 1945, Serial No. 598.701

7 Claims. (Cl. 23S-61) This application is a continuation-in-part of my copending application Serial No. 485,308, filed May 1. 1943, for Electronic computing system.

This invention relates generally tov an electronic computing system, and more particularly to an electronic computer for deriving the sum of at least two quantities, each of which is represented by separate voltage pulse trains characteristic of the binary values of each of the quantitles. v

The binary system of computation is particularly suited to electronic computers, since a complete binary term of a binary number may be expressed in terms (a) of the conducting condition or (b) of the cut-off condition of the anode circuit of a conventional vacuum tube. A saving in the number of tubes required for a given numloer is also possible in a ratio of 3:1 over a numerical system utilizing a radix of 10. A description of the binary system of computation may be found in Elementary Number Theory, by Uspenski and Heaslet.

The principle employed is the summation of the pulses representing the numbers to be added. the generation of a control pulse train having pulses whenever the pulse train representing the summation exceeds the amplitude of one pulse and in which the amplitudes of the pulses in the control train are all of the same magnitude, the delay of this control train by a time equal to the interval between pulses in the train. The addition of this delayed train to the input so as to represent the carryover from one digit to the next and the subtraction of the undelayed control train from the total sum to accomplish the cancellation of pulses of double magnitude.

with the ilrst control pulse train to derive a fourth pulse train which is characteristic of the sum of Briefly, the system comprises an improved method and means for adding the magnitudes of the voltage pulses of each of the input pulse trains to derive therefrom a combined pulse train. To the combined pulse train is added a delayed pulse train representing the carry-over counts in the binary addition to derive a first control pulse train representing the binary sum but not in proper form for normal use. The ilrst control pulse train may contain pulses of. zero, unity, double or triple amplitude. The method employed consists in utilizing these amplitudes to produce a pulse train representing the binary sum in correct form as follows: Amplitudes of unity produce a count in the output pulse train the binary numbers to be added. The fourth pulse train may be applied to additional computing apparatus or the sum may be indicated directly.

The two pulse trains to be added are impressed upon the input of a thermionic tube circuit having a common load, to derive therefrom the first combined pulse train. The combined pulse train is applied to the grid of a conventional amplifier stage to which the delayed pulse train representing the carry-over operation is also applied. The output of this stage constitutes the first control pulse train and is applied to a clipping-limiting stage, the ouput of which consists only of pulses of unit magnitude occurring whenever the magnitude of the pulses in the first'control pulse train exceed unity and comprising the second control pulse train. This second control pulse train is applied to a conventional delay circuit which delays its pulses an amount equal tothe time interval between pulses. The delayedvpulses are combined with the combined pulse ytrain to derive the first control pulse train as previously described. The-second control pulse train isalso applied to a conventional amplifier to derive a third control pulse train of double amplitude. The rst and third control pulse trains are applied to the inputs of a summing stage. Since the pulses are applied in opposing polarity the pulses of the third control pulse train will tend to cancel thosev of the rst control pulse train. However, for amplitudes of zero or unit magnitude in the first control pulse train, no pulses are present in the third, while for pulses of triple magnitude in the first, the presence of the double amplitude pulse in the third control train produces a partial cancellation which results in a pulse of unit amplitude in the output. When the pulse in the'ilrst control train is of double amplitude the cancellation is complete. The output of the summing stage is the fourth pulse train and represents the binary sum.

Among the objects of the invention is to probined pulse train, are limited, inverted, delayed i and amplified to derive at least one control pulse train characteristic of carryover terms in the computation, and wherein the combined control pulse trains are combined to derive an output pulse train characteristic of the binary sum. A 4

still further object of the invention is to provide an improved method of and means for deriving the sum of at least two quantities each represented by separate voltage pulse trains characteristic of the binary values of each of said quantities, wherein the applied pulse trains are added to derive a combined pulse train and the com. bined pulse train is limited to derive a controlA pulse train characteristic of pulses of double amplitude in the combined pulse train. and wherein the double amplitude pulses are combined with suitably delayed trains derived from the combined pulse train to derive an voutput pulse train characteristic of the binary sum of the quantities to be added.

The invention win be described in further cietail by reference to the accompanying drawings, of which Figure 1 is a schematic circuit diagram of a preferred embodiment thereof; Figure 2 is a family of graphs characteristic of the pulse trains occurring throughout the different portions of the circuit of Fig. 1; Figures 3 and 4 are explanatory diagrams relating to the operation of the circuit of Figure 1; Figure 5 is a wiring diagram of a modified form of the invention; Figure 6 is a family of graphs characteristic of the pulse trains occurring throughout the different portions of the circuit of Figure and Figure '7 illustrates a modiiled detail of the circuit. Similar reference numerals are applied to similar elements throughout the drawings.

Referring to the drawings, a voltage pulse train illustrated by Fig. 2a, corresponding to the number 59 expressed in terms of the binary number 111011., is applied to the input terminals 2 which are connected to the input of a first amplifier tube 3. A voltagepulse train y, corresponding to the quantity 25 in terms of the corresponding binary number 11001, is applied to a second group of input terminals 4 which are connected to the input of a second amplifier tube 5. The pulse trains y may be derived in any manner known in the art, for example, a series of delay circuits for discharging, in any predetermined sequence, the charge upon a previously charged capacitor. Such a pulse train generating circuit isl disclosed in applicants copending U. S. application Serial No. 488,801, flied May 26, 1943.

The anode circuits of the

amplifier tubes

3 and 5, respectively, include a common load resistor i which is connected to a source of operating potential (not shown). The anodes of the rst and

second amplier tubes

3, 5 are connected, through an isolating capacitor 1, to the control electrode of a third amplifier tube 8, which inverts the polarity of the combined pulse train derived from the

amplifier tube

3, 5 and the output of the delay network Il. The output of the third amplifier tube I is applied to the control electrode of a limiter-inverter tube 9. The control electrode bias potential of tube 0 is selected so as to provide a threshold which will permit pulses of double and triple amplitude impressed on the input to produce an output in the plate circuit but discriminates against pulses oi.' unit amplitude. A The plate circuit of tube 9 is chosen so as to limit the amplitude of the pulses in the output to a fixed amplitude for all input pulses of double amplitude or greater. Figs. 3 and 4 show the mutual characteristic of tube 9 and illustrate the clipping and limiting action of this tube. The plate current limiting is realized by employing a very high resistance i4 in the plate circuit. Other methods, such as reducing the applied plate voltage could be used.

The control electrode bias potential may be derived from a battery i0 connected, through a grid resistor Il, to the control electrode of the limiter-clipper-inverter tube 9. As an added refinement to accommodate wide variation in pulse rate without shifting of the location of the pulse peaks on the mutual characteristic, a means of maintainingthe base line of the input pulses may be employed. This means may take the form of a rectiner or similar locking circuit. One form of this circuit is shown in Fig. '1. This refinement is not essential if the pulse width is small compared to the spacing or if the width of the mutual characteristic is small compared to the pulse amplitude, i. e., if the shift in the a-c axis of the pulse train is not sunlcient to cause achange in the limiting clipping action of tube 9. The output of tube 9 represents the carryover count in the binary addition and will henceforth be designated as the second control pulse train c.

The second control pulse train c is applied to the control electrode of an inverter amplifier tube I2. This amplification of this tube is established by selection of the values of its associated circuit components so that the pulse train in its output signal has a constant magnitude of double amplitude. This may be further insured by providing limiter-clipper action similar to tube 9 but is not essential to the fundamental operation of the circuit. The output of tube I2 represents the cancellation terms in the binary addition and will henceforth be designated as the third control pulse train d. e

The second control pulse train c also is applied, through a conventional delay circuit I5, to the control electrode of the irst inverter tube 8. Thedelay provided in the delay circuit i5 corresponds to the period of the pulses of the applied voltage pulse trains. The resultant pulse train applied to the control electrode of the first inverter tube 8 will, therefore, represent the sum of the applied pulse trains and the delayed second control pulse train, and will hereinafter be designated as the rst control pulse train a.

The first control pulse train a is applied to a delay circuit li, which delays the pulse train an amount equivalent to the total delay in the circuits associated with the inverter and limiter tubes 8, 9 and l2. The output of the delay circuit IS is applied to the control electrode of a triode I'I. The third control pulse train d is applied to the control electrode of a triode il. The triodes I1, I8, respectively, include common cathode and anode circuits and are self-biased by means of a cathode resistor i9 and cathode bypass capacitor 20 connected between the cathodes and ground.

The anodes of the triodes I1, I8 are-connected, through an output capacitor 2 I, to an output terminal 22. The other output terminal 23 may be connected to ground or any suitable indicator 24, for indicating the binary number corresponding to the sum of the applied quantities y, may be connected to the terminals 22, 23.

The indicator 24, for example, may comprise a conventional oscilloscope tube, the beam of which is normally blanked oif and normally deflected just oi the iiuorescent screen. The pulse train to be indicated is applied to the tube control grid to unblock the cathode ray at each occurrence of a positive pulse characteristic of a binary one term. The initial pulse is applied to key a conventional sweep voltage generator to provide a relatively slower sweep voltage which may be applied to the tube deiiection'elements to sweep the ray across the fluorescent screen. The sweep voltage preferably should be of saw-tooth wave form, and the fluorescent screen should be of the type providing sustained fiuorescence. The indications will be in the form of luminous dashes separated by relatively wide dark spaces corresponding to binary terms.

Referring to Fig. 2, the first graph 2a illustrates the pulse train corresponding to the first applied quantity zr. Reading from right to left, the pulses of unit amplitude, and the absence of pulses, correspond to the binary number 111011, which equals 59. -2b similarly illustrates the pulse train corresponding to the second applied quantity y. Similarly, reading from right to left, this pulse train corresponds to the binary number 11001, which equals 25. 2c illustrates the first control pulse train a, which is characteristic of the combined pulse trains :c-l-y-i-(c delayed). The delayed pulse train, shown at 2g, is characteristic of carryover pulses occurring whenever two or more unit pulses occur coincidentally.

2d shows the pulse train b derived from the ouput of the first inverter tube 8, which is equivalent to the first control pulse train a inverted in polarity. 2e represents the second control pulse train c, which is equivalent to the pulse train b clipped at an amplitude of +1 and limited at an amplitude of +2 and inverted in polarity. 2f illustrates the third control pulse train d derived from the output of the inverter tube I2, which is equivalent to double the amplitude of the second control pulse train c clipped at a magnitude of binary 1 and inverted in polarity. Pulses occur in the pulse train d only when two or more pulses` coincide in the first control pulse train a. Since the .a pulse train has been triple inverted, the d pulse train will be of opposite polarity thereto. When combined in the tubes II, I8, the d pulse train will subtract double amplitude pulses from all double or triple amplitude pulses occurring in the a pulse train. .f

2g illustrates the delayed second control pulse train c. 2h represents the output pulse train e characteristic of the binary sum to be derived, and is equivalent to the combined, relatively delayed rst and third control pulse trains a+d inverted in polarity. Reading still from right to formed by the

tubes

9 and 25 instead of the tube 9 as in the case of Fig.' 1. Due to the inverting action of the tube 25, a tube 26 is provided to invert the d (delayed) pulse train before it is combined with the :c and y pulse trains to form the first control pulse-train b.

The graphs of Fig. 6 are for the most selfexplanatory, especially in view of what has been said in connection with Fig. 2. Due to the fact that the clipping and limiting of the pulse train b is performed by separate tubes, there is'in the case of Figs. 5 and 6 a pulse train c which-is clipped at one of its amplitude levels and a pulse train d which is like the pulse c of Figs. 1 and 2 except that it has to be inverted before it is combined with the a: and y pulse trains.

I claim as my invention:

1. The combination oi pulse train combining means, means for applying to said combining means number representative pulses of unit' amplitude to derive a combined pulse train, means for deriving a unit amplitude control pulse train in which pulses occur only during such time intervals as two or more pulses are combined in said pulse combining means, means for delaying said control pulse train by a time interval equal to the period of the vpulses of said trains, means for applying said delayed control pulse train to said combining means to produce a resultant pulse train of variable amplitude, and means for reducing by two units of amplitude pulses of said resultant pulse train which are of two or'more units amplitude. y

2. 'I'he combination of pulse train combining means, means for applying to said combining means number representative pulses of unit amplitude to derive a combined pulse train, means for deriving a unit amplitude control pulse train in which pulses occur only during such time intervals as two or more pulses are combined in said pulse combining means, means for delaying said control pulse train by a time interval equal to the period of the pulses of said trains, means for applying said delayed control pulse train to said combining means to produce a resultant pulse train of variable amplitude, a pair of triodes having common anode and cathode connections, means for applying said resultant pulse train to the control grid of one of said triodes, means for vamplifying said control pulse train to double unit vals as two or more pulses are combined in said pulse combining means, means for delaying said control pulse train by a time interval equal to the period of the pulses of said trains, means left, the graph 2h. indicates a pulse train correfor applying said delayed control pulse train to said combining means to produce a resultant pulse train of variable amplitude, a pair of triodes having common anode and cathode connections, means for applying said resultant pulse train to the control grid of one of said triodes, means for amplifying said control pulse train to double unit amplitude, means for applying said amplified pulse train to the control grid of the other of said triodes, and an output terminal connected to the anodes of said triodes.

4. The combination of pulse train combining means, means for applying to said combining means number representative pulses of unit amplitude to derive a combined pulse train, means for clipping said combined pulses at unit amplitude and for limiting said combined pulses at double unit amplitude to derive a unit amplitude control pulse train in which pulses occur only during such time intervals as two or more pulses are combined in said pulse combining means, means for delaying said control pulse train by a time interval equal to the period of the pulses of said trains, means for applying said delayed control pulse train to said combining means to produce a resultant pulse train of variable amplitude, and means for reducing by two units of amplitude pulses of said resultant pulse train which are of two or more units amplitude.

5, An electronic computer for deriving the sum of two quantities each represented by separate voltage pulse trains characteristic of the binary values of each of said quantities including means for adding the magnitudes of the pulses in said pulse trains to derive a combined pulse'train, means for deriving from said combined pulse train one control pulse train characteristic of carryover terms inthe computation and another control pulse train of' double unit amplitude, means'for combining said combined pulse train and said carryover control pulse train to derive a resultant pulse train, and means for combining said resultant and double amplitude pulse trains to derive a pulse train characteristic of the binary value of the sum of said quantities.

6. An electronic computing circuit for deriving 4the sum of two quantities each represented by separate voltage pulse trains characteristic of the binary values of each of said quantities including means for adding the magnitudes of the pulses in said pulse trains to derive a combined pulse train, means for clipping and limiting said combined pulse train to derive a control pulse train of unit amplitude, means for amplifying said unit amplitude control pulse train for deriving a double unit amplitude control pulse train, means for delaying a part of said unit amplitude control pulse train an interval corresponding to the period of said pulses, means for combining said combined pulse train and said delayed pulse train to derive a, resultant pulse tram, means for delaying said resultant pulse train an amount to make it opposed in phase to said double amplitude control pulse train, and means for combining said resultant and double amplitude pulse trains to derive a pulse train characteristic of the binary value of the sum of said quantities.

7. An electronic computing circuit for deriving the sum of two quantities each represented by 'separate voltage pulse trains characteristic of the binary values of each of said quantities lncluding a pair of thermionic tubes energized through a' common load resistor for adding the magnitudes of the pulses in said pulse trains to derive a combined pulse train, means for clipping and limiting said combined pulse train to derive a unit amplitude control pulse train, means for amplifying said unit amplitude control pulse train for deriving a double amplitude control pulse train, means for delaying a part of said rst unit amplitude control pulse train an interval corresponding to the period of said pulses, means for combining said combined pulse train and said delayed pulse train to derive a resultant pulse train, means for delaying said resultant pulse train an amount required to make it opposed in phase to said double amplitude pulse train, and means for combining said resultant and double amplitude control pulse trains to derive a pulse train characteristic of the. binary value of the sum of said quantities.

' PHILIP J. HERBST.