US20230387222A1 - Semiconductor device and method - Google Patents
Semiconductor device and method Download PDFInfo
- Publication number
- US20230387222A1 US20230387222A1 US18/447,212 US202318447212A US2023387222A1 US 20230387222 A1 US20230387222 A1 US 20230387222A1 US 202318447212 A US202318447212 A US 202318447212A US 2023387222 A1 US2023387222 A1 US 2023387222A1
- Authority
- US
- United States
- Prior art keywords
- plasma
- contact
- treatment
- layer
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 180
- 239000004065 semiconductor Substances 0.000 title claims abstract description 24
- 230000008569 process Effects 0.000 claims abstract description 117
- 239000004020 conductor Substances 0.000 claims abstract description 23
- 238000000151 deposition Methods 0.000 claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 claims abstract description 8
- 239000002243 precursor Substances 0.000 claims description 87
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 30
- 239000001257 hydrogen Substances 0.000 claims description 18
- 229910052739 hydrogen Inorganic materials 0.000 claims description 18
- 229910052721 tungsten Inorganic materials 0.000 claims description 18
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 16
- 229910052786 argon Inorganic materials 0.000 claims description 15
- 229910017052 cobalt Inorganic materials 0.000 claims description 13
- 239000010941 cobalt Substances 0.000 claims description 13
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 claims description 13
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 12
- 239000010937 tungsten Substances 0.000 claims description 12
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 7
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 239000000463 material Substances 0.000 abstract description 79
- 238000005204 segregation Methods 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 151
- 210000002381 plasma Anatomy 0.000 description 80
- 239000007789 gas Substances 0.000 description 34
- 230000015572 biosynthetic process Effects 0.000 description 24
- 239000003989 dielectric material Substances 0.000 description 22
- 125000006850 spacer group Chemical group 0.000 description 22
- 238000005229 chemical vapour deposition Methods 0.000 description 19
- 239000000758 substrate Substances 0.000 description 19
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 16
- 239000007769 metal material Substances 0.000 description 16
- 238000005137 deposition process Methods 0.000 description 14
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 13
- 229910052814 silicon oxide Inorganic materials 0.000 description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 239000003085 diluting agent Substances 0.000 description 12
- -1 SiOC Chemical compound 0.000 description 11
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 10
- 229910052751 metal Inorganic materials 0.000 description 10
- 239000002184 metal Substances 0.000 description 10
- 239000000126 substance Substances 0.000 description 9
- 239000010936 titanium Substances 0.000 description 9
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 8
- 238000000231 atomic layer deposition Methods 0.000 description 8
- 239000002019 doping agent Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 8
- 230000000873 masking effect Effects 0.000 description 8
- 229910052757 nitrogen Inorganic materials 0.000 description 8
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 8
- 229910010271 silicon carbide Inorganic materials 0.000 description 8
- 229910052718 tin Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 238000004544 sputter deposition Methods 0.000 description 7
- 229910052726 zirconium Inorganic materials 0.000 description 7
- 229910010037 TiAlN Inorganic materials 0.000 description 6
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 6
- 238000002955 isolation Methods 0.000 description 6
- 239000001301 oxygen Substances 0.000 description 6
- 229910052760 oxygen Inorganic materials 0.000 description 6
- 238000009832 plasma treatment Methods 0.000 description 6
- 230000009467 reduction Effects 0.000 description 6
- 230000002829 reductive effect Effects 0.000 description 6
- ITWBWJFEJCHKSN-UHFFFAOYSA-N 1,4,7-triazonane Chemical compound C1CNCCNCCN1 ITWBWJFEJCHKSN-UHFFFAOYSA-N 0.000 description 5
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 229910004200 TaSiN Inorganic materials 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 5
- 230000008021 deposition Effects 0.000 description 5
- 238000009616 inductively coupled plasma Methods 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 230000000670 limiting effect Effects 0.000 description 5
- 229910052748 manganese Inorganic materials 0.000 description 5
- 229910052759 nickel Inorganic materials 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 238000005498 polishing Methods 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910052719 titanium Inorganic materials 0.000 description 5
- JJWKPURADFRFRB-UHFFFAOYSA-N carbonyl sulfide Chemical compound O=C=S JJWKPURADFRFRB-UHFFFAOYSA-N 0.000 description 4
- 239000012159 carrier gas Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000012212 insulator Substances 0.000 description 4
- 230000003647 oxidation Effects 0.000 description 4
- 238000007254 oxidation reaction Methods 0.000 description 4
- 238000005240 physical vapour deposition Methods 0.000 description 4
- 229910021332 silicide Inorganic materials 0.000 description 4
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 4
- 229910003468 tantalcarbide Inorganic materials 0.000 description 4
- YOUIDGQAIILFBW-UHFFFAOYSA-J tetrachlorotungsten Chemical compound Cl[W](Cl)(Cl)Cl YOUIDGQAIILFBW-UHFFFAOYSA-J 0.000 description 4
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 3
- 229910004012 SiCx Inorganic materials 0.000 description 3
- 229910004166 TaN Inorganic materials 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 229910052796 boron Inorganic materials 0.000 description 3
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 3
- 239000007943 implant Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 238000001020 plasma etching Methods 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 229910016570 AlCu Inorganic materials 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 150000004645 aluminates Chemical class 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000001965 increasing effect Effects 0.000 description 2
- 238000010849 ion bombardment Methods 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 229910052914 metal silicate Inorganic materials 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 2
- 150000004767 nitrides Chemical class 0.000 description 2
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 230000036961 partial effect Effects 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 238000007517 polishing process Methods 0.000 description 2
- 239000002952 polymeric resin Substances 0.000 description 2
- 238000002360 preparation method Methods 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 2
- 230000007704 transition Effects 0.000 description 2
- 229910000314 transition metal oxide Inorganic materials 0.000 description 2
- 229910000326 transition metal silicate Inorganic materials 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- 229910002704 AlGaN Inorganic materials 0.000 description 1
- 229910000980 Aluminium gallium arsenide Inorganic materials 0.000 description 1
- 229910019001 CoSi Inorganic materials 0.000 description 1
- 229910052691 Erbium Inorganic materials 0.000 description 1
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 229910004129 HfSiO Inorganic materials 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910005883 NiSi Inorganic materials 0.000 description 1
- 208000012868 Overgrowth Diseases 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- 229910010038 TiAl Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000012080 ambient air Substances 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 210000004027 cell Anatomy 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 1
- 238000007598 dipping method Methods 0.000 description 1
- 238000010494 dissociation reaction Methods 0.000 description 1
- 230000005593 dissociations Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- UYAHIZSMUZPPFV-UHFFFAOYSA-N erbium Chemical compound [Er] UYAHIZSMUZPPFV-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229910003465 moissanite Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000037361 pathway Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910000077 silane Inorganic materials 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- PBCFLUZVCVVTBY-UHFFFAOYSA-N tantalum pentoxide Inorganic materials O=[Ta](=O)O[Ta](=O)=O PBCFLUZVCVVTBY-UHFFFAOYSA-N 0.000 description 1
- 239000011135 tin Substances 0.000 description 1
- KPGXUAIFQMJJFB-UHFFFAOYSA-H tungsten hexachloride Chemical compound Cl[W](Cl)(Cl)(Cl)(Cl)Cl KPGXUAIFQMJJFB-UHFFFAOYSA-H 0.000 description 1
- WIDQNNDDTXUPAN-UHFFFAOYSA-I tungsten(v) chloride Chemical group Cl[W](Cl)(Cl)(Cl)Cl WIDQNNDDTXUPAN-UHFFFAOYSA-I 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76888—By rendering at least a portion of the conductor non conductive, e.g. oxidation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
- H01L21/02063—Cleaning during device manufacture during, before or after processing of insulating layers the processing being the formation of vias or contact holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76814—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics post-treatment or after-treatment, e.g. cleaning or removal of oxides on underlying conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76859—After-treatment introducing at least one additional element into the layer by ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823431—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41791—Source or drain electrodes for field effect devices for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3215—Doping the layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76844—Bottomless liners
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body
- H01L23/485—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/456—Ohmic electrodes on silicon
Abstract
A semiconductor device and method of manufacture are provided which utilize a remote plasma process which reduces or eliminates segregation of material. By reducing segregation of the material, overlying conductive material can be deposited on a smoother interface. By depositing on smoother interfaces, overall losses of the deposited material may be avoided, which improves the overall yield.
Description
- This application is a continuation of U.S. patent application Ser. No. 17/245,766, filed on Apr. 30, 2021, entitled “Semiconductor Device and Method,” which claims the benefit of U.S. Provisional Application No. 63/158,996, filed on Mar. 10, 2021, which application is hereby incorporated herein by reference.
- Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon.
- The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. However, as the minimum features sizes are reduced, additional problems arise that should be addressed.
- Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a gate structure over a semiconductor fin, in accordance with some embodiments. -
FIG. 2 illustrates a finFET device, in accordance with some embodiments. -
FIG. 3 illustrates formation of interlayer dielectric, in accordance with some embodiments. -
FIG. 4 illustrates placement and patterning of a photoresist, in accordance with some embodiments. -
FIG. 5 illustrates a patterning of the interlayer dielectric, in accordance with some embodiments. -
FIG. 6 illustrates a recessing of a source/drain contact, in accordance with some embodiments. -
FIGS. 7A-7E illustrate treatment processes, in accordance with some embodiments. -
FIG. 8 illustrates formation of a conductive contact, in accordance with some embodiments. -
FIG. 9 illustrates part of a formation of additional vias, in accordance with some embodiments. -
FIG. 10 illustrates a planarization process, in accordance with some embodiments. -
FIG. 11 illustrates a recapping process, in accordance with some embodiments. - The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Embodiments will now be described with respect to particular embodiments which utilize a non-segregating process to prepare a source/drain contact for further connections in a 5 nm process node, a 3 nm process node, and beyond. The embodiments described, however, are intended to be illustrative and are not intended to be limiting, as the ideas presented herein may be applied in a wide variety of embodiments.
- With reference now to
FIG. 1 , there is illustrated a perspective view of asemiconductor device 100 such as a fin field effect transistor (finFET) device. In an embodiment thesemiconductor device 100 comprises asubstrate 101 withfirst trenches 103 formed therein. Thesubstrate 101 may be a silicon substrate, although other substrates, such as semiconductor-on-insulator (SOI), strained SOI, and silicon germanium on insulator, could be used. The substrate lot may be a p-type semiconductor, although in other embodiments, it could be an n-type semiconductor. - The
first trenches 103 may be formed as an initial step in the eventual formation offirst isolation regions 105. Thefirst trenches 103 may be formed using a masking layer (not separately illustrated inFIG. 1 ) along with a suitable etching process. For example, the masking layer may be a hardmask comprising silicon nitride formed through a process such as chemical vapor deposition (CVD), although other materials, such as oxides, oxynitrides, silicon carbide, combinations of these, or the like, and other processes, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or even silicon oxide formation followed by nitridation, may be utilized. Once formed, the masking layer may be patterned through a suitable photolithographic process to expose those portions of thesubstrate 101 that will be removed to form thefirst trenches 103. - As one of skill in the art will recognize, however, the processes and materials described above to form the masking layer are not the only method that may be used to protect portions of the
substrate 101 while exposing other portions of thesubstrate 101 for the formation of thefirst trenches 103. Any suitable process, such as a patterned and developed photoresist, may be utilized to expose portions of thesubstrate 101 to be removed to form thefirst trenches 103. All such methods are fully intended to be included in the scope of the present embodiments. - Once a masking layer has been formed and patterned, the
first trenches 103 are formed in thesubstrate 101. The exposedsubstrate 101 may be removed through a suitable process such as reactive ion etching (RIE) in order to form thefirst trenches 103 in thesubstrate 101, although any suitable process may be used. In an embodiment, thefirst trenches 103 may be formed to have a first depth of less than about 5,000 Å from the surface of thesubstrate 101, such as about 2,500 Å. - However, as one of ordinary skill in the art will recognize, the process described above to form the
first trenches 103 is merely one potential process, and is not meant to be the only embodiment. Rather, any suitable process through which thefirst trenches 103 may be formed may be utilized and any suitable process, including any number of masking and removal steps may be used. - In addition to forming the
first trenches 103, the masking and etching process additionally formsfins 107 from those portions of thesubstrate 101 that remain unremoved. For convenience thefins 107 have been illustrated in the figures as being separated from thesubstrate 101 by a dashed line, although a physical indication of the separation may or may not be present. Thesefins 107 may be used, as discussed below, to form the channel region of multiple-gate FinFET transistors. WhileFIG. 1 only illustrates twofins 107 formed from thesubstrate 101, any number offins 107 may be utilized. - The
fins 107 may be formed such that they have a width at the surface of thesubstrate 101 of between about 5 nm and about 80 nm, such as about 30 nm. Additionally, thefins 107 may be spaced apart from each other by a distance of between about to nm and about 100 nm, such as about 50 nm. By spacing thefins 107 in such a fashion, thefins 107 may each form a separate channel region while still being close enough to share a common gate (discussed further below). - Once the
first trenches 103 and thefins 107 have been formed, thefirst trenches 103 may be filled with a dielectric material and the dielectric material may be recessed within thefirst trenches 103 to form thefirst isolation regions 105. The dielectric material may be an oxide material, a high-density plasma (HDP) oxide, or the like. The dielectric material may be formed, after an optional cleaning and lining of thefirst trenches 103, using either a chemical vapor deposition (CVD) method (e.g., the HARP process), a high density plasma CVD method, or other suitable method of formation as is known in the art. - The
first trenches 103 may be filled by overfilling thefirst trenches 103 and thesubstrate 101 with the dielectric material and then removing the excess material outside of thefirst trenches 103 and thefins 107 through a suitable process such as chemical mechanical polishing (CMP), an etch, a combination of these, or the like. In an embodiment, the removal process removes any dielectric material that is located over thefins 107 as well, so that the removal of the dielectric material will expose the surface of thefins 107 to further processing steps. - Once the
first trenches 103 have been filled with the dielectric material, the dielectric material may then be recessed away from the surface of thefins 107. The recessing may be performed to expose at least a portion of the sidewalls of thefins 107 adjacent to the top surface of thefins 107. The dielectric material may be recessed using a wet etch by dipping the top surface of thefins 107 into an etchant such as HF, although other etchants, such as H2, and other methods, such as a reactive ion etch, a dry etch with etchants such as NH3/NF3, chemical oxide removal, or dry chemical clean may be used. The dielectric material may be recessed to a distance from the surface of thefins 107 of between about 50 Å and about 500 Å, such as about 400 Å. Additionally, the recessing may also remove any leftover dielectric material located over thefins 107 to ensure that thefins 107 are exposed for further processing. - As one of ordinary skill in the art will recognize, however, the steps described above may be only part of the overall process flow used to fill and recess the dielectric material. For example, lining steps, cleaning steps, annealing steps, gap filling steps, combinations of these, and the like may also be utilized to form and fill the
first trenches 103 with the dielectric material. All of the potential process steps are fully intended to be included within the scope of the present embodiment. - After the
first isolation regions 105 have been formed, adummy gate dielectric 109, adummy gate electrode 111 over thedummy gate dielectric 109, andfirst spacers 113 may be formed over each of thefins 107. In an embodiment the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or any other methods known and used in the art for forming a gate dielectric. Depending on the technique of gate dielectric formation, the dummy gate dielectric 109 thickness on the top of thefins 107 may be different from the gate dielectric thickness on the sidewall of thefins 107. - The dummy gate dielectric 109 may comprise a material such as silicon dioxide or silicon oxynitride with a thickness ranging from about 3 angstroms to about 100 angstroms, such as about to angstroms. The dummy gate dielectric 109 may be formed from a high permittivity (high-k) material (e.g., with a relative permittivity greater than about 5) such as lanthanum oxide (La2O3), aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), or zirconium oxide (ZrO2), or combinations thereof, with an equivalent oxide thickness of about 0.5 angstroms to about 100 angstroms, such as about to angstroms or less. Additionally, any combination of silicon dioxide, silicon oxynitride, and/or high-k materials may also be used for the
dummy gate dielectric 109. - The
dummy gate electrode 111 may comprise a conductive material and may be selected from a group comprising of W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like. Thedummy gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputter deposition, or other techniques known and used in the art for depositing conductive materials. The thickness of thedummy gate electrode 111 may be in the range of about 5 Å to about 200 Å. The top surface of thedummy gate electrode 111 may have a non-planar top surface, and may be planarized prior to patterning of thedummy gate electrode 111 or gate etch. Ions may or may not be introduced into thedummy gate electrode 111 at this point. Ions may be introduced, for example, by ion implantation techniques. - Once formed, the
dummy gate dielectric 109 and thedummy gate electrode 111 may be patterned to form a series ofstacks 115 over thefins 107. Thestacks 115 define multiple channel regions located on each side of thefins 107 beneath thedummy gate dielectric 109. Thestacks 115 may be formed by depositing and patterning a gate mask (not separately illustrated inFIG. 1 ) on thedummy gate electrode 111 using, for example, deposition and photolithography techniques known in the art. The gate mask may incorporate commonly used masking and sacrificial materials, such as (but not limited to) silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and/or silicon nitride and may be deposited to a thickness of between about 5 Å and about 200 Å. The dummy gate electrode iii and the dummy gate dielectric 109 may be etched using a dry etching process to form the patterned stacks 115. - Once the
stacks 115 have been patterned, thefirst spacers 113 may be formed. Thefirst spacers 113 may be formed on opposing sides of thestacks 115. Thefirst spacers 113 are typically formed by blanket depositing a spacer layer (not separately illustrated inFIG. 1 ) on the previously formed structure. The spacer layer may comprise SiN, oxynitride, SiC, SiON, SiOCN, SiOC, oxide, and the like and may be formed by methods utilized to form such a layer, such as chemical vapor deposition (CVD), plasma enhanced CVD, sputter, and other methods known in the art. The spacer layer may comprise a different material with different etch characteristics or the same material as the dielectric material within thefirst isolation regions 105. Thefirst spacers 113 may then be patterned, such as by one or more etches to remove the spacer layer from the horizontal surfaces of the structure, to form thefirst spacers 113. - In an embodiment the
first spacers 113 may be formed to have a thickness of between about 5 Å and about 500 Å, such as about 50 Å. Additionally, once thefirst spacers 113 have been formed, afirst spacer 113 adjacent to onestack 115 may be separated from afirst spacer 113 adjacent to anotherstack 115 by a distance of between about 5 nm and about 200 nm, such as about 20 nm. However, any suitable thicknesses and distances may be utilized. -
FIG. 2 illustrates a removal of thefins 107 from those areas not protected by thestacks 115 and thefirst spacers 113 and a regrowth of source/drain regions 201. The removal of thefins 107 from those areas not protected by thestacks 115 and thefirst spacers 113 may be performed by a reactive ion etch (RIE) using thestacks 115 and thefirst spacers 113 as hardmasks. However, any suitable process may be utilized. - Once these portions of the
fins 107 have been removed, a hard mask (not separately illustrated), is placed and patterned to cover the dummy gate electrode iii to prevent growth and the source/drain regions 201 may be regrown in contact with each of thefins 107. In an embodiment the source/drain regions 201 may be regrown and, in some embodiments the source/drain regions 201 may be regrown to form a stressor that will impart a stress to the channel regions of thefins 107 located underneath thestacks 115. In an embodiment wherein thefins 107 comprise silicon and the FinFET is a p-type device, the source/drain regions 201 may be regrown through a selective epitaxial process with a material, such as silicon or else a material such as silicon germanium that has a different lattice constant than the channel regions. In other embodiments the source/drain regions 201 may comprise materials such as GaAs, GaP, GaN, InP, InAs, InSb, GaAsP, AlGaN, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, combinations of these, or the like. The epitaxial growth process may use precursors such as silane, dichlorosilane, germane, and the like, and may continue for between about 5 minutes and about 120 minutes, such as about 30 minutes. - In an embodiment the source/
drain regions 201 may be formed to have a thickness of between about 5 Å and about 1000 Å, and may have a height over thefirst isolation regions 105 of between about 10 Å and about 500 Å, such as about 200 Å. In this embodiment, the source/drain regions 201 may be formed to have a height above the upper surface of thefirst isolation regions 105 of between about 5 nm and about 250 nm, such as about 100 nm. However, any suitable height may be utilized. - Once the source/
drain regions 201 are formed, dopants may be implanted into the source/drain regions 201 by implanting appropriate dopants to complement the dopants in thefins 107. For example, p-type dopants such as boron, gallium, indium, or the like may be implanted to form a PMOS device. In another embodiment, n-type dopants such as phosphorous, arsenic, antimony, or the like may be implanted to form an NMOS device. These dopants may be implanted using thestacks 115 and thefirst spacers 113 as masks. It should be noted that one of ordinary skill in the art will realize that many other processes, steps, or the like may be used to implant the dopants. For example, one of ordinary skill in the art will realize that a plurality of implants may be performed using various combinations of spacers and liners to form source/drain regions having a specific shape or characteristic suitable for a particular purpose. Any of these processes may be used to implant the dopants, and the above description is not meant to limit the present invention to the steps presented above. - Additionally at this point the hard mask that cover the
dummy gate electrode 111 during the formation of the source/drain regions 201 is removed. In an embodiment the hard mask may be removed using, e.g., a wet or dry etching process that is selective to the material of the hard mask. However, any suitable removal process may be utilized. - Once the hard mask has been removed, a first etch stop layer 204 (not separately illustrated in
FIG. 2 for clarity but illustrated and seen inFIG. 3 below) may be deposited. In an embodiment the firstetch stop layer 204 may be formed of silicon oxide or silicon nitride using plasma enhanced chemical vapor deposition (PECVD), although other materials such as SiON, SiCON, SiC, SiOC, SiCxNy, SiOx, other dielectrics, combinations thereof, or the like, and other techniques of forming the firstetch stop layer 204, such as low pressure CVD (LPCVD), PVD, or the like, could also be used. The firstetch stop layer 204 may have a thickness of between about 5 Å and about 500 Å. -
FIG. 2 also illustrates a formation of an inter-layer dielectric (ILD) layer 203 (illustrated in dashed lines inFIG. 2 in order to more clearly illustrate the underlying structures) over thestacks 115 and the source/drain regions 201. TheILD layer 203 may comprise a material such as boron phosphorous silicate glass (BPSG), although any suitable dielectrics may be used. TheILD layer 203 may be formed using a process such as PECVD, although other processes, such as LPCVD, may be used. TheILD layer 203 may be formed to a thickness of between about 100 Å and about 3,000 Å. Once formed, theILD layer 203 may be planarized with thefirst spacers 113 using, e.g., a planarization process such as chemical mechanical polishing process, although any suitable process may be utilized. -
FIG. 3 illustrates a cross sectional view of the structure ofFIG. 2 along line 3-3′ while also showing additional structures not illustrated inFIG. 2 , and also illustrates that, after the formation of theILD layer 203, the material of the dummy gate electrode tit and the dummy gate dielectric 109 may be removed and replaced to form agate stack 205. In an embodiment the dummy gate electrode tit and, if desired, the dummy gate dielectric 109 may be removed using, e.g., a wet or dry etching process that utilizes etchants that are selective to the material of the dummy gate electrode tn. However, any suitable removal process may be utilized. - Once the dummy gate electrode tit has been removed, the openings left behind may be refilled to form a
gate stack 205. In a particular embodiment thegate stack 205 comprises a first dielectric material, a first metal material, a second metal material, and a third metal material. In an embodiment the first dielectric material is a high-k material such as HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO, Ta2O5, combinations of these, or the like, deposited through a process such as atomic layer deposition, chemical vapor deposition, or the like. The first dielectric material may be deposited to a thickness of between about 5 Å and about 200 Å, although any suitable material and thickness may be utilized. - The first metal material may be formed adjacent to the first dielectric material and may be formed from a metallic material such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. The first metal material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like, to a thickness of between about 5 Å and about 200 Å, although any suitable deposition process or thickness may be used.
- The second metal material may be formed adjacent to the first metal material and, in a particular embodiment, may be similar to the first metal material. For example, the second metal material may be formed from a metallic material such as Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, WN, other metal oxides, metal nitrides, metal silicates, transition metal-oxides, transition metal-nitrides, transition metal-silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, combinations of these, or the like. Additionally, the second metal material may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like, to a thickness of between about 5 Å and about 200 Å, although any suitable deposition process or thickness may be used.
- The third metal material fills a remainder of the opening left behind by the removal of the
dummy gate electrode 111. In an embodiment the third metal material is a metallic material such as W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like, and may be deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like to fill and/or overfill the opening left behind by the removal of thedummy gate electrode 111. In a particular embodiment the third metal material may be deposited to a thickness of between about 5 Å and about 500 Å, although any suitable material, deposition process, and thickness may be utilized. - Once the opening left behind by the removal of the dummy gate electrode iii has been filled, the materials may be planarized in order to remove any material that is outside of the opening left behind by the removal of the
dummy gate electrode 111. In a particular embodiment the removal may be performed using a planarization process such as chemical mechanical polishing. However, any suitable planarization and removal process may be utilized. - Optionally, after the materials of the
gate stack 205 have been formed and planarized, the materials of thegate stack 205 may be recessed and capped with aconductive capping layer 301 and adielectric capping layer 303. In an embodiment the materials of thegate stack 205 may be recessed using, e.g., a wet or dry etching process that utilizes etchants selective to the materials of thegate stack 205. In an embodiment the materials of thegate stack 205 may be recessed a distance of between about 5 nm and about 150 nm, such as about 120 nm. However, any suitable process and distance may be utilized. - Once the materials of the
gate stack 205 have been recessed, theconductive capping layer 301 may be deposited within the recess on the materials of thegate stack 205 using a selective deposition process. In some embodiments, the selective deposition is a fluorine-free tungsten deposition, and hence, theconductive capping layer 301 can be free of fluorine. In some embodiments, the selective deposition process, which further is a fluorine-free tungsten deposition, is an ALD process that uses a hydrogen (H2) precursor and a tungsten chloride precursor. In other embodiments, the selective deposition process is a CVD process such as an MOCVD process using a tungsten chloride precursor. The tungsten chloride precursor can be tungsten pentachloride, tungsten hexachloride, another tungsten chloride, or a combination thereof. In some embodiments, theconductive capping layer 301 is formed to a height in a range of 2.5 nm to 3.3 nm. However, any suitable dimensions may be utilized. - The
dielectric capping layer 303 may be deposited and planarized with thefirst spacers 113. In an embodiment thedielectric capping layer 303 is a material such as SiN, SiON, SiCON, SiC, SiOC, combinations of these, or the like, deposited using a deposition process such as atomic layer deposition, chemical vapor deposition, sputtering, or the like. Thedielectric capping layer 303 may be deposited to a thickness of between about 5 Å and about 200 Å, and then planarized using a planarization process such as chemical mechanical polishing such that thedielectric capping layer 303 is planar with thefirst spacers 113. - Once the
dielectric capping layer 303 has been planarized,contacts 305 are formed through theILD layer 203 and the firstetch stop layer 204 to make physical and electrical contact with the source/drain regions 201. In an embodiment thecontacts 305 may be formed by initially forming source/drain contact openings through theILD layer 203 and the firstetch stop layer 204. In an embodiment the source/drain contact openings can be formed using one or more etching processes to sequentially etch through theILD layer 203 and the firstetch stop layer 204. However, any suitable process or processes may be used to form the source/drain contact openings and expose the source/drain regions 201. - Once the source/
drain regions 201 have been exposed, an optional silicide contact (not separately illustrated) may be formed on the source/drain regions 201. The silicide contact may comprise titanium, nickel, cobalt, or erbium in order to reduce the Schottky barrier height of the contact. However, other metals, such as platinum, palladium, and the like, may also be used. The silicidation may be performed by blanket deposition of an appropriate metal layer, followed by an annealing step which causes the metal to react with the underlying exposed silicon. Un-reacted metal is then removed, such as with a selective etch process. The thickness of the silicide contact may be between about 5 nm and about 50 nm. - Once the silicide contacts have been formed, the
contacts 305 are formed. In an embodiment thecontacts 305 may be a conductive material such as Co, W, Al, Cu, Ti, Ta, Ru, TiN, TiAl, TiAlN, TaN, TaC, NiSi, CoSi, combinations of these, or the like, although any suitable material may be deposited using a deposition process such as sputtering, chemical vapor deposition, electroplating, electroless plating, or the like, to fill and/or overfill the opening. Once filled or overfilled, any deposited material outside of the opening may be removed using a planarization process such as chemical mechanical polishing (CMP). However, any suitable material and process of formation may be utilized. -
FIG. 3 continues by illustrating a formation of a secondetch stop layer 307 over the gate stacks 205. In an embodiment the secondetch stop layer 307 may be formed of silicon nitride or silicon oxide using plasma enhanced chemical vapor deposition (PECVD), although other materials such as SiON, SiCON, SiC, SiOC, SiCxNy, SiOx, other dielectrics, combinations thereof, or the like, and other techniques of forming the secondetch stop layer 307, such as low pressure CVD (LPCVD), PVD, or the like, could be used. The secondetch stop layer 307 may have a thickness of between about 5 Å and about 500 Å. -
FIG. 3 additionally illustrates a formation of asecond ILD layer 311. Thesecond ILD layer 311 may comprise an oxide material such as SiOx, SiON, SiCON, SiC, SiOC, SiCxNy, although any other suitable materials, such as boron phosphorous silicate glass (BPSG) or any other low-k dielectric layers, may be used. Thesecond ILD layer 311 may be formed using a process such as PECVD, although other processes, such as LPCVD, may also be used. Thesecond ILD layer 311 may be formed to a thickness of between about 70 Å and about 3,000 Å, such as 700 Å. Once formed, thesecond ILD layer 311 may be planarized using, e.g., a planarization process such as a chemical mechanical polishing process, although any suitable process may be utilized. -
FIG. 4 illustrates a formation of a photoresist over thesecond ILD layer 311 in preparation for forming openings to the source/drain regions 201. In an embodiment the photoresist may comprise a bottom anti-reflective coating (BARC)layer 401, anintermediate mask layer 403, and a first topphotosensitive layer 405. TheBARC layer 401 is applied in preparation for an application of the first topphotosensitive layer 405. TheBARC layer 401, as its name suggests, works to prevent the uncontrolled and undesired reflection of energy (e.g., light) back into the overlying first topphotosensitive layer 405 during an exposure of the first topphotosensitive layer 405, thereby preventing the reflecting light from causing reactions in an undesired region of the first topphotosensitive layer 405. Additionally, theBARC layer 401 may be used to provide a planar surface, helping to reduce the negative effects of the energy impinging at an angle. - The
intermediate mask layer 403 may be placed over theBARC layer 401. In an embodiment theintermediate mask layer 403 is a hard mask material such as silicon nitride, oxides, oxynitrides, silicon carbide, combinations of these, or the like. The hard mask material for theintermediate mask layer 403 may be formed through a process such as chemical vapor deposition (CVD), although other processes, such as plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), spin-on coating, or even silicon oxide formation followed by nitridation, may be utilized. Any suitable method or combination of methods to form or otherwise place the hardmask material may be utilized, and all such methods or combination are fully intended to be included within the scope of the embodiments. Theintermediate mask layer 403 may be formed to a thickness of between about 100 Å and about 800 Å, such as about 300 Å. - In an embodiment the first top
photosensitive layer 405 is applied over theintermediate mask layer 403 using, e.g., a spin-on process, and includes a photoresist polymer resin along with one or more photoactive compounds (PACs) in a photoresist solvent. Once each of theBARC layer 401, theintermediate mask layer 403, and the first topphotosensitive layer 405 have been applied, the first topphotosensitive layer 405 is exposed to a patterned energy source (e.g., light). The PACs will absorb the patterned light source and generate a reactant in those portions of the first topphotosensitive layer 405 that are exposed, thereby causing a subsequent reaction with the photoresist polymer resin that can be developed in order to replicate the patterned energy source within the first topphotosensitive layer 405. Once the reaction has occurred, the first topphotosensitive layer 405 is developed in order to createfirst openings 407 within the first topphotosensitive layer 405. -
FIG. 5 illustrates that, once thefirst openings 407 have been formed within the first topphotosensitive layer 405, the first topphotosensitive layer 405 may then be used as a mask to extend the pattern into theintermediate mask layer 403 and theBARC layer 401 using one or more etching processes. Similarly, once theintermediate mask layer 403 and theBARC layer 401 have been patterned, theintermediate mask layer 403 and theBARC layer 401 may be utilized as masks to extend thefirst openings 407 through theILD layer 203 and the secondetch stop layer 307 to expose thecontacts 305. - In a particular embodiment, the extension may be performed using a series of dry etches with different etchants, diluents, combinations thereof, or the like. For example, an etching process using a combination of methane and nitrogen followed by an etching process utilizing nitrogen may be used, and then an etching process using a combination of CF4, nitrogen, argon, and hydrogen may be used to etch through the
intermediate mask layer 403. The pattern may then be extended through theBARC layer 401 using a first etch with nitrogen and hydrogen followed by an etch using a combination of carbonyl sulfide (COS), oxygen and nitrogen. - Once the
BARC layer 401 has been etched, an etch utilizing CF4, CHF3, nitrogen and argon followed by an etch using C4F6, oxygen and argon may be used to etch through theILD layer 203. Once thefirst ILD layer 203 has been etched, an oxygen strip may be used to remove the first topphotosensitive layer 405. Then, a series of liner removal etches utilizing CH3F and hydrogen may be utilized in order to extend the pattern through the secondetch stop layer 307. Finally, a last etch utilizing nitrogen and hydrogen may be used. - However, while a very particular set of etches has been described above, this description is intended to be illustrative and is not intended to be limiting. Rather, any suitable etch or combination of etches may be used to extend the
first opening 407 through the various layers in order to expose thecontacts 305. All such etches or combination of etches are fully intended to be included within the scope of the embodiments. -
FIG. 6 illustrates formation of arecess 601 within thecontact 305. In an embodiment therecess 601 may be formed by removing material of the contact 305 (e.g., cobalt) using an etching process such as a wet etch or a dry etch using etchants that are selective to the material of thecontact 305. Additionally, therecess 601 may be formed to extend into the contact 305 a first distance D1 of between about 5 nm and about 10 nm. However, any suitable distance and any suitable method of recessing the material may be utilized. -
FIG. 6 also illustrates that, once therecess 601 has been formed, a treatment may be performed on the exposed surface of thecontact 305 in order to help prevent selective growth of subsequently deposited material along the sidewalls of thefirst openings 407. In an embodiment the treatment may be an oxidation treatment which treats the sidewalls but which will also react with the exposed material of thecontact 305 to form abase layer 603 such as an oxide base layer along the exposed surfaces of therecesses 601. In an embodiment thebase layer 603 may be formed as a native oxide material, whereby the exposed material of thecontact 305 is oxidized either intentionally or through an exposure to an oxygen containing ambient atmosphere to form the oxide material. In an embodiment in which the exposed material is intentionally oxidized, the oxidation can occur through a process such as an ion bombardment with oxygen followed by an ashing process in an ambient air environment. As such, thebase layer 603 is formed adjacent to thecontact 305 along a bottom of therecess 601 and may have a thickness of about 6 nm. - However, while multiple oxidation processes for forming the
base layer 603 within therecess 601 have been described, these are intended to be illustrative and are not intended to be limiting. Rather, any suitable method of forming thebase layer 603 may be utilized. All such methods are fully intended to be included within the scope of the embodiments. -
FIGS. 7A-7E illustrate a treatment process (represented inFIG. 7A by the wavy lines labeled 701) which may be used in order to partially or completely remove thebase layer 603 without material segregation and prepare thecontact 305 to receive an overlying conductive contact 801 (not illustrated inFIGS. 7A-7E but illustrated and discussed further below with respect toFIG. 8 ).FIG. 7B illustrates that, to initiate thetreatment process 701, thecontact 305 with the base layer 603 (along with the remaining structure) may be placed within afirst treatment system 700 that may, for example, use a remote plasma system as part of thetreatment process 701. - In an embodiment the
first treatment system 700 may receive a first treatment precursor from a firstprecursor delivery system 705 which works to supply the desired precursor material to thetreatment chamber 703 through, e.g., aprecursor gas controller 713. In an embodiment, the firstprecursor delivery system 705 may include agas supply 707 and aflow controller 709, wherein thegas supply 707 may be a vessel, such as a gas storage tank, that is located either locally to thetreatment chamber 703 or else may be located remotely from thetreatment chamber 703. In another embodiment, thegas supply 707 may be a facility that independently prepares and delivers the first treatment precursor to theflow controller 709. Any suitable source for the first treatment precursor may be utilized as thegas supply 707, and all such sources are fully intended to be included within the scope of the embodiments. - Additionally, in an embodiment in which the first treatment precursor is stored in a solid or liquid state, the
gas supply 707 may store a carrier gas and the carrier gas may be introduced into a precursor canister (not separately illustrated), which stores the first treatment precursor in the solid or liquid state. The carrier gas is then used to push and carry the first treatment precursor as it either evaporates or sublimates into a gaseous section of the precursor canister before being sent to theprecursor gas controller 713. Any suitable method and combination of units may be utilized to provide the first treatment precursor, and all such combination of units are fully intended to be included within the scope of the embodiments. - The
gas supply 707 may supply the desired first treatment precursor to theflow controller 709. Theflow controller 709 may be utilized to control the flow of the first treatment precursor to theprecursor gas controller 713 and, eventually, to thetreatment chamber 703, thereby also helping to control the pressure within thetreatment chamber 703. Theflow controller 709 may be, e.g., a proportional valve, a modulating valve, a needle valve, a pressure regulator, a mass flow controller, combinations of these, or the like. However, any suitable method for controlling and regulating the flow of the first treatment precursor to theprecursor gas controller 713 may be utilized, and all such components and methods are fully intended to be included within the scope of the embodiments. - However, as one of ordinary skill in the art will recognize, while the first
precursor delivery system 705 has been described herein as having particular components, this is merely an illustrative example and is not intended to limit the embodiments in any fashion. Any type of suitable precursor delivery system, with any type and number of individual components, may be utilized. All such precursor delivery systems are fully intended to be included within the scope of the embodiments. - The first
precursor delivery system 705 may supply its precursor materials into theprecursor gas controller 713 which may connect and isolate the firstprecursor delivery system 705 to and from thetreatment chamber 703 in order to deliver the desired precursor material to thetreatment chamber 703 at a desired rate. Theprecursor gas controller 713 may include such devices as valves, flow meters, sensors, and the like to control the delivery rate of the first treatment precursor, and may be controlled by instructions received from thecontrol unit 715. Theprecursor gas controller 713, upon receiving instructions from thecontrol unit 715, may open and close valves so as to connect the firstprecursor delivery system 705 to thetreatment chamber 703 and direct the desired treatment through a manifold 716 to aplasma block 720. -
FIG. 7C illustrates an embodiment of the plasma block 720 (or plasma generator) fromFIG. 7B in greater detail. In an embodiment theplasma block 720 has aninlet port 731 that receives the first treatment precursor from theprecursor gas controller 713 and anoutlet port 733 that is coupled to deliver a first treatment plasma 721 (converted from the first treatment precursor and not illustrated inFIG. 7C but seen inFIG. 7B ) to thetreatment chamber 703. The first treatment precursor enters theplasma block 720 and passes between amagnetic core 735 that surrounds a portion of theplasma block 720. Themagnetic core 735 is utilized to induce the formation of thefirst treatment plasma 721 from the first treatment precursor that enters theplasma block 720 before exiting out of theoutlet port 733. - The
magnetic core 735 may be situated around a portion of the flow path through theplasma block 720 from theinlet port 731 to theoutlet port 733. In an embodiment themagnetic core 735 is one portion of a transformer 737 (illustrated inFIG. 7C with dashed line 737), with aprimary coil 739 forming another portion of thetransformer 737. In an embodiment theprimary coil 739 may have a winding of between about 100 and about 1000 such as about 600. - To generate the desired
first treatment plasma 721 from the first treatment precursor within theplasma block 720, a short, high-voltage pulse of electricity controlled, e.g., by the control unit 715 (seeFIG. 7B ) may be applied to theprimary coil 739. The high-voltage pulse of electricity in theprimary coil 739 is transformed to a pulse of energy into themagnetic core 735, which induces the formation of thefirst treatment plasma 721 within theplasma block 720. In an embodiment the high-voltage pulse may be between about to kHz and about 30 MHz such as about 13.56 MHz, while the temperature is between about 50° C. and about 200° C. and with a pressure of between about 1 torr and about 20 torr. - However, while igniting the first treatment precursor with a magnetic coil is described as an embodiment that may be used with the embodiments, the embodiments are not so limited. Rather, any suitable method or structures may be used to ignite the first treatment precursor to form the
first treatment plasma 721. For example, in other embodiments a high voltage pulse may be applied to an electrode (not illustrated) coupled to theplasma block 720, or the first treatment precursor may be exposed to a ultraviolet radiation that may be used to ignite the first treatment precursor and form thefirst treatment plasma 721. Any suitable method of igniting the first treatment precursor and any other suitable plasma inducing device are fully intended to be included within the scope of the embodiments. - The
plasma block 720 comprises a circular path between theinlet port 731 and theoutlet port 733 in which the first treatment precursor may travel. In an embodiment the circular path may have a first length L1 of between about 100 mm and about 500 mm, such as about 250 mm, and a first width W1 of between about 100 mm and about 500 mm such as about 250 mm. Similarly, the interior of the circular path through the plasma block may have a second distance D2 of between about 20 mm and about 150 mm, such as about 70 mm. However, any other suitable structure or shape may be utilized. - The
plasma block 720 also comprises aninner housing 741 and aninsulator 743 surrounding theinner housing 741. Theinsulator 743 may be used to electrically and thermally isolate theinner housing 741 of theplasma block 720. In an embodiment theinner housing 741 encloses and encapsulates the circular path of the first treatment precursor and (after ignition) thefirst treatment plasma 721 in order to guide the first treatment precursor and thefirst treatment plasma 721 through theplasma block 720. - The
plasma block 720 may also comprise asensor 745 that may be used to measure the conditions within theplasma block 720. In an embodiment thesensor 745 may be a current probe used to measure the current and power of the plasma as part of a feedback loop to the control unit 715 (seeFIG. 7B ). In addition, thesensor 745 may also comprise an optical sensor or any other measurement devices that may be used to measure and control the plasma generation within theplasma block 720. - Returning now to
FIG. 7B , once thefirst treatment plasma 721 has been generated, thefirst treatment plasma 721 may be directed into thetreatment chamber 703. Thetreatment chamber 703 may receive thefirst treatment plasma 721 and expose thefirst treatment plasma 721 to thecontact 305, and thetreatment chamber 703 may be any desired shape that may be suitable for dispersing thefirst treatment plasma 721 and contacting thefirst treatment plasma 721 with thecontact 305. In the embodiment illustrated inFIG. 7B , thetreatment chamber 703 has a cylindrical sidewall and a bottom. However, thetreatment chamber 703 is not limited to a cylindrical shape, and any other suitable shape, such as a hollow square tube, an octagonal shape, or the like, may be utilized. Furthermore, thetreatment chamber 703 may be surrounded by ahousing 719 made of material that is inert to the various process materials. As such, while thehousing 719 may be any suitable material that can withstand the chemistries and pressures involved in the deposition process, in an embodiment thehousing 719 may be steel, stainless steel, nickel, aluminum, alloys of these, combinations of these, and like. - Within the
treatment chamber 703 thecontact 305 may be placed on a mountingplatform 722 in order to position and control thecontact 305 during thetreatment process 701. Thetreatment chamber 703 may also have anexhaust outlet 725 for exhaust gases to exit thetreatment chamber 703. Avacuum pump 724 may be connected to theexhaust outlet 725 of thetreatment chamber 703 in order to help evacuate the exhaust gases. Thevacuum pump 724, under control of thecontrol unit 715, may also be utilized to reduce and control the pressure within thetreatment chamber 703 to a desired pressure and may also be utilized to evacuate precursor materials from thetreatment chamber 703. - In a specific embodiment, the
treatment process 701 is initiated by putting the first treatment precursor into the firstprecursor delivery system 705 or having the first treatment precursor formed by the firstprecursor delivery system 705. In an embodiment the first treatment precursor may be a precursor which can reduce and remove thebase layer 603, but which will also help to reduce and/or prevent the remaining material of the contact 305 (e.g., cobalt) from segregating and causing voids to occur along the surface of thecontact 305. In a particular embodiment the first treatment precursor may be hydrogen (H2), oxygen (O2), argon (Ar), combinations of these, or the like. However, any suitable precursor may be utilized. - Additionally, in an embodiment in which the first treatment precursor is a gas, a diluent gas is utilized to help carry the first treatment precursor and also to help assist with the ignition of the plasma. In some embodiments the diluent gas may be a gas such as argon, nitrogen, helium, combinations of these, or the like. The diluent gas may be added either within the first
precursor delivery system 705 itself, or else may be added separately and then combined with the first treatment precursor within the manifold 716 exiting theprecursor gas controller 713. However, any suitable diluent gas and any suitable method of mixing may be utilized. - Once the first treatment precursor and the diluent gas have been placed into the first
precursor delivery system 705, thetreatment process 701 may be initiated by thecontrol unit 715 sending an instruction to theprecursor gas controller 713 to connect the firstprecursor delivery system 705 to themanifold 716. In an embodiment flow rates within the manifold 716 may be controlled such that the first treatment precursor (e.g., H2) to diluent gas (e.g., argon) flow rate ratio is between about 1:1 and about 1:2. If the ratio of the diluent gas (e.g., argon) is above this amount, the ion dissociation of the first treatment precursor (e.g., hydrogen) is satiated and it would not participate in the reactions. Additionally, if the ratio of the diluent gas is below this range, the amount of the diluent gas is not sufficient to help the first treatment precursor dissociate. - Once the first treatment precursor is within the
manifold 716, the first treatment precursor may enter theplasma block 720. In theplasma block 720 the first treatment precursor and the carrier gas will be converted into thefirst treatment plasma 721. Once converted, thefirst treatment plasma 721 is then sent into thetreatment chamber 703. - During the
treatment process 701, the ambient conditions may be kept at a pressure and temperature which helps to remove thebase layer 603 while still reducing or preventing segregation of the material of the contact 305 (e.g., cobalt). For example, in some embodiments the ambient conditions within thetreatment chamber 703 may have a pressure of between about 1 T and about 2 T, and thetreatment chamber 703 may be kept at a temperature of between about 200° C. and about 300° C. Additionally, thetreatment process 701 may be performed at a power of between about 1000 W and about 2000 W for a time of between about 90 seconds and about 180 seconds. However, any suitable conditions may be utilized. - Once in the
treatment chamber 703, thefirst treatment plasma 721 will begin to react with thebase layer 603 and start removing thebase layer 603, withFIG. 7A showing a partial reaction wherein a part of thebase layer 603 is reduced. However, by utilizing the processes discussed herein, the partial removal of thebase layer 603 will not cause the underlying material of the contact 305 (e.g., cobalt) to segregate into different crystalline regions. By preventing or at least minimizing segregation of the material of thecontact 305, a smoother and cleaner surface of thecontact 305 may be achieved. -
FIG. 7D illustrates that, while thefirst treatment 701 may be stopped at any suitable time (e.g., thefirst treatment 701 may be stopped after a portion, but not all, of thebase layer 603 has been removed), in some embodiments thefirst treatment 701 may be continued until thebase layer 603 has been completely removed. As such, thecontact 305 is exposed without any portion of thebase layer 603 being present. -
FIG. 7E illustrates that, optionally at this point, after the remote plasma treatment of thefirst treatment 701 has been performed, a second plasma treatment may be performed. In an embodiment the second plasma treatment may not be a remote plasma treatment, but instead the plasma may be generated directly over the structure, such as a charge coupled plasma generation. For example, and as illustrated inFIG. 7E thecontact 305 may be placed in asecond treatment system 750 for the second plasma treatment. - In an embodiment the
second treatment system 750 may be a different system from thefirst treatment system 700, but may still have many similar components, such that, for clarity, similar components are labeled similarly as the components described above with respect to thefirst treatment system 700. In other embodiments, thesecond treatment system 750 may actually be the same physical structure as thefirst treatment system 700, wherein thefirst treatment system 700 comprises all of the equipment described as follows. In such an embodiment pieces of equipment that are not utilized as part of the second plasma treatment, such as theplasma block 720 are not illustrated inFIG. 7E because they are not in use, but may still be physically present. - In an embodiment, the
second treatment system 750, in addition to the structures already described above, also comprises anupper electrode 751, for use as a plasma generator. In an embodiment the plasma generator may be a transformer coupled plasma generator and may be, e.g., a coil. The coil may be attached to afirst RF generator 753 that is utilized to provide power to the upper electrode 751 (under control of the control unit 715) in order to ignite the plasma during introduction of, e.g., a second treatment precursor. - However, while the
upper electrode 751 is described above as a transformer coupled plasma generator, embodiments are not intended to be limited to a transformer coupled plasma generator. Rather, any suitable method of generating the plasma, such as inductively coupled plasma systems, an electron cyclotron resonance, or the like, may also be utilized. All such methods are fully intended to be included within the scope of the embodiments. - Additionally in this embodiment, the mounting
platform 722 may additionally comprise asecond electrode 755 coupled to asecond RF generator 757. Thesecond electrode 755 may be electrically biased by the second RF generator 757 (under control of the control unit 715) at a RF voltage during the treatment process. By being electrically biased, thesecond electrode 755 is used to provide a bias to the incoming plasmas and assist to ignite them into a plasma. Additionally, thesecond electrode 755 is also utilized to maintain the plasma during the process by maintaining the bias. - To start the process, the first treatment precursor can again be placed in the first
precursor delivery system 705. In an embodiment the first precursor delivery may be used by itself or else with the diluent gas as described above. Additionally, thecontact 305 will be placed or else remain on the mountingplatform 722, and the first treatment precursor is introduced to thetreatment chamber 703 as a gas (not a plasma). - Once the first treatment precursor is present within the
treatment chamber 703, thecontrol unit 715 will perform an ignition step and ignite the first treatment precursor (or the combination of the first treatment precursor and diluent gas) into a plasma by setting the RF power at 60 MHz to between about 100 W and about 200 W at a pressure of between about 1 torr and about 5 torr and a temperature of between about And about 180° C. The ignition step may be maintained for a time of between about 4 s and about 30 s in order to ensure ignition of the plasma. - Additionally, while some embodiments utilize a single ignition of the first treatment precursor, other embodiments may utilize a number of cycles where the first treatment precursor is ignited. For example, the first treatment precursor may be ignited a first time and then allowed to return to a non-plasma state before being ignited again. This cycle may be repeated as many times as desired, such as three or more times, such as six cycles.
- By utilizing the optional direct bombardment process, a combined process can be achieved in order to achieve the benefits of the direct bombardment process (e.g., helping to ensure complete removal of the
base layer 603 at the end of the process), while also minimizing the amount of time that the direct bombardment process is used. With less time being used, less damage will also occur, thereby limiting the amount of defects that are present in the final structure. -
FIG. 8 illustrates a formation of conductive contacts 801 (on either embodiment in which thebase layer 603 is fully removed or not). Theconductive contacts 801 may comprise a conductive material such as W, Al, Cu, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations of these, or the like. In some embodiments, theconductive contacts 801 comprise tungsten. The conductive contacts may be formed by any suitable method, such as e.g. CVD, plasma-enhanced CVD (PECVD), MOCVD, thermal CVD, PVD, ALD, or the like. In some embodiments, a bottom-up deposition process is performed using a thermal CVD process. The bottom-up deposition process may be performed using WF6 and H2 as process gases (when tungsten is to be grown). However, any suitable materials and processes may be utilized. - The vertical growth of the
conductive contacts 801 may be controlled to produce heights of theconductive contacts 801 in a range of 48 nm to 67 nm, which may be advantageous for producingconductive contacts 801 with a desired height compatible with subsequent planarizations.Conductive contacts 801 with heights less than 48 nm may be shorter than a subsequent planarization, which may lead to a subsequently deposited dielectric layer covering top surfaces of the conductive contacts and decreasing performance.Conductive contacts 801 with heights greater than 67 nm may lead to overgrowth on the top surface of the IMD layer, which may lead to overburdening of a subsequent planarization. - In some embodiments, a germanium implantation process or germanium ion bombardment is performed on top surfaces of the
conductive contacts 801 in order to help strengthen an interface between theconductive contacts 801 and the surrounding layers. By strengthening the interface, the amount of CMP slurry that is subsequently applied during planarization processes (described further below) and that seeps down through cracks may be reduced. - Once the germanium implantation process has been performed, sacrificial or buffer layers (not separately illustrated) may be formed over the
conductive contacts 801 prior to a planarization process such as a CMP. In particular, because the formation processes may cause some top surfaces of theconductive contacts 801 to be concave and other top surfaces of theconductive contacts 801 to be convex, the subsequent CMP may trigger underpolishment or overpolishment defects. As such, the sacrificial layers may be formed on theconductive contacts 801 in order to reduce underpolishment or overpolishment defects by overburdening theconductive contacts 801 and as a stop line in CMP processing. In some embodiments, the sacrificial layers comprise one or more layers of Ti, TiN, and tungsten. The sacrificial layers of Ti and TiN may be formed using methods such as CVD, PVD, ALD, combinations of these, or the like. The sacrificial layer of tungsten may be formed using similar methods and materials as theconductive contacts 801. However, any suitable methods or materials may be used. -
FIG. 9 illustrates that, at this point, optional additional vias (only the top of which are illustrated inFIG. 9 ) through thesecond ILD layer 311 may be formed. In an embodiment the vias may be formed as described above with respect to theconductive contacts 801, such as by forming an opening into or through the second ILD layer and then filling and overfilling the opening with a conductive material (the overfilled portion of which is illustrated as overlying the conductive contacts 801). However, any suitable method of forming the additional vias may be utilized, and all such methods and materials are fully intended to be included within the scope of the embodiments. -
FIG. 10 illustrates that, once the material of the additional vias has been formed to fill and/or overfill the openings through thesecond ILD layer 311, any deposited material outside of the openings through thesecond ILD layer 311 may be removed using a planarization process such as chemical mechanical polishing (CMP). However, any suitable material and process of formation may be utilized. As such, theconductive contacts 801 and additional vias (which are not visible in the particular view illustrated inFIG. 10 ) are planarized to be coplanar with the material of thesecond ILD layer 311. -
FIG. 11 illustrates that, in some embodiments the planarization process or a separate planarization process may be further used in order to reduce the height of thesecond ILD layer 311 and remove any chapping profiles or other defects. In some embodiments the height of thesecond ILD layer 311 may be reduced by a distance of about 52 nm, such that thesecond ILD layer 311 may have an end height of between about to nm and about 25 nm, such as about 18 nm. However, any suitable height may be utilized. -
FIG. 11 also illustrates a formation of an IMD layer tow formed over theconductive contacts 801 to replace height lost by thesecond ILD layer 311 in the previous planarization process. The IMD layer tow may be formed using similar processes and materials as thesecond ILD layer 311 as described above with respect toFIG. 3 . However, any suitable processes or materials may be used. - Once the IMD layer tow has been formed, additional processing steps may be utilized in order to further completion of the overall semiconductor device. For example, additional metallization layers may be manufactured, one or more passivation layers may be deposited and patterned, and external connections may be placed in order to provide a pathway for power, ground, and signal connections to, from, and between the active devices and other devices within the semiconductor device. However, any other suitable steps and/or methods may be utilized to help manufacture the semiconductor device.
- However, by utilizing a remote plasma to help remove the base layer 607 from the
contact 305, the removal process will have a reduced amount of physical bombardment during the reduction and removal of the base layer 607. As such, there will be less physical damage that increases the amount of surface roughness of the underlying material of thecontact 305, and an overall reduction in the amount of segregation of the materials is achieved. The reduction in segregation also causes a reduction in voids that occur along the surface of thecontact 305. With fewer voids being formed, there is less intermixing between the top surface of thecontact 305 and the bottom surface of the overlyingconductive contact 801 and a cleaner interface between thecontact 305 and theconductive contact 801 may be achieved, thereby reducing loss of the material of the conductive contact 801 (e.g., reduction of tungsten loss) and increasing the overall yield. - In accordance with an embodiment, a method of manufacturing a semiconductor device includes: forming a contact to a source/drain region, the contact being adjacent to a semiconductor fin; depositing a dielectric layer over the contact; exposing the contact through the dielectric layer; placing the contact into a treatment chamber; generating a plasma outside of the treatment chamber; introducing the plasma to the treatment chamber; and depositing a conductive material in physical contact with the contact. In an embodiment the generating the plasma uses an inductively coupled plasma. In an embodiment the generating the plasma uses hydrogen as a precursor. In an embodiment the treatment chamber is kept at a pressure of between about 1 Torr and about 2 Torr during the introducing the plasma. In an embodiment the treatment chamber is kept at a temperature of about 200° C. during the introducing the plasma. In an embodiment the contact comprises cobalt. In an embodiment the introducing the plasma causes the cobalt to segregate no more than 50%.
- In accordance with another embodiment, a method of manufacturing a semiconductor device includes: forming an opening through a dielectric layer to expose a source/drain contact; oxidizing a portion of the source/drain contact to form a base layer; removing the base layer with a remote plasma process, the remote plasma process utilizing an inductively coupled hydrogen plasma; and depositing a conductive material onto the source/drain contact. In an embodiment the remote plasma process also utilizes an argon plasma. In an embodiment the removing the base layer is performed at a pressure of between about 1 Torr and about 2 Torr. In an embodiment the removing the base layer is performed at a temperature of about 200° C. In an embodiment the source/drain contact comprises cobalt. In an embodiment the conductive material comprises tungsten. In an embodiment the method further includes implanting germanium into the conductive material.
- In accordance with yet another embodiment, a method of manufacturing a semiconductor device includes: recessing a source/drain contact through an opening in a dielectric layer; oxidizing a top surface of the source/drain contact through the opening to form a base layer; removing the base layer with a hydrogen plasma and an argon plasma, wherein the hydrogen plasma and argon plasma are generated in a remote plasma unit; and depositing a conductive material into the opening. In an embodiment the source/drain contact comprises cobalt. In an embodiment the depositing the conductive material deposits tungsten. In an embodiment the method further includes implanting germanium into the conductive material. In an embodiment the method further includes planarizing the conductive material. In an embodiment the method further includes, after the removing the base layer with the hydrogen plasma and the argon plasma, exposing the source/drain contact to a second plasma generated using a charge coupled plasma generation process.
- The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (20)
1. A method of manufacturing a semiconductor device, the method comprising:
forming a contact to a source/drain region, the contact being adjacent to a semiconductor fin;
depositing a dielectric layer over the contact;
exposing the contact through the dielectric layer;
oxidizing a first portion of the contact;
removing the first portion with a remote plasma process, the remote plasma process utilizing an inductively coupled hydrogen plasma; and
depositing a conductive material in physical contact with the contact.
2. The method of claim 1 , wherein the depositing the conductive material deposits tungsten.
3. The method of claim 1 , wherein the remote plasma process uses hydrogen as a precursor.
4. The method of claim 1 , wherein the removing the first portion with the remote plasma process uses a pressure of between about 1 Torr and about 2 Torr.
5. The method of claim 4 , wherein the removing the first portion with the remote plasma process uses a temperature of about 200° C.
6. The method of claim 1 , wherein the contact comprises cobalt.
7. The method of claim 6 , wherein the remote plasma process causes the cobalt to segregate no more than 50%.
8. A method of manufacturing a semiconductor device, the method comprising:
forming an opening through a dielectric layer to expose a source/drain contact;
oxidizing a portion of the source/drain contact to form a base layer;
removing the base layer with a remote plasma process, the remote plasma process utilizing an inductively coupled hydrogen plasma; and
depositing a conductive material onto the source/drain contact.
9. The method of claim 8 , wherein the remote plasma process also utilizes an argon plasma.
10. The method of claim 8 , wherein the removing the base layer is performed at a pressure of between about 1 Torr and about 2 Torr.
11. The method of claim 10 , wherein the removing the base layer is performed at a temperature of about 200° C.
12. The method of claim 8 , wherein the source/drain contact comprises cobalt.
13. The method of claim 8 , wherein the conductive material comprises tungsten.
14. The method of claim 8 , further comprising implanting germanium into the conductive material.
15. A method of manufacturing a semiconductor device, the method comprising:
recessing a source/drain contact through an opening in a dielectric layer;
oxidizing a top surface of the source/drain contact through the opening to form a base layer;
removing the base layer with a hydrogen plasma and an argon plasma, wherein the hydrogen plasma and argon plasma are generated in a remote plasma unit; and
depositing a conductive material into the opening.
16. The method of claim 15 , wherein the source/drain contact comprises cobalt.
17. The method of claim 16 , wherein the depositing the conductive material deposits tungsten.
18. The method of claim 14 , further comprising implanting germanium into the conductive material.
19. The method of claim 18 , further comprising planarizing the conductive material.
20. The method of claim 14 , further comprising, after the removing the base layer with the hydrogen plasma and the argon plasma, exposing the source/drain contact to a second plasma generated using a charge coupled plasma generation process.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US18/447,212 US20230387222A1 (en) | 2021-03-10 | 2023-08-09 | Semiconductor device and method |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US202163158996P | 2021-03-10 | 2021-03-10 | |
US17/245,766 US11855153B2 (en) | 2021-03-10 | 2021-04-30 | Semiconductor device and method |
US18/447,212 US20230387222A1 (en) | 2021-03-10 | 2023-08-09 | Semiconductor device and method |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/245,766 Continuation US11855153B2 (en) | 2021-03-10 | 2021-04-30 | Semiconductor device and method |
Publications (1)
Publication Number | Publication Date |
---|---|
US20230387222A1 true US20230387222A1 (en) | 2023-11-30 |
Family
ID=83005580
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/245,766 Active 2041-09-19 US11855153B2 (en) | 2021-03-10 | 2021-04-30 | Semiconductor device and method |
US18/447,212 Pending US20230387222A1 (en) | 2021-03-10 | 2023-08-09 | Semiconductor device and method |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/245,766 Active 2041-09-19 US11855153B2 (en) | 2021-03-10 | 2021-04-30 | Semiconductor device and method |
Country Status (5)
Country | Link |
---|---|
US (2) | US11855153B2 (en) |
KR (1) | KR20220127115A (en) |
CN (1) | CN115084017A (en) |
DE (1) | DE102021112091A1 (en) |
TW (1) | TWI825439B (en) |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW375808B (en) | 1998-03-23 | 1999-12-01 | Taiwan Semiconductor Mfg Co Ltd | Process for fabricating copper metal interconnection |
US9236267B2 (en) | 2012-02-09 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cut-mask patterning process for fin-like field effect transistor (FinFET) device |
US20140011339A1 (en) | 2012-07-06 | 2014-01-09 | Applied Materials, Inc. | Method for removing native oxide and residue from a germanium or iii-v group containing surface |
US9105490B2 (en) | 2012-09-27 | 2015-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure of semiconductor device |
US9236300B2 (en) | 2012-11-30 | 2016-01-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact plugs in SRAM cells and the method of forming the same |
CN104183609B (en) | 2013-05-21 | 2017-08-01 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor devices and preparation method thereof |
US9136106B2 (en) | 2013-12-19 | 2015-09-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for integrated circuit patterning |
US9312354B2 (en) * | 2014-02-21 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact etch stop layers of a field effect transistor |
US9406804B2 (en) | 2014-04-11 | 2016-08-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFETs with contact-all-around |
US9443769B2 (en) | 2014-04-21 | 2016-09-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Wrap-around contact |
US9831183B2 (en) | 2014-08-07 | 2017-11-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact structure and method of forming |
US9368394B1 (en) * | 2015-03-31 | 2016-06-14 | Taiwan Semiconductor Manufacturing Company Ltd. | Dry etching gas and method of manufacturing semiconductor device |
US9520482B1 (en) | 2015-11-13 | 2016-12-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of cutting metal gate |
US10153199B2 (en) * | 2016-03-25 | 2018-12-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device and fabrication method therefor |
US9548366B1 (en) | 2016-04-04 | 2017-01-17 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self aligned contact scheme |
EP3920212A1 (en) * | 2016-12-30 | 2021-12-08 | INTEL Corporation | Contact architecture for capacitance reduction and satisfactory contact resistance |
US10269621B2 (en) * | 2017-04-18 | 2019-04-23 | Taiwan Semiconductor Manufacturing Company, Ltd. | Contact plugs and methods forming same |
US10763168B2 (en) * | 2017-11-17 | 2020-09-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with doped via plug and method for forming the same |
US10651292B2 (en) | 2018-02-19 | 2020-05-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dual metal via for contact resistance reduction |
US10475702B2 (en) * | 2018-03-14 | 2019-11-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Conductive feature formation and structure using bottom-up filling deposition |
US11086233B2 (en) | 2018-03-20 | 2021-08-10 | Lam Research Corporation | Protective coating for electrostatic chucks |
US11145751B2 (en) | 2018-03-29 | 2021-10-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Semiconductor structure with doped contact plug and method for forming the same |
US10886226B2 (en) * | 2018-07-31 | 2021-01-05 | Taiwan Semiconductor Manufacturing Co, Ltd. | Conductive contact having staircase barrier layers |
US11189694B2 (en) * | 2018-10-29 | 2021-11-30 | Mediatek Inc. | Semiconductor devices and methods of forming the same |
US11695051B2 (en) | 2019-03-29 | 2023-07-04 | Intel Corporation | Gate stacks for FinFET transistors |
US11410880B2 (en) | 2019-04-23 | 2022-08-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Phase control in contact formation |
US11939666B2 (en) * | 2020-06-01 | 2024-03-26 | Applied Materials, Inc. | Methods and apparatus for precleaning and treating wafer surfaces |
US20220254660A1 (en) * | 2021-02-05 | 2022-08-11 | Linco Technology Co., Ltd. | Substrate processing apparatus |
-
2021
- 2021-04-30 US US17/245,766 patent/US11855153B2/en active Active
- 2021-05-10 DE DE102021112091.8A patent/DE102021112091A1/en active Pending
- 2021-06-24 KR KR1020210082176A patent/KR20220127115A/en not_active Application Discontinuation
- 2021-06-28 TW TW110123645A patent/TWI825439B/en active
- 2021-08-11 CN CN202110920471.4A patent/CN115084017A/en active Pending
-
2023
- 2023-08-09 US US18/447,212 patent/US20230387222A1/en active Pending
Also Published As
Publication number | Publication date |
---|---|
TWI825439B (en) | 2023-12-11 |
TW202236386A (en) | 2022-09-16 |
CN115084017A (en) | 2022-09-20 |
US20220293741A1 (en) | 2022-09-15 |
KR20220127115A (en) | 2022-09-19 |
DE102021112091A1 (en) | 2022-09-15 |
US11855153B2 (en) | 2023-12-26 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US11508849B2 (en) | Semiconductor device and methods of manufacture | |
US20180144970A1 (en) | Semiconductor Device, Method, and Tool of Manufacture | |
US11600530B2 (en) | Semiconductor device and method of manufacture | |
US11670695B2 (en) | Semiconductor device and method of manufacture | |
US11973117B2 (en) | Semiconductor device | |
US11848240B2 (en) | Method of manufacturing a semiconductor device | |
US20230275153A1 (en) | Semiconductor Device and Method | |
US20230115597A1 (en) | Semiconductor device and manufacturing method thereof | |
US11855153B2 (en) | Semiconductor device and method | |
US20230197524A1 (en) | Semiconductor Device and Method of Manufacture | |
TW202025231A (en) | Method for forming semiconductor device and system for performing plasma cleaning process | |
US20240079265A1 (en) | Deposition Method for Semiconductor Device | |
US20230178361A1 (en) | Semiconductor Devices and Methods of Manufacture | |
US11901436B2 (en) | Formation of transistor gates |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |