US20230326936A1 - Display device - Google Patents

Display device Download PDF

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Publication number
US20230326936A1
US20230326936A1 US18/104,478 US202318104478A US2023326936A1 US 20230326936 A1 US20230326936 A1 US 20230326936A1 US 202318104478 A US202318104478 A US 202318104478A US 2023326936 A1 US2023326936 A1 US 2023326936A1
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Prior art keywords
electrode
metal layer
disposed
transistor
pixel
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US18/104,478
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English (en)
Inventor
Dong Hee Shin
No Kyung PARK
Sun Kwun Son
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Samsung Display Co Ltd
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Samsung Display Co Ltd
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Assigned to SAMSUNG DISPLAY CO., LTD. reassignment SAMSUNG DISPLAY CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PARK, NO KYUNG, SHIN, DONG HEE, SON, SUN KWUN
Publication of US20230326936A1 publication Critical patent/US20230326936A1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/075—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00
    • H01L25/0753—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L33/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits

Definitions

  • the disclosure relates to a display device.
  • display devices have been applied to various electronic devices such as smart phones, digital cameras, notebook computers, navigation systems, and smart televisions.
  • Examples of display devices include flat panel display devices such as a liquid crystal display (LCD) device, a field emission display (FED) device, or an organic light-emitting diode (OLED) display device.
  • the OLED display device in particular, includes light-emitting elements, which can allow pixels of a display panel to emit light, and can thus display an image without the aid of a backlight unit that provides light to the display panel.
  • the light-emitting elements may be OLEDs using an organic material as a fluorescent material and inorganic light-emitting diodes (LEDs) using an inorganic material as a fluorescent material.
  • aspects of the disclosure provide a display device capable of uniformly maintaining a capacitance of a first capacitor even when an error arises during the alignment of an active layer and a second metal layer.
  • a display device may include a first voltage line disposed in a first metal layer on a substrate and extending in a first direction, a first transistor including a source electrode disposed in an active layer on the first metal layer and a gate electrode disposed in a second metal layer on the active layer, the first transistor being electrically connected to the first voltage line, a first connection electrode disposed in the second metal layer and integrally formed with the gate electrode of the first transistor, a cover pattern disposed in the second metal layer and spaced apart from the first connection electrode in the first direction, and a first capacitor including a first capacitor electrode disposed in the active layer and electrically connected to the gate electrode of the first transistor, and a second capacitor electrode disposed in the first metal layer and electrically connected to the source electrode of the first transistor.
  • a first side of the cover pattern and a first side of the first connection electrode facing each other may overlap the first capacitor electrode in a plan view.
  • a first width of the cover pattern and a second width of the first connection electrode in a second direction may be equal.
  • the second direction may intersect the first direction.
  • a second side of the cover pattern adjacent to the first side of the cover pattern and a second side the first connection electrode adjacent to the first side of the first connection electrode may be colinear with each other.
  • the display device may further include a data line disposed in the first metal layer and extending in the first direction, and a second transistor including a source electrode and a drain electrode and electrically connecting the data line and the first capacitor electrode.
  • the source electrode of the second transistor and the first capacitor electrode may be integral with each other.
  • the display device may further include a second connection electrode disposed in the second metal layer and electrically connecting the data line and the drain electrode of the second transistor.
  • the display device may further include an initialization voltage line disposed in the first metal layer and extending in the first direction, and a third transistor including a source electrode and a drain electrode and electrically connecting the initialization voltage line and the source electrode of the first transistor.
  • the display device may further include a third connection electrode disposed in the second metal layer and electrically connecting the initialization voltage line and the source electrode of the third transistor.
  • the display device may further include a fourth connection electrode disposed in the second metal layer and electrically connecting the source electrode of the first transistor, the drain electrode of the third transistor, and the second capacitor electrode.
  • the display device may further include a fifth connection electrode disposed in the second metal layer, electrically connected to the second capacitor electrode, and integrally formed with the cover pattern.
  • the display device may further include a first electrode disposed in a third metal layer on the second metal layer, extending in the first direction, and electrically connected to the fifth connection electrode, and a second electrode disposed in the third metal layer and extending in parallel to the first electrode.
  • the display device may further include light-emitting elements arranged between the first electrode and the second electrode, a second voltage line disposed in the second metal layer and extending in a second direction intersecting the first direction, a first contact electrode disposed in a fourth metal layer on the third metal layer and electrically connecting the first electrode and the light-emitting elements, and a second contact electrode disposed in the fourth metal layer and electrically connecting the second voltage line and the light-emitting elements.
  • the cover pattern may be electrically floated.
  • the display device may further include a vertical gate line disposed in the first metal layer and extending in the first direction, a horizontal gate line disposed in the second metal layer and extending in a second direction intersecting the first direction, and an auxiliary gate line extending in the first direction from the horizontal gate line.
  • a display device may include a first metal layer disposed on a substrate, an active layer disposed on the first metal layer, a second metal layer disposed on the active layer, a first transistor including a source electrode disposed in the active layer and a gate electrode disposed in the second metal layer, a first connection electrode disposed in the second metal layer and integrally formed with the gate electrode of the first transistor, a cover pattern disposed in the second metal layer and spaced apart from the first connection electrode in a first direction, and a first capacitor including a first capacitor electrode disposed in the active layer and electrically connected to the gate electrode of the first transistor, and a second capacitor electrode disposed in the first metal layer and electrically connected to the source electrode of the first transistor.
  • a first width of the cover pattern and a second width of the first connection electrode in a second direction may be equal.
  • the second direction may intersect the first direction.
  • a first side of the cover pattern and a first side of the first connection electrode facing each other may overlap the first capacitor electrode in a plan view.
  • a second side of the cover pattern adjacent to the first side of the cover pattern and a second side of the first connection electrode adjacent to the first side of the first connection electrode may be colinear with each other.
  • the display device may further include a data line disposed in the first metal layer and extending in the first direction, and a second transistor electrically connecting the data line and the first capacitor electrode.
  • the display device may further include an initialization voltage line disposed in the first metal layer and extending in the first direction, and a third transistor electrically connecting the initialization voltage line and the source electrode of the first transistor.
  • the display device may further include a first electrode disposed in a third metal layer on the second metal layer and extending in the first direction, a second electrode disposed in the third metal layer and extending in parallel to the first electrode, and a plurality of light-emitting elements arranged in the first direction between the first electrode and the second electrode.
  • the capacitance of a first capacitor may be uniformly maintained even when error occurs during the alignment of the active layer and the second metal layer.
  • FIG. 1 is a plan view of a display device according to an embodiment of the disclosure
  • FIG. 2 is a plan view illustrating the contacts of vertical gate lines and horizontal gate lines of the display device of FIG. 1 ;
  • FIG. 3 illustrates pixels and lines of the display device of FIG. 1 ;
  • FIG. 4 is a schematic diagram of an equivalent circuit of a pixel of the display device of FIG. 1 ;
  • FIG. 5 is a plan view illustrating a part of a display area of the display device of FIG. 1 ;
  • FIG. 6 is a plan view illustrating a part of a display area of the display device of FIG. 1 ;
  • FIG. 7 is a schematic cross-sectional view taken along line I-I′ of FIGS. 5 and 6 ;
  • FIG. 8 is a schematic cross-sectional view taken along line II-II′ of FIGS. 5 and 6 ;
  • FIG. 9 is a plan view illustrating a layout of an active layer and a second metal layer in the display device of FIG. 1 ;
  • FIG. 10 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 ;
  • FIG. 11 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 ;
  • FIG. 12 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 ;
  • FIG. 13 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 ;
  • FIG. 14 is a plan view illustrating a layout of a first metal layer, the active layer, the second metal layer, and a third metal layer of the display device of FIG. 1 ;
  • FIG. 15 is a plan view illustrating a layout of the first metal layer, the active layer, the second metal layer, the third metal layer, and a fourth metal layer of the display device of FIG. 1 ;
  • FIG. 16 is a plan view illustrating a layout of the third metal layer, light-emitting elements, and the fourth metal layer in the display device of FIG. 1 ;
  • FIG. 17 is a schematic cross-sectional view taken along lines and IV-IV′ of FIGS. 15 and 16 .
  • the illustrated embodiments are to be understood as providing features of varying detail of some ways in which the disclosure may be implemented in practice. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and/or aspects, etc. (hereinafter individually or collectively referred to as “elements”), of the various embodiments may be otherwise combined, separated, interchanged, and/or rearranged without departing from the disclosure.
  • an element such as a layer
  • it may be directly on, connected to, or coupled to the other element or layer or intervening elements or layers may be present.
  • an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers present.
  • the term “connected” may refer to physical, electrical, and/or fluid connection, with or without intervening elements.
  • the element when an element is referred to as being “in contact” or “contacted” or the like to another element, the element may be in “electrical contact” or in “physical contact” with another element; or in “indirect contact” or in “direct contact” with another element.
  • the X-axis, the Y-axis, and the Z-axis are not limited to three axes of a rectangular coordinate system, and thus the X-, Y-, and Z-axes, and may be interpreted in a broader sense.
  • the X-axis, the Y-axis, and the Z-axis may be perpendicular to one another, or may represent different directions that are not perpendicular to one another.
  • “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be construed as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for instance, XYZ, XYY, YZ, and ZZ.
  • the term “and/or” includes any and all combinations of one or more of the associated listed items.
  • Spatially relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” “side” (e.g., as in “sidewall”), and the like, may be used herein for descriptive purposes, and, thereby, to describe one elements relationship to another element(s) as illustrated in the drawings.
  • Spatially relative terms are intended to encompass different orientations of an apparatus in use, operation, and/or manufacture in addition to the orientation depicted in the drawings. For example, if the apparatus in the drawings is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features.
  • the term “below” can encompass both an orientation of above and below.
  • the apparatus may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and, as such, the spatially relative descriptors used herein should be interpreted accordingly.
  • the terms “above”, “top”, and “top surface”, as used herein, refer to an upward direction from the display device 10 , i.e., a Z-axis direction
  • the terms “below”, “bottom”, and “bottom surface”, as used herein, refer to a downward direction from the display device 10 , i.e., the opposite direction of the Z-axis direction.
  • the terms “left”, “right”, “upper”, and “lower”, as used herein, refer to their respective directions as viewed from above the display device 10 .
  • the terms “left”, “right”, “upper”, and “lower” refer to the opposite direction of an X-axis direction, the X-axis direction, a Y-axis direction, and the opposite direction of the Y-axis direction, respectively.
  • each block, unit, part, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware to perform some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) to perform other functions.
  • each block, unit, part, and/or module of some embodiments may be physically separated into two or more interacting and discrete blocks, units, parts, and/or modules without departing from the scope of the disclosure.
  • the blocks, units, parts, and/or modules of some embodiments may be physically combined into more complex blocks, units, parts, and/or modules without departing from the scope of the disclosure.
  • FIG. 1 is a plan view of a display device according to an embodiment of the disclosure.
  • a display device 10 which is a device for displaying a moving or still image, may be used not only as the display screen of a portable electronic device such as a mobile phone, a smartphone, a tablet personal computer (PC), a smartwatch, a watchphone, a mobile communication terminal, an electronic notepad, an electronic book (e-book), a portable multimedia player (PMP), a navigation device, or a ultra-mobile PC (UMPC), but also as the display screen of various other products such as a television (TV), a laptop computer, a monitor, a billboard, or an Internet-of-Things (IoT) device.
  • a portable electronic device such as a mobile phone, a smartphone, a tablet personal computer (PC), a smartwatch, a watchphone, a mobile communication terminal, an electronic notepad, an electronic book (e-book), a portable multimedia player (PMP), a navigation device, or a ultra-mobile PC (UMPC)
  • TV television
  • laptop computer a monitor
  • billboard a bill
  • the display device 10 may include a display panel 100 , flexible films 210 , display drivers 220 , a circuit board 230 , a timing controller 240 , and a power supply part 250 .
  • the display panel 100 may have a rectangular shape in a plan view.
  • the display panel 100 may have a rectangular shape having long sides in a first direction (or the X-axis direction) and short sides in a second direction (or the Y-axis direction), in a plan view.
  • the corners where the long sides and the short sides of the display panel 100 meet may be right-angled or may be rounded to have a curvature.
  • the planar shape of the display panel 100 is not particularly limited, and the display panel 100 may have various other shapes such as a non-tetragonal polygonal shape, a circular shape, or an elliptical shape.
  • the display panel 100 may be formed to be flat, but the disclosure is not limited thereto. In another embodiment, the display panel 100 may be formed to be bent to have a curvature.
  • the display panel 100 may include a display area DA and a non-display area NDA.
  • the display area DA which is an area that displays an image, may be defined as a middle area of the display panel 100 .
  • the display area DA may include pixels SP, gate lines GL, data lines DL, initialization voltage lines VIL, first voltage lines VDL, horizontal voltage lines HVDL, vertical voltage lines VVSL, and second voltage lines VSL.
  • the pixels SP may be formed in pixel regions at the intersections between the data lines DL and the gate lines GL.
  • the pixels SP may include first pixels SP 1 , second pixels SP 2 , and third pixels SP 3 . Each of the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 may be connected to one gate line GL and one data line DL.
  • the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 may be defined as minimal areas for outputting light.
  • the first pixels SP 1 may emit first-color light or red light
  • the second pixels SP 2 may emit second-color light or green light
  • the third pixels SP 3 may emit third-color light or blue light.
  • the pixel circuits of the first pixels SP 1 , the pixel circuits of the third pixels SP 3 , and the pixel circuits of the second pixels SP 2 may be arranged along the opposite direction of the second direction (or the Y-axis direction), but the disclosure is not limited thereto.
  • the gate lines GL may include vertical gate lines VGL, horizontal gate lines HGL, and auxiliary gate lines BGL.
  • the vertical gate lines VGL may be connected to the display drivers 220 , may extend in the second direction (or the Y-axis direction), and may be spaced apart from one another in the first direction (or the X-axis direction).
  • the vertical gate lines VGL may be arranged in parallel to the data lines DL.
  • the horizontal gate lines HGL may extend in the first direction (or the X-axis direction) and may be spaced apart from one another in the second direction (or the Y-axis direction).
  • the horizontal gate lines HGL may intersect the vertical gate lines VGL.
  • the horizontal gate lines HGL may be connected to the vertical gate lines VGL through contacts MDC.
  • the contacts MDC may be parts of the horizontal gate lines HGL that are inserted in contact holes to be in contact with the vertical gate lines VGL.
  • the auxiliary gate lines BGL may extend from the horizontal gate lines HGL to provide gate signals to the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 .
  • the data lines DL may extend in the second direction (or the Y-axis direction) and may be spaced apart from one another in the first direction (or the X-axis direction).
  • the data lines DL may include first data lines DL 1 , second data lines DL 2 , and third data lines DL 3 .
  • the first data lines DL 1 , the second data lines DL 2 , and the third data lines DL 3 may provide data voltages to the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 , respectively.
  • the initialization voltage lines VIL may extend in the second direction (or the Y-axis direction) and may be spaced apart from one another in the first direction (or the X-axis direction).
  • the initialization voltage lines VIL may supply initialization voltages from the display drivers 220 to the pixel circuits of the first pixels SP 1 , the pixel circuits of the second pixels SP 2 , and the pixel circuits of the third pixels SP 3 .
  • the initialization voltage lines VIL may receive sensing signals from the pixel circuits of the first pixels SP 1 , the pixel circuits of the second pixels SP 2 , and the pixel circuits of the third pixels SP 3 and may provide the sensing signals to the display drivers 220 .
  • the first voltage lines VDL may extend in the second direction (or the Y-axis direction) and may be spaced apart from one another in the first direction (or the X-axis direction).
  • the first voltage lines VDL may provide driving voltages or high-potential voltages from the power supply part 250 to the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 .
  • the horizontal voltage lines HVDL may extend in the first direction (or the X-axis direction) and may be spaced apart from one another in the second direction (or the Y-axis direction).
  • the horizontal voltage lines HVDL may be connected to the first voltage lines VDL.
  • the horizontal voltage lines HVDL may receive the driving voltages or the high-potential voltages from the first voltage lines VDL.
  • the vertical voltage lines VVSL may extend in the second direction (or the Y-axis direction) and may be spaced apart from one another in the first direction (or the X-axis direction).
  • the vertical voltage lines VVSL may be connected to the second voltage lines VSL.
  • the vertical voltage lines VVSL may provide low-potential voltages from the power supply part 250 to the second voltage lines VSL.
  • the second voltage lines VSL may extend in the first direction (or the X-axis direction) and may be spaced apart from one another in the second direction (or the Y-axis direction).
  • the second voltage lines VSL may provide the low-potential voltages to the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 .
  • the pixels SP may vary how the pixels SP, the gate lines GL, the data lines DL, the initialization voltage lines VIL, the first voltage lines VDL, and the second voltage lines VSL are connected to one another.
  • the non-display area NDA may be defined as an area of the display panel 100 other than the display area DA.
  • the non-display area NDA may include fan-out lines, which connect the vertical gate lines VGL, the data lines DL, the initialization voltage lines VIL, the first voltage lines VDL, and the vertical voltage lines VVSL to the display drivers 220 , and pad units, which are connected to the flexible films 210 .
  • Input terminals provided at first sides of the flexible films 210 may be attached to the circuit board 230 by a film attachment process, and output terminals provided at second sides of the flexible films 210 may be attached to the pad units by a film attachment process.
  • the flexible films 210 like tape carrier packages or chip-on-films, may be bent.
  • the flexible films 210 may be bent toward the bottom of the display panel 100 to reduce the bezel area of the display device 10 .
  • the display drivers 220 may be mounted on the flexible films 210 .
  • the display drivers 220 may be implemented as integrated circuits (ICs).
  • the display drivers 220 may receive digital video data and data control signals from the timing controller 240 and may convert the digital video data into analog data voltages and provide the analog data voltages to the data lines DL through the fan-out lines in accordance with the data control signals.
  • the display drivers 220 may generate gate signals in accordance with gate control signals from the timing controller 240 and may sequentially provide the gate signals to the vertical gate lines VGL in a predefined order.
  • the display drivers 220 may perform the functions of a data driver and a gate driver at the same time.
  • the display device 10 includes the display drivers 220 , which are disposed in a lower part of the non-display area NDA, the size of left, right, and upper parts of the non-display area NDA can be minimized.
  • the circuit board 230 may support the timing controller 240 and the power supply part 250 and may provide signals and power to the display drivers 220 .
  • the circuit board 230 may provide signals from the timing controller 240 and power supply voltages from the power supply part 250 to the display drivers 220 to display an image.
  • signal lines and power lines may be provided on the circuit board 230 .
  • the timing controller 240 may be mounted on the circuit board 230 and may receive image data and timing synchronization signals from a display driving system or a graphics device through a user connector on the circuit board 230 .
  • the timing controller 240 may generate digital video data by aligning the image data in accordance with the timing synchronization signals to fit the layout of the pixels SP, and may provide the digital video data to the display drivers 220 .
  • the timing controller 240 may generate data control signals and gate control signals based on the timing synchronization signals.
  • the timing controller 240 may control the timing of providing data voltages from the display drivers 220 , based on the data control signals and may control the timing of providing gate signals from the display drivers 220 , based on the gate control signals.
  • the power supply part 250 may be disposed on the circuit board 230 and may provide power supply voltages to the display drivers 220 and the display panel 100 .
  • the power supply part 250 may generate driving voltages or high-potential voltages and provide the high-potential voltages to the first voltage lines VDL, may generate low-potential voltages and provide the low-potential voltages to the vertical voltage lines VVSL, and may generate initialization voltages and provide the initialization voltages to the initialization voltage lines VIL.
  • FIG. 2 is a plan view illustrating the contacts of the vertical gate lines and the horizontal gate lines of the display device of FIG. 1 .
  • the display area DA may include first, second, and third display areas DA 1 , DA 2 , and DA 3 .
  • the vertical gate lines HGL may intersect the vertical gate lines VGL.
  • the horizontal gate lines HGL may intersect the vertical gate lines VGL, at the contacts MDC and non-contacts NMC.
  • each of the horizontal gate lines HGL may be connected to one of the vertical gate lines VGL through one of the contacts MDC and may be insulated from the rest of the vertical gate lines VGL at non-contacts NMC.
  • Contacts MDC in the first display area DA 1 may be disposed along an extension line from an upper left part of the first display area DA 1 to a lower right part of the first display area DA 1 .
  • Contacts MDC in the second display area DA 2 may be disposed along an extension line from an upper left part of the second display area DA 2 to a lower right part of the second display area DA 2 .
  • Contacts MDC in the third display area DA 3 may be disposed along an extension line from an upper left part of the third display area DA 3 to a lower right part of the third display area DA 3 .
  • the contacts MDC may be arranged along a diagonal line between the first direction (or the X-axis direction) and the opposite direction of the second direction (or the Y-axis direction), in each of the first, second, and third display areas DA 1 , DA 2 , and DA 3 .
  • the display device 10 may include the display drivers 220 , which perform the functions of a data driver and a gate driver.
  • the display drivers 220 which perform the functions of a data driver and a gate driver.
  • the data lines DL and the vertical gate lines VGL receive data voltages and gate signals, respectively, from the display drivers 220 , which are disposed in the lower part of the non-display area NDA, the size of the left, right, and upper parts of the non-display area NDA can be minimized.
  • FIG. 3 illustrates the pixels and lines of the display device of FIG. 1 .
  • the pixels SP may include the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 .
  • the pixel circuits of the first pixels SP 1 , the pixel circuits of the third pixels SP 3 , and the pixel circuits of the second pixels SP 2 may be arranged along the opposite direction of the second direction (or the Y-axis direction), but the disclosure is not limited thereto.
  • the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 may be connected to the first voltage lines VDL, the initialization voltage lines VIL, and the data lines DL.
  • the first voltage lines VDL may extend in the second direction (or the Y-axis direction).
  • the first voltage lines VDL may be disposed on the left sides of the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 .
  • the first voltage lines VDL may provide driving voltages or high-potential voltages to transistors of each of the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 .
  • the horizontal voltage lines HVDL may extend in the first direction (or the X-axis direction).
  • the horizontal voltage lines HVDL may be disposed on the upper sides of the horizontal gate lines HGL.
  • the horizontal voltage lines HVDL may be connected to the first voltage lines VDL.
  • the horizontal voltage lines HVDL may receive the driving voltages or the high-potential voltages from the first voltage lines VDL.
  • the initialization voltage lines VIL may extend in the second direction (or the Y-axis direction).
  • the initialization voltage lines VIL may be disposed on the right sides of the auxiliary gate lines BGL.
  • the initialization voltage lines VIL may be disposed between the auxiliary gate lines BGL and the data lines DL.
  • the initialization voltage lines VIL may provide initialization voltages to the pixel circuits of the first pixels SP 1 , the pixel circuits of the second pixels SP 2 , and the pixel circuits of the third pixels SP 3 .
  • the initialization voltage lines VIL may receive sensing signals from the pixel circuits of the first pixels SP 1 , the pixel circuits of the second pixels SP 2 , and the pixel circuits of the third pixels SP 3 and provide the sensing signals to the display drivers 220 .
  • the gate lines GL may include the vertical gate lines VGL, the horizontal gate lines HGL, and the auxiliary gate lines BGL.
  • the vertical gate lines VGL may extend in the second direction (or the Y-axis direction).
  • the vertical gate lines VGL may be connected between the display drivers 220 and the horizontal gate lines HGL.
  • the vertical gate lines VGL may intersect the horizontal gate lines HGL.
  • the vertical gate lines VGL may provide the gate signals from the display drivers 220 to the horizontal gate lines HGL.
  • an (n ⁇ 3)-th vertical gate line VGLn ⁇ 3 (where n is a positive integer) and an (n ⁇ 2)-th vertical gate line VGLn ⁇ 2 may be disposed on the left side of a j-th column COLj (where j is a positive integer) of pixels SP.
  • the vertical gate lines VGLn ⁇ 3 and VGLn ⁇ 2 may be disposed in parallel on the left sides of the first voltage lines VDL.
  • An (n ⁇ 1)-th vertical gate line VGLn ⁇ 1 and an n-th vertical gate line VGLn may be disposed between a data line DL connected to the j-th column COLj of pixels SP and a first voltage line VDL connected to a (j+1)-th column COLj+1 of pixels SP.
  • the (n ⁇ 1)-th vertical gate line VGLn ⁇ 1 may be connected to an (n ⁇ 1)-th horizontal gate line HGLn ⁇ 1 through a contact MDC and may be insulated from other horizontal gate lines HGL.
  • the n-th vertical gate line VGLn may be connected to an n-th horizontal gate line HGLn through a contact MDC and may be insulated from other horizontal gate lines HGL.
  • the (n ⁇ 1)-th and n-th vertical gate lines VGLn ⁇ 1 and VGLn may be disposed on the left side of the first voltage line VDL connected to the (j+1)-th column COLj+1 of pixels SP.
  • the horizontal gate lines HGL may extend in the first direction (or the X-axis direction).
  • the horizontal gate lines HGL may be disposed on the upper sides of the first pixels SP 1 .
  • the horizontal gate lines HGL may be connected between the vertical gate lines VGL and the auxiliary gate lines BGL.
  • the horizontal gate lines BGL may provide the gate signals from the vertical gate lines VGL to the auxiliary gate lines BGL.
  • the (n ⁇ 1)-th horizontal gate line HGLn ⁇ 1 may be disposed on the upper side of a k-th row ROWk (where k is a positive integer) of first pixels SP 1 .
  • the (n ⁇ 1)-th horizontal gate line HGLn ⁇ 1 may be connected to the (n ⁇ 1)-th vertical gate line VGLn ⁇ 1 through a contact MDC and may be insulated from other vertical gate lines VGL.
  • the n-th horizontal gate line HGLn may be disposed on the upper side of a (k+1)-th row ROWk+1 of first pixels SP 1 .
  • the n-th horizontal gate line HGLn may be connected to the n-th vertical gate line VGLn through a contact MDC and may be insulated from other vertical gate lines VGL.
  • the auxiliary gate lines BGL may extend in the opposite direction of the second direction (or the Y-axis direction) from the horizontal gate lines HGL.
  • the auxiliary gate lines BGL may be disposed on the right sides of the first pixels SP 1 , the second pixels SP 2 , and the third pixels SP 3 .
  • the auxiliary gate lines BGL may provide gate signals from the horizontal gate lines HGL to the pixel circuits of the first pixels SP 1 , the pixel circuits of the second pixels SP 2 , and the pixel circuits of the third pixels SP 3 .
  • the data lines DL may extend in the second direction (or the Y-axis direction).
  • the data lines DL may provide data voltages to the pixels SP.
  • the data lines DL may include first data lines DL 1 , second data lines DL 2 , and third data lines DL 3 .
  • the first data lines DL 1 may extend in the second direction (or the Y-axis direction).
  • the first data lines DL 1 may be disposed on the right sides of the initialization voltage lines VIL.
  • the first data lines DL 1 may provide the data voltages from the display drivers 220 to the pixel circuits of the first pixels SP 1 .
  • the second data lines DL 2 may extend in the second direction (or the Y-axis direction).
  • the second data lines DL 2 may be disposed on the right sides of the initialization voltage lines VIL.
  • the second data lines DL 2 may provide the data voltages from the display drivers 220 to the pixel circuits of the second pixels SP 2 .
  • the third data lines DL 3 may extend in the second direction (or the Y-axis direction).
  • the third data lines DL 3 may be disposed on the right sides of the initialization voltage lines VIL.
  • the third data lines DL 3 may provide the data voltages from the display drivers 220 to the pixel circuits of the third pixels SP 3 .
  • the vertical voltage lines VVSL may extend in the second direction (or the Y-axis direction).
  • the vertical voltage lines VVSL may be disposed on the right sides of the third data lines DL 3 .
  • the vertical voltage lines VVSL may be connected between the power supply part 250 and the second voltage lines VSL.
  • the vertical voltage lines VVSL may provide low-potential voltages from the power supply part 250 to the second voltage lines VSL.
  • the second voltage lines VSL may extend in the first direction (or the X-axis direction).
  • the second voltage lines VSL may be disposed on the lower sides of the second pixels SP 2 .
  • the second voltage lines VSL may provide the low-potential voltages from the vertical voltage lines VVSL to light-emitting element layers of the first pixels SP 1 , light-emitting element layers of the second pixels SP 2 , and light-emitting element layers of the third pixels SP 3 .
  • FIG. 4 is a schematic diagram of and equivalent circuit of a pixel of the display device of FIG. 1 .
  • a pixel SP may be connected to a first voltage line VDL, a data line DL, an initialization voltage line VIL, a gate line GL, and a second voltage line VSL.
  • the pixel SP may include first, second, and third transistors ST 1 , ST 2 , and ST 3 , a first capacitor C 1 , and multiple light-emitting elements ED.
  • the first transistor ST 1 may include a gate electrode, a drain electrode, and a source electrode.
  • the gate electrode of the first transistor ST 1 may be connected to a first node N 1
  • the drain electrode of the first transistor ST 1 may be connected to the first voltage line VDL
  • the source electrode of the first transistor ST 1 may be connected to a second node N 2 .
  • the first transistor ST 1 may control a drain-source current (or a driving current) based on a data voltage applied to its gate electrode.
  • the light-emitting elements ED may include first, second, third, and fourth light-emitting elements ED 1 , ED 2 , ED 3 , and ED 4 .
  • the first, second, third, and fourth light-emitting elements ED 1 , ED 2 , ED 3 , and ED 4 may be connected in series.
  • the first, second, third, and fourth light-emitting elements ED 1 , ED 2 , ED 3 , and ED 4 may receive the driving current and may emit light.
  • the amount of light emitted by the light-emitting elements ED or the luminance of the light-emitting elements ED may be proportional to the magnitude of the diving current.
  • the light-emitting elements ED may be inorganic light-emitting elements including an inorganic semiconductor, but the disclosure is not limited thereto.
  • a first electrode of the first light-emitting element ED 1 may be connected to the second node N 2 , and a second electrode of the first light-emitting element ED 1 may be connected to a third node N 3 .
  • the first electrode of the first light-emitting element ED 1 may be connected to the source electrode of the first transistor ST 1 , a drain electrode of the third transistor ST 3 , and a second capacitor electrode of the first capacitor C 1 through the second node N 2 .
  • the second electrode of the first light-emitting element ED 1 may be connected to a first electrode of the second light-emitting element ED 2 through the third node N 3 .
  • the first electrode of the second light-emitting element ED 2 may be connected to the third node N 3 , and a second electrode of the second light-emitting element ED 2 may be connected to a fourth node N 4 .
  • a first electrode of the third light-emitting element ED 3 may be connected to the fourth node N 4
  • a second electrode of the third light-emitting element ED 3 may be connected to a fifth node N 5 .
  • a first electrode of the fourth light-emitting element ED 4 may be connected to the fifth node N 5
  • a second electrode of the fourth light-emitting element ED 4 may be connected to the second voltage line VSL.
  • the second transistor ST 2 may be turned on by a gate signal from the gate line GL to electrically connect the data line DL and the first node N 1 , which is connected to the gate electrode of the first transistor ST 1 .
  • the second transistor ST 2 may be turned on by the gate signal from the gate line GL to provide a data voltage to the first node N 1 .
  • a gate electrode of the second transistor ST 2 may be connected to the gate line GL, a drain electrode of the second transistor ST 2 may be connected to the data line DL, and a source electrode of the second transistor ST 2 may be connected to the first node N 1 .
  • the source electrode of the second transistor ST 2 may be connected to the gate electrode of the first transistor ST 1 and a first capacitor electrode of the first capacitor C 1 through the first node N 1 .
  • the third transistor ST 3 may be turned on by the gate signal from the gate line GL to electrically connect the initialization voltage line VIL and the second node N 2 , which is connected to the source electrode of the first transistor ST 1 .
  • the third transistor ST 3 may be turned on by the gate signal from the gate line GL to provide an initialization voltage to the second node N 2 .
  • the third transistor ST 3 may be turned on by the gate signal from the gate line GL to provide a sensing signal to the initialization voltage line VIL.
  • a gate electrode of the third transistor ST 3 may be connected to the gate line GL, a drain electrode of the third transistor ST 3 may be connected to the second node N 2 , and a source electrode of the third transistor ST 3 may be connected to the initialization voltage line VIL.
  • the drain electrode of the third transistor ST 3 may be connected to the source electrode of the first transistor ST 1 and the first electrode of the first light-emitting element ED 1 through the second node N 2 .
  • the drain electrode of the third transistor ST 3 may be connected to the second capacitor electrode of the first capacitor C 1 .
  • FIGS. 5 and 6 are plan views illustrating parts of the display area of the display device of FIG. 1 .
  • FIG. 7 is a schematic cross-sectional view taken along line I-I′ of FIGS. 5 and 6
  • FIG. 8 is a schematic cross-sectional view taken along line II-IF of FIGS. 5 and 6 .
  • the display area DA may include pixels SP, a first voltage line VDL, a horizontal voltage line HVDL, an initialization voltage line VIL, the (n ⁇ 1)-th vertical gate line VGLn ⁇ 1, the n-th vertical gate line VGLn, the n-th horizontal gate line HGLn, an auxiliary gate line BGL, data lines DL, a vertical voltage line VVSL, and a second voltage line VSL.
  • the pixels SP may include first, second, and third pixels SP 1 , SP 2 , and SP 3 .
  • the pixel circuits of the first, third, and second pixels SP 1 , SP 3 , and SP 2 may be arranged along the opposite direction of the second direction (or the Y-axis direction).
  • the pixel circuits of the first, second, and third pixels SP 1 , SP 2 , and SP 3 may be disposed in a pixel region.
  • the first voltage line VDL may be disposed in a first metal layer MTL 1 on a substrate SUB.
  • the first voltage line VDL may be disposed on the left sides of the pixel circuits of the first, second, and third pixels SP 1 , SP 2 , and SP 3 .
  • the first voltage line VDL may overlap a fifteenth connection electrode CE 15 of a second metal layer MTL 2 in a thickness direction (or the Z-axis direction).
  • the first voltage line VDL may be connected to the fifteenth connection electrode CE 15 through a fifteenth contact hole CNT 15 .
  • the first voltage line VDL may be connected to a drain electrode DE 1 of a first transistor ST 1 of the first pixel SP 1 through a first contact hole CNT 1 .
  • the fifteenth connection electrode CE 15 may be connected to a drain electrode DE 1 of a first transistor ST 1 of the second pixel SP 2 through a sixth contact hole CNT 6 .
  • the fifteenth connection electrode CE 15 may be connected to a drain electrode DE 1 of a first transistor ST 1 of the third pixel SP 3 through an eleventh contact hole CNT 11 .
  • the first voltage line VDL may provide driving voltages or high-potential voltages to the first, second, and third pixels SP 1 , SP 2 , and SP 3 through the fifteenth connection electrode CE 15 .
  • the horizontal voltage line HVDL may be disposed in the second metal layer MTL 2 .
  • the second metal layer MTL 2 may be disposed on a gate insulating film GI, which covers an active layer ACTL.
  • the horizontal voltage line HVDL may be disposed on the upper side of the n-th horizontal gate line HGLn.
  • the horizontal voltage line HVDL may be connected to the first voltage line VDL through a twenty-sixth contact hole CNT 26 to receive a driving voltage or a high-potential voltage.
  • the horizontal voltage line HVDL may provide a driving voltage or a high-potential voltage to alignment electrodes of a third metal layer.
  • the initialization voltage line VIL may be disposed in the first metal layer MTL 1 .
  • the initialization voltage line VIL may be disposed on the right side of the auxiliary gate line BGL.
  • a third connection electrode CE 3 of the second metal layer MTL 2 may electrically connect the initialization voltage line VIL to a source electrode SE 3 of a third transistor ST 3 of the first pixel SP 1 through a fifth contact hole CNT 5 .
  • An eighth connection electrode CE 8 of the second metal layer MTL 2 may electrically connect the initialization voltage line VIL to a source electrode SE 3 of a third transistor ST 3 of the second pixel SP 2 through a tenth contact hole CNT 10 .
  • the eighth connection electrode CE 8 may electrically connect the initialization voltage line VIL to a source electrode SE 3 of a third transistor ST 3 of the third pixel SP 3 through the tenth contact hole CNT 10 .
  • the source electrode SE 3 of the third transistor ST 3 of the second pixel SP 2 and the source electrode SE 3 of the third transistor ST 3 of the third pixel SP 3 may be integral with each other, but the disclosure is not limited thereto.
  • the initialization voltage line VIL may provide an initialization voltage to the third transistors ST 3 of the first, second, and third pixels SP 1 , SP 2 , and SP 3 and may receive sensing signals from the third transistors ST 3 of the first, second, and third pixels SP 1 , SP 2 , and SP 3 .
  • Multiple vertical gate lines VGL may be disposed in the first metal layer MTL 1 .
  • the (n ⁇ 1)-th and n-th vertical gate lines VGLn ⁇ 1 and VGLn may be disposed on the left side of the first voltage line VDL.
  • the (n ⁇ 1)-th vertical gate line VGLn ⁇ 1 may overlap an auxiliary electrode AUE of the second metal layer MTL 2 in the thickness direction (or the Z-axis direction) and may be connected to the auxiliary electrode AUE through multiple twenty-eighth contact holes CNT 28 .
  • line resistance can be reduced.
  • the n-th vertical gate line VGLn may be connected to the n-th horizontal gate line HGLn through a contact MDC.
  • the n-th vertical gate line VGLn may provide a gate signal to the n-th horizontal gate line HGLn.
  • the n-th vertical gate line VGLn may overlap an auxiliary electrode AUE of the second metal layer MTL 2 in the thickness direction (or the Z-axis direction) and may be connected to the auxiliary electrode AUE through multiple twenty-ninth contact holes CNT 29 .
  • line resistance can be reduced.
  • the n-th horizontal gate line HGLn may be disposed in the second metal layer MTL 2 .
  • the n-th horizontal gate line HGLn may be disposed on the upper side of the pixel circuit of the first pixel SP 1 .
  • the n-th horizontal gate line HGLn may be connected to the n-th vertical gate line VGLn, which is disposed in the first metal layer MTL 1 , through a contact MDC.
  • the n-th horizontal gate line HGLn may provide the gate signal from the n-th vertical gate line VGLn to the auxiliary gate line BGL.
  • the auxiliary gate line BGL may be disposed in the second metal layer MTL 2 .
  • the auxiliary gate line BGL may protrude in the opposite direction of the second direction (or the Y-axis direction) from the n-th horizontal gate line HGLn.
  • the auxiliary gate line BGL and the n-th horizontal gate line HGLn may be integral with each other, but the disclosure is not limited thereto.
  • the auxiliary gate line BGL may be disposed on the right sides of the pixel circuits of the first, second, and third pixels SP 1 , SP 2 , and SP 3 .
  • the auxiliary gate line BGL may provide the gate signal from the n-th horizontal gate line HGLn to the second and third transistors ST 2 and ST 3 of each of the first, second, and third pixels SP 1 , SP 2 , and SP 3 .
  • the first data line DL 1 may be disposed in the first metal layer MTL 1 .
  • the first data line DL 1 may be disposed on the right side of the initialization voltage line VIL.
  • a second connection electrode CE 2 of the second metal layer MTL 2 may electrically connect the first data line DL 1 to a drain electrode DE 2 of the second transistor ST 2 of the first pixel SP 1 through a fourth contact hole CNT 4 .
  • the first data line DL 1 may provide a data voltage to the second transistor ST 2 of the first pixel SP 1 .
  • the second data line DL 2 may be disposed in the first metal layer MTL 1 .
  • the second data line DL 2 may be disposed on the right side of the first data line DL 1 .
  • a seventh connection electrode CE 7 of the second metal layer MTL 2 may electrically connect the second data line DL 2 to a drain electrode DE 2 of the second transistor ST 2 of the second pixel SP 2 through a ninth contact hole CNT 9 .
  • the second data line DL 2 may provide a data voltage to the second transistor ST 2 of the second pixel SP 2 .
  • the third data line DL 3 may be disposed in the first metal layer MTL 1 .
  • the third data line DL 3 may be disposed on the right side of the second data line DL 2 .
  • a twelfth connection electrode CE 12 of the second metal layer MTL 2 may electrically connect the third data line DL 3 to a drain electrode DE 2 of the second transistor ST 2 of the third pixel SP 3 through a fourteenth contact hole CNT 14 .
  • the third data line DL 3 may provide a data voltage to the second transistor ST 2 of the third pixel SP 3 .
  • the vertical voltage line VVSL may be disposed in the first metal layer MTL 1 .
  • the vertical voltage line VVSL may be disposed on the right side of the third data line DL 3 .
  • the vertical voltage line VVSL may be connected to the second voltage line VSL of the second metal layer MTL 2 through a twenty-seventh contact hole CNT 27 .
  • the vertical voltage line VVSL may provide a low-potential voltage to the second voltage line VSL.
  • the vertical voltage line VVSL may overlap an auxiliary electrode AUE of the second metal layer MTL 2 in the thickness direction (or the Z-axis direction) and may be connected to the auxiliary electrode AUE through multiple thirtieth contact holes CNT 30 . As the vertical voltage line VVSL is connected to the auxiliary electrode AUE, line resistance can be reduced.
  • the second voltage line VSL may be disposed in the second metal layer MTL 2 .
  • the second voltage line VSL may be disposed on the lower side of the pixel circuit of the second pixel SP 2 .
  • the second voltage line VSL may provide the low-potential voltage from the vertical voltage line VVSL to second electrodes of the first, second, and third pixels SP 1 , SP 2 , and SP 3 .
  • the second voltage line VSL may be connected to the second electrode (RME 2 in FIG. 16 ) of the third pixel SP 3 through a twenty-third contact hole CNT 23 , may be connected to the second electrode (RME 2 in FIG.
  • the second electrodes of the first, second, and third pixels SP 1 , SP 2 , and SP 3 may be disposed in the third metal layer, and the twenty-third, twenty-fourth, and twenty-fifth contact holes CNT 23 , CNT 24 , and CNT 25 may be formed through a via layer VIA and a passivation layer PV.
  • the passivation layer PV may be disposed on the second metal layer MTL 2 and the gate insulating film GI, and the via layer VIA may be disposed on the passivation layer PV.
  • the pixel circuit of the first pixel SP 1 may include first, second, and third transistors ST 1 , ST 2 , and ST 3 .
  • the first transistor ST 1 of the first pixel SP 1 may include an active region ACT 1 , a gate electrode GE 1 , a drain electrode DE 1 , and a source electrode SE 1 .
  • the active region ACT 1 of the first transistor ST 1 may be disposed in the active layer ACTL and may overlap the gate electrode GE 1 of the first transistor ST 1 in the thickness direction (or the Z-axis direction).
  • the active layer ACTL may be disposed on a buffer layer BF, which covers the first metal layer MTL 1 .
  • the gate electrode GE 1 of the first transistor ST 1 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 1 of the first transistor ST 1 and a first connection electrode CE 1 may be integral with each other.
  • the first connection electrode CE 1 may be connected to a first capacitor electrode CPE 1 of a first capacitor C 1 , which is disposed in the active layer ACTL, through a third contact hole CNT 3 .
  • the first capacitor electrode CPE 1 of the first capacitor C 1 may be formed as a conductor by thermally treating the active layer ACTL.
  • the first capacitor electrode CPE 1 of the first capacitor C 1 and a source electrode SE 2 of the second transistor ST 2 may be integral with each other, but the disclosure is not limited thereto.
  • the drain and source electrodes DE 1 and SE 1 of the first transistor ST 1 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain and source electrodes DE 1 and SE 1 of the first transistor ST 1 may be formed as N-type semiconductors, but the disclosure is not limited thereto.
  • the fifteenth connection electrode CE 15 may be connected to the drain electrode DE 1 of the first transistor ST 1 of the first pixel SP 1 through the first contact hole CNT 1 .
  • the fifteenth connection electrode CE 15 may electrically connect the first voltage line VDL to the drain electrode DE 1 of the first transistor ST 1 .
  • the drain electrode DE 1 of the first transistor ST 1 may receive a driving voltage or a high-potential voltage from the first voltage line VDL.
  • a fourth connection electrode CE 4 of the second metal layer MTL 2 may electrically connect the source electrode SE 1 of the first transistor ST 1 , a drain electrode DE 3 of the third transistor ST 3 , and a second capacitor electrode CPE 2 of the first metal layer MTL 1 of the first pixel SP 1 through a second contact hole CNT 2 .
  • the first capacitor C 1 may be formed between a first capacitor electrode CPE 1 of the active layer ACTL and the second capacitor electrode CPE 2 of the first metal layer MTL 1 .
  • a fifth connection electrode CE 5 of the second metal layer MTL 2 may be connected to the second capacitor electrode CPE 2 through a sixteenth contact hole CNT 16 .
  • the fifth connection electrode CE 5 may be connected to a first electrode (RME 1 in FIG. 16 ) of the first pixel SP 1 through a seventeenth contact hole CNT 17 .
  • the first electrode of the first pixel SP 1 may be disposed in a third electrode layer, and the seventeenth contact hole CNT 17 may be formed through the via layer VIA and the passivation layer PV.
  • a cover pattern CPT of the second metal layer MTL 2 may be disposed on the upper side of the first connection electrode CE 1 .
  • the cover pattern CPT may be spaced apart from the first connection electrode CE 1 in the second direction (or the Y-axis direction).
  • the cover pattern CPT may be spaced apart from the first connection electrode CE 1 by a predetermined (or selectable) distance. Sides of the cover pattern CPT and the first connection electrode CE 1 that are facing each other may overlap the first capacitor electrode CPE 1 in the third direction (or the Z-axis direction).
  • the cover pattern CPT of the first pixel SP 1 and the fifth connection electrode CE 5 may be integral with each other, but the disclosure is not limited thereto.
  • the width of the cover pattern CPT may be substantially the same as the width of the first connection electrode CE 1 .
  • the left sides of the cover pattern CPT and the first connection electrode CE 1 may fall on the same line extending in the second direction (or the Y-axis direction), for example, the left sides of the cover pattern CPT and the first connection electrode CE 1 may be colinear with each other, but the disclosure is not limited thereto.
  • the right sides of the cover pattern CPT and the first connection electrode CE 1 may fall on the same line extending in the second direction (or the Y-axis direction), for example, the right sides of the cover pattern CPT and the first connection electrode CE 1 may be colinear with each other, but the disclosure is not limited thereto.
  • the left side of the first capacitor electrode CPE 1 may be disposed in line with the left side of the cover pattern CPT. Accordingly, even if the cover pattern CPT is aligned on the left side of a reference origin, the lower side of the cover pattern CPT and the upper side of the first connection electrode CE 1 may overlap the first capacitor electrode CPE 1 .
  • the second transistor ST 2 of the first pixel SP 1 may include an active region ACT 2 , a gate electrode GE 2 , a drain electrode DE 2 , and a source electrode SE 2 .
  • the active region ACT 2 of the second transistor ST 2 may be disposed in the active layer ACTL and may overlap the gate electrode GE 2 of the second transistor ST 2 in the thickness direction (or the Z-axis direction).
  • the gate electrode GE 2 of the second transistor ST 2 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 2 of the second transistor ST 2 may be a part of the auxiliary gate line BGL.
  • the drain and source electrodes DE 2 and SE 2 of the second transistor ST 2 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain electrode DE 2 of the second transistor ST 2 may be electrically connected to the first data line DL 1 through the second connection electrode CE 2 .
  • the drain electrode DE 2 of the second transistor ST 2 may receive a data voltage for the first pixel SP 1 from the first data line DL 1 .
  • the source electrode SE 2 of the second transistor ST 2 and the first capacitor electrode CPE 1 of the first capacitor C 1 may be integral with each other.
  • the source electrode SE 2 of the second transistor ST 2 may be electrically connected to the gate electrode GE 1 of the first transistor ST 1 through the first capacitor electrode CPE 1 and the first connection electrode CE 1 .
  • the third transistor ST 3 of the first pixel SP 1 may include an active region ACT 3 , a gate electrode GE 3 , a drain electrode DE 3 , and a source electrode SE 3 .
  • the active region ACT 3 of the third transistor ST 3 may be disposed in the active layer ACTL and may overlap the gate electrode GE 3 of the third transistor ST 3 in the thickness direction (or the Z-axis direction).
  • the gate electrode GE 3 of the third transistor ST 3 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 3 of the third transistor ST 3 may be a part of the auxiliary gate line BGL.
  • the drain and source electrodes DE 3 and SE 3 of the third transistor ST 3 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain electrode DE 3 of the third transistor ST 3 may be electrically connected to the source electrode SE 1 of the first transistor ST 1 and the second capacitor electrode CPE 2 through the fourth connection electrode CE 4 .
  • the source electrode SE 3 of the third transistor ST 3 may be connected to the third connection electrode CE 3 of the second metal layer MTL 2 through the fifth contact hole CNT 5 .
  • the third connection electrode CE 3 may electrically connect the source electrode SE 3 of the third transistor ST 3 to the initialization voltage line VIL.
  • the source electrode SE 3 of the third transistor ST 3 may receive an initialization voltage from the initialization voltage line VIL.
  • the source electrode SE 3 of the third transistor ST 3 may provide a sensing signal to the initialization voltage line VIL.
  • the pixel circuit of the second pixel SP 2 may include first, second, and third transistors ST 1 , ST 2 , and ST 3 .
  • the first transistor ST 1 of the second pixel SP 2 may include an active region ACT 1 , a gate electrode GE 1 , a drain electrode DE 1 , and a source electrode SE 1 .
  • the active region ACT 1 of the first transistor ST 1 may be disposed in the active layer ACTL and may overlap the gate electrode GE 1 of the first transistor ST 1 in the thickness direction (or the Z-axis direction).
  • the gate electrode GE 1 of the first transistor ST 1 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 1 of the first transistor ST 1 and a sixth connection electrode CE 6 may be integral with each other.
  • the sixth connection electrode CE 6 may be connected to a first capacitor electrode CPE 1 of a first capacitor C 1 , which is disposed in the active layer ACTL, through an eighth contact hole CNT 8 .
  • the first capacitor electrode CPE 1 of the first capacitor electrode CPE 1 may be formed as a conductor by thermally treating the active layer ACTL.
  • the first capacitor electrode CPE 1 of the first capacitor C 1 and a source electrode SE 2 of the second transistor ST 2 may be integral with each other, but the disclosure is not limited thereto.
  • the drain and source electrodes DE 1 and SE 1 of the first transistor ST 1 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain and source electrodes DE 1 and SE 1 of the first transistor ST 1 may be formed as N-type semiconductors, but the disclosure is not limited thereto.
  • the fifteenth connection electrode CE 15 may be connected to the drain electrode DE 1 of the first transistor ST 1 through the sixth contact hole CNT 6 .
  • the fifteenth connection electrode CE 15 may electrically connect the first voltage line VDL to the drain electrode DE 1 of the first transistor ST 1 .
  • the drain electrode DE 1 of the first transistor ST 1 may receive a driving voltage or a high-potential voltage from the first voltage line VDL.
  • a ninth connection electrode CE 9 of the second metal layer MTL 2 may electrically connect the source electrode SE 1 of the first transistor ST 1 , a drain electrode DE 3 of the third transistor ST 3 , and a second capacitor electrode CPE 2 of the first metal layer MTL 1 through a seventh contact hole CNT 7 .
  • the first capacitor C 1 may be formed between a first capacitor electrode CPE 1 of the active layer ACTL and the second capacitor electrode CPE 2 of the first metal layer MTL 1 .
  • a tenth connection electrode CE 10 of the second metal layer MTL 2 may be connected to the second capacitor electrode CPE 2 through an eighteenth contact hole CNT 18 .
  • the tenth connection electrode CE 10 may be connected to a first electrode (RME 1 in FIG. 16 ) of the second pixel SP 2 through a nineteenth contact hole CNT 19 .
  • the first electrode of the second pixel SP 2 may be disposed in the third electrode layer, and the nineteenth contact hole CNT 19 may be formed through the via layer VIA and the passivation layer PV.
  • a cover pattern CPT of the second metal layer MTL 2 may be disposed on the lower side of the sixth connection electrode CE 6 .
  • the cover pattern CPT may be spaced apart from the sixth connection electrode CE 6 in the opposite direction of the second direction (or the Y-axis direction).
  • the distance between the cover pattern CPT and the sixth connection electrode CE 6 may be substantially the same as the distance between the cover pattern CPT of the first pixel SP 1 and the first connection electrode CE 1 , but the disclosure is not limited thereto.
  • Sides of the cover pattern CPT and the sixth connection electrode CE 6 that are facing each other may overlap the first capacitor electrode CPE 1 in the third direction (or the Z-axis direction).
  • the cover pattern CPT may be electrically floated from the fifteenth connection electrode CE 15 , but the disclosure is not limited thereto.
  • the cover pattern CPT and the fifteenth connection electrode CE 15 may be integral with each other, in which case, a part connecting the cover pattern CPT and the fifteenth connection electrode CE 15 may not overlap the first capacitor electrode CPE 1 .
  • the width of the cover pattern CPT may be substantially the same as the width of the sixth connection electrode CE 6 .
  • the left sides of the cover pattern CPT and the sixth connection electrode CE 6 may fall on the same line extending in the second direction (or the Y-axis direction), for example, the left sides of the cover pattern CPT and the sixth connection electrode CE 6 may be colinear with each other, but the disclosure is not limited thereto.
  • the right sides of the cover pattern CPT and the sixth connection electrode CE 6 may fall on the same line extending in the second direction (or the Y-axis direction), for example, the right sides of the cover pattern CPT and the sixth connection electrode CE 6 may be colinear with each other, but the disclosure is not limited thereto.
  • the left side of the first capacitor electrode CPE 1 may be disposed in line with the left side of the cover pattern CPT. Accordingly, even if the cover pattern CPT is aligned on the left side of a reference origin, the upper side of the cover pattern CPT and the lower side of the sixth connection electrode CE 6 may overlap the first capacitor electrode CPE 1 .
  • the second transistor ST 2 of the second pixel SP 2 may include an active region ACT 2 , a gate electrode GE 2 , a drain electrode DE 2 , and a source electrode SE 2 .
  • the active region ACT 2 of the second transistor ST 2 may be disposed in the active layer ACTL and may overlap the gate electrode GE 2 of the second transistor ST 2 in the thickness direction (or the Z-axis direction).
  • the gate electrode GE 2 of the second transistor ST 2 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 2 of the second transistor ST 2 may be a part of the auxiliary gate line BGL.
  • the drain and source electrodes DE 2 and SE 2 of the second transistor ST 2 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain electrode DE 2 of the second transistor ST 2 may be electrically connected to the second data line DL 2 through a seventh connection electrode CE 7 .
  • the drain electrode DE 2 of the second transistor ST 2 may receive a data voltage for the second pixel SP 2 from the second data line DL 2 .
  • the source electrode SE 2 of the second transistor ST 2 and the first capacitor electrode CPE 1 of the first capacitor C 1 may be integral with each other.
  • the source electrode SE 2 of the second transistor ST 2 may be electrically connected to the gate electrode GE 1 of the first transistor ST 1 through the first capacitor electrode CPE 1 and the sixth connection electrode CE 6 .
  • the third transistor ST 3 of the second pixel SP 2 may include an active region ACT 3 , a gate electrode GE 3 , a drain electrode DE 3 , and a source electrode SE 3 .
  • the active region ACT 3 of the third transistor ST 3 may be disposed in the active layer ACTL and may overlap the gate electrode GE 3 of the third transistor ST 3 in the thickness direction (or the Z-axis direction).
  • the gate electrode GE 3 of the third transistor ST 3 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 3 of the third transistor ST 3 may be a part of the auxiliary gate line BGL.
  • the drain and source electrodes DE 3 and SE 3 of the third transistor ST 3 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain electrode DE 3 of the third transistor ST 3 may be electrically connected to the source electrode SE 1 of the first transistor ST 1 and the second capacitor electrode CPE 2 through the ninth connection electrode CE 9 .
  • the source electrode SE 3 of the third transistor ST 3 may be connected to the eighth connection electrode CE 8 of the second metal layer MTL 2 through the tenth contact hole CNT 10 .
  • the eighth connection electrode CE 8 may electrically connect the source electrode SE 3 of the third transistor ST 3 to the initialization voltage line VIL.
  • the source electrode SE 3 of the third transistor ST 3 may receive an initialization voltage from the initialization voltage line VIL.
  • the source electrode SE 3 of the third transistor ST 3 may provide a sensing signal to the initialization voltage line VIL.
  • the pixel circuit of the third pixel SP 3 may include first, second, and third transistors ST 1 , ST 2 , and ST 3 .
  • the first transistor ST 1 of the third pixel SP 3 may include an active region ACT 1 , a gate electrode GE 1 , a drain electrode DE 1 , and a source electrode SE 1 .
  • the active region ACT 1 of the first transistor ST 1 may be disposed in the active layer ACTL and may overlap the gate electrode GE 1 of the first transistor ST 1 in the thickness direction (or the Z-axis direction).
  • the gate electrode GE 1 of the first transistor ST 1 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 1 of the first transistor ST 1 and an eleventh connection electrode CE 11 may be integral with each other.
  • the eleventh connection electrode CE 11 may be connected to a first capacitor electrode CPE 1 of a first capacitor C 1 , which is disposed in the active layer ACTL, through a thirteenth contact hole CNT 13 .
  • the first capacitor electrode CPE 1 of the first capacitor C 1 may be formed as a conductor by thermally treating the active layer ACTL.
  • the first capacitor electrode CPE 1 of the first capacitor C 1 and a source electrode SE 2 of the second transistor ST 2 may be integral with each other, but the disclosure is not limited thereto.
  • the drain and source electrodes DE 1 and SE 1 of the first transistor ST 1 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain and source electrodes DE 1 and SE 1 of the first transistor ST 1 may be formed as N-type semiconductors, but the disclosure is not limited thereto.
  • the fifteenth connection electrode CE 15 may be connected to the drain electrode DE 1 of the first transistor ST 1 through the eleventh contact hole CNT 11 .
  • the fifteenth connection electrode CE 15 may electrically connect the first voltage line VDL to the drain electrode DE 1 of the first transistor ST 1 .
  • the drain electrode DE 1 of the first transistor ST 1 may receive a driving voltage or a high-potential voltage from the first voltage line VDL.
  • a thirteenth connection electrode CE 13 of the second metal layer MTL 2 may electrically connect the source electrode SE 1 of the first transistor ST 1 , a drain electrode DE 3 of the third transistor ST 3 , and a second capacitor electrode CPE 2 of the first metal layer MTL 1 through a twelfth contact hole CNT 12 .
  • the first capacitor C 1 may be formed between a first capacitor electrode CPE 1 of the active layer ACTL and the second capacitor electrode CPE 2 of the first metal layer MTL 1 .
  • a fourteenth connection electrode CE 14 of the second metal layer MTL 2 may be connected to the second capacitor electrode CPE 2 through a twentieth contact hole CNT 20 .
  • the fourteenth connection electrode CE 14 may be connected to a first electrode (RME 1 in FIG. 16 ) of the third pixel SP 3 through a twenty-first contact hole CNT 21 .
  • the first electrode of the third pixel SP 3 may be disposed in the third electrode layer, and the twenty-first contact hole CNT 21 may be formed through the via layer VIA and the passivation layer PV.
  • a cover pattern CPT of the second metal layer MTL 2 may be disposed on the upper side of the eleventh connection electrode CE 11 .
  • the cover pattern CPT may be spaced apart from the eleventh connection electrode CE 11 in the second direction (or the Y-axis direction).
  • the distance between the cover pattern CPT and the eleventh connection electrode CE 11 may be substantially the same as the distance between the cover pattern CPT of the second pixel SP 2 and the sixth connection electrode CE 6 , but the disclosure is not limited thereto.
  • Sides of the cover pattern CPT and the eleventh connection electrode CE 11 that are facing each other may overlap the first capacitor electrode CPE 1 in the third direction (or the Z-axis direction).
  • the cover pattern CPT may be electrically floated from the fifteenth connection electrode CE 15 , but the disclosure is not limited thereto.
  • the cover pattern CPT and the fifteenth connection electrode CE 15 may be integral with each other, in which case, a part connecting the cover pattern CPT and the fifteenth connection electrode CE 15 may not overlap the first capacitor electrode CPE 1 .
  • the width of the cover pattern CPT may be substantially the same as the width of the eleventh connection electrode CE 11 .
  • the left sides of the cover pattern CPT and the eleventh connection electrode CE 11 may fall on the same line extending in the second direction (or the Y-axis direction), for example, the left sides of the cover pattern CPT and the eleventh connection electrode CE 11 may be colinear with each other, but the disclosure is not limited thereto.
  • the right sides of the cover pattern CPT and the eleventh connection electrode CE 11 may fall on the same line extending in the second direction (or the Y-axis direction), for example, the right sides of the cover pattern CPT and the eleventh connection electrode CE 11 may be colinear with each other, but the disclosure is not limited thereto.
  • the left side of the first capacitor electrode CPE 1 may be disposed in line with the left side of the cover pattern CPT. Accordingly, even if the cover pattern CPT is aligned on the left side of a reference origin, the lower side of the cover pattern CPT and the upper side of the eleventh connection electrode CE 11 may overlap the first capacitor electrode CPE 1 .
  • the second transistor ST 2 of the third pixel SP 3 may include an active region ACT 2 , a gate electrode GE 2 , a drain electrode DE 2 , and a source electrode SE 2 .
  • the active region ACT 2 of the second transistor ST 2 may be disposed in the active layer ACTL and may overlap the gate electrode GE 2 of the second transistor ST 2 in the thickness direction (or the Z-axis direction).
  • the gate electrode GE 2 of the second transistor ST 2 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 2 of the second transistor ST 2 may be a part of the auxiliary gate line BGL.
  • the drain and source electrodes DE 2 and SE 2 of the second transistor ST 2 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain electrode DE 2 of the second transistor ST 2 may be electrically connected to the third data line DL 3 through the twelfth connection electrode CE 12 .
  • the drain electrode DE 2 of the second transistor ST 2 may receive a data voltage for the third pixel SP 3 from the third data line DL 3 .
  • the source electrode SE 2 of the second transistor ST 2 and the first capacitor electrode CPE 1 of the first capacitor C 1 may be integral with each other.
  • the source electrode SE 2 of the second transistor ST 2 may be electrically connected to the gate electrode GE 1 of the first transistor ST 1 through the first capacitor electrode CPE 1 and the eleventh connection electrode CE 11 .
  • the third transistor ST 3 of the third pixel SP 3 may include an active region ACT 3 , a gate electrode GE 3 , a drain electrode DE 3 , and a source electrode SE 3 .
  • the active region ACT 3 of the third transistor ST 3 may be disposed in the active layer ACTL and may overlap the gate electrode GE 3 of the third transistor ST 3 in the thickness direction (or the Z-axis direction).
  • the gate electrode GE 3 of the third transistor ST 3 may be disposed in the second metal layer MTL 2 .
  • the gate electrode GE 3 of the third transistor ST 3 may be a part of the auxiliary gate line BGL.
  • the drain and source electrodes DE 3 and SE 3 of the third transistor ST 3 may be formed as conductors by thermally treating the active layer ACTL.
  • the drain electrode DE 3 of the third transistor ST 3 may be electrically connected to the source electrode SE 1 of the first transistor ST 1 and the second capacitor electrode CPE 2 through the thirteenth connection electrode CE 13 .
  • the source electrode SE 3 of the third transistor ST 3 may be connected to the eighth connection electrode CE 8 of the second metal layer MTL 2 through the tenth contact hole CNT 10 .
  • the eighth connection electrode CE 8 may electrically connect the source electrode SE 3 of the third transistor ST 3 to the initialization voltage line VIL.
  • the source electrode SE 3 of the third transistor ST 3 may receive an initialization voltage from the initialization voltage line VIL.
  • the source electrode SE 3 of the third transistor ST 3 may provide a sensing signal to the initialization voltage line VIL.
  • FIG. 9 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 .
  • FIG. 9 is an enlarged plan view illustrating a part of the pixel circuit of the third pixel SP 3 of FIG. 5 . Descriptions of features or elements that have already been described above will be omitted or simplified.
  • a center CPT_C of the cover pattern CPT of the third pixel SP 3 may substantially coincide with a reference origin O.
  • the reference origin O may be located at the intersection between X- and Y-axes passing through the cover pattern CPT.
  • the reference origin O of FIG. 9 may coincide with reference origins O of FIGS. 10 through 13 .
  • the second metal layer MTL 2 may be disposed on the active layer ACTL by aligning the center CPT-C of the cover pattern CPT with the reference origin O.
  • the cover pattern CPT of the third pixel SP 3 may be disposed on the upper side of the eleventh connection electrode CE 11 .
  • the cover pattern CPT may be spaced apart from the eleventh connection electrode CE 11 in the second direction (or the Y-axis direction).
  • the cover pattern CPT and the eleventh connection electrode CE 11 may be symmetrical with respect to the Y axis, but the disclosure is not limited thereto.
  • the distance between the cover pattern CPT and the eleventh connection electrode CE 11 may be substantially the same as the distance between the cover pattern CPT of the second pixel SP 2 and the sixth connection electrode CE 6 , but the disclosure is not limited thereto.
  • the cover pattern CPT may be electrically floated, but the disclosure is not limited thereto.
  • the cover pattern CPT and the fifteenth connection electrode CE 15 may be integral with each other, in which case, a part connecting the cover pattern CPT and the fifteenth connection electrode CE 15 may not overlap the first capacitor electrode CPE 1 .
  • a first width W 1 of the cover pattern CPT may be substantially the same as a second width W 2 of the eleventh connection electrode CE 11 .
  • the left sides of the cover pattern CPT and the eleventh connection electrode CE 11 may fall on a same line extending in the second direction (or the Y-axis direction), for example, the left sides of the cover pattern CPR and the eleventh connection electrode CE 11 may be colinear with each other, but the disclosure is not limited thereto.
  • the right sides of the cover pattern CPT and the eleventh connection electrode CE 11 may fall on the same line extending in the second direction (or the Y-axis direction), for example the right sides of the cover pattern CPT and the eleventh connection electrode CE 11 may be colinear with each other, but the disclosure is not limited thereto.
  • the left side of the first capacitor electrode CPE 1 may be disposed in line with the left side of the cover pattern CPT.
  • the lower side of the cover pattern CPCT may overlap the first capacitor electrode CPE 1 .
  • FIG. 10 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 .
  • the center CPT_C of the cover pattern CPT of the third pixel SP 3 may be disposed on the left side of the reference origin O.
  • the second metal layer MTL 2 may be disposed on the left side of the active layer ACTL due to error. Even if error occurs during the alignment of the second metal layer MTL 2 , the left side of the cover pattern CPT may not be disposed beyond the left side of the first capacitor electrode CPE 1 .
  • the overlapping area of the first capacitor electrode CPE 1 with the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 10 may be substantially the same as the overlapping area of the first capacitor electrode CPE 1 with the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 9 .
  • a part of the first capacitor electrode CPE 1 not overlapping the second metal layer MTL 2 may be formed as a conductor with an N-type semiconductor.
  • the size of the conductor part of the first capacitor electrode CPE 1 may determine the capacitance of the first capacitor C 1 .
  • the capacitance of the first capacitor C 1 of FIG. 10 may be substantially the same as the capacitance of the first capacitor C 1 of FIG. 9 .
  • the cover pattern CPT which is distanced apart from the eleventh connection electrode CE 11 and has the same width as the eleventh connection electrode CE 11 , is provided, the capacitance of the first capacitor C 1 can be uniformly maintained even if error occurs during the alignment of the second metal layer MTL 2 .
  • FIG. 11 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 .
  • the center CPT_C of the cover pattern CPT of the third pixel SP 3 may be disposed on the right side of the reference origin O.
  • the second metal layer MTL 2 may be disposed on the right side of the active layer ACTL due to error.
  • the overlapping area of the first capacitor electrode CPE 1 with the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 11 may be substantially the same as the overlapping area of the first capacitor electrode CPE 1 with the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 9 .
  • a part of the first capacitor electrode CPE 1 not overlapping the second metal layer MTL 2 may be formed as a conductor with an N-type semiconductor.
  • the size of the conductor part of the first capacitor electrode CPE 1 may determine the capacitance of the first capacitor C 1 .
  • the capacitance of the first capacitor C 1 of FIG. 11 may be substantially the same as the capacitance of the first capacitor C 1 of FIG. 9 .
  • the cover pattern CPT which is distanced apart from the eleventh connection electrode CE 11 and has the same width as the eleventh connection electrode CE 11 , is provided, the capacitance of the first capacitor C 1 can be uniformly maintained even if error occurs during the alignment of the second metal layer MTL 2 .
  • FIG. 12 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 .
  • the center CPT_C of the cover pattern CPT of the third pixel SP 3 may be disposed on the upper side of the reference origin O.
  • the second metal layer MTL 2 may be disposed on the upper side of the active layer ACTL due to error.
  • the overlapping area of the eleventh connection electrode CE 11 and the first capacitor CPE 1 of FIG. 12 may be increased from the overlapping area of the eleventh connection electrode CE 11 and the first capacitor CPE 1 of FIG. 9 by an amount of which the overlapping area between the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 12 is reduced from the overlapping area between the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 9 .
  • the overlapping area of the first capacitor electrode CPE 1 with the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 12 may be substantially the same as the overlapping area of the first capacitor electrode CPE 1 with the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 9 .
  • a part of the first capacitor electrode CPE 1 not overlapping the second metal layer MTL 2 may be formed as a conductor with an N-type semiconductor.
  • the size of the conductor part of the first capacitor electrode CPE 1 may determine the capacitance of the first capacitor C 1 .
  • the capacitance of the first capacitor C 1 of FIG. 12 may be substantially the same as the capacitance of the first capacitor C 1 of FIG. 9 .
  • the capacitance of the first capacitor C 1 can be uniformly maintained even if error occurs during the alignment of the second metal layer MTL 2 .
  • FIG. 13 is a plan view illustrating a layout of the active layer and the second metal layer in the display device of FIG. 1 .
  • the center CPT_C of the cover pattern CPT of the third pixel SP 3 may be disposed on the lower side of the reference origin O.
  • the second metal layer MTL 2 may be disposed on the lower side of the active layer ACTL due to error.
  • the overlapping area of the eleventh connection electrode CE 11 and the first capacitor CPE 1 of FIG. 13 may be increased from the overlapping area of the eleventh connection electrode CE 11 and the first capacitor CPE 1 of FIG. 9 by an amount of which the overlapping area of the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 13 is reduced from the overlapping area of the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 9 .
  • the overlapping area of the first capacitor electrode CPE 1 with the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 13 may be substantially the same as the overlapping area of the first capacitor electrode CPE 1 with the cover pattern CPT and the eleventh connection electrode CE 11 of FIG. 9 .
  • a part of the first capacitor electrode CPE 1 not overlapping the second metal layer MTL 2 may be formed as a conductor with an N-type semiconductor.
  • the size of the conductor part of the first capacitor electrode CPE 1 may determine the capacitance of the first capacitor C 1 .
  • the capacitance of the first capacitor C 1 of FIG. 13 may be substantially the same as the capacitance of the first capacitor C 1 of FIG. 9 .
  • the capacitance of the first capacitor C 1 can be uniformly maintained even if error occurs during the alignment of the second metal layer MTL 2 .
  • FIG. 14 is a plan view illustrating a layout of a first metal layer, an active layer, a second metal layer, and a third metal layer of the display device of FIG. 1
  • FIG. 15 is a plan view illustrating a layout of the first metal layer, the active layer, the second metal layer, the third metal layer, and a fourth metal layer of the display device of FIG. 1
  • FIG. 14 include the third metal layer in addition to FIGS. 5 and 6
  • FIG. 15 includes the fourth metal layer in addition to FIG. 14
  • FIG. 16 is a plan view illustrating a layout of the third metal layer, light-emitting elements, and the fourth metal layer in the display device of FIG. 1
  • FIG. 17 is a schematic cross-sectional view taken along lines and IV-IV′ of FIGS. 15 and 16 .
  • a light-emitting element layer EML may be disposed on a thin-film transistor (TFT) layer TFTL.
  • the light-emitting element layer EML may include bank patterns BP, first electrodes RME 1 , second electrodes RME 2 , first light-emitting elements ED 1 , second light-emitting elements ED 2 , third light-emitting elements ED 3 , fourth light-emitting elements ED 4 , a first insulating film PAS 1 , a second insulating film PAS 2 , first contact electrodes CTE 1 , second contact electrodes CTE 2 , third contact electrodes CTE 3 , fourth contact electrodes CTE 4 , fifth contact electrodes CTE 5 , and a third insulating film PAS 3 .
  • the bank pattern BP may protrude from the via layer in an upward direction (or the Z-axis direction). Each of the bank patterns BP may have inclined sides.
  • the first light-emitting elements ED 1 , the second light-emitting elements ED 2 , the third light-emitting elements ED 3 , and the fourth light-emitting elements ED 4 may be disposed between the bank patterns BP.
  • Multiple bank patterns BP may be disposed in the entire display area DA as island patterns.
  • First and second electrodes RME 1 and RME 2 of each of first, second, and third pixels SP 1 , SP 2 , and SP 3 may be disposed in a third metal layer MTL 3 .
  • the third metal layer MTL 3 may be disposed on the via layer VIA and the bank patterns BP.
  • the first and second electrodes RME 1 and RME 2 of each of the first, second, and third pixels SP 1 , SP 2 , and SP 3 may extend in the second direction (or the Y-axis direction).
  • the first electrode RME 1 of the first pixel SP 1 may be disposed between the second electrode RME 2 of the first pixel SP 1 and the second electrode RME 2 of the second pixel SP 2 .
  • the first electrode RME 1 of the second pixel SP 2 may be disposed between the second electrode RME 2 of the second pixel SP 2 and the second pixel RME 2 of the third pixel SP 3 .
  • the first electrode RME 1 of the third pixel SP 3 may be disposed between the second electrode RME 2 of the third pixel SP 2 and a second electrode RME 2 of another first pixel SP 1 .
  • the first electrodes RME 1 and the second electrodes RME 2 may cover the top surface and the inclined sides of each of the bank patterns BP. Accordingly, the first electrodes RME 1 and the second electrodes RME 2 may reflect light emitted by the first light-emitting elements ED 1 , the second light-emitting elements ED 2 , the third light-emitting elements ED 3 , and the fourth light-emitting elements ED 4 , to an upward direction (or the Z-axis direction).
  • the first electrodes RME 1 may be separated in units of rows.
  • the first electrodes RME 1 and the second electrodes RME 2 may be alignment electrodes for aligning the first light-emitting elements ED 1 , the second light-emitting elements ED 2 , the third light-emitting elements ED 3 , and the fourth light-emitting elements ED 4 during the fabrication of the display device 10 .
  • the first electrodes RME 1 may initially be integrally formed with alignment electrodes ALE before separated from the alignment electrodes ALE, and the alignment electrodes ALE may be connected to a horizontal voltage line HVDL of the second metal layer MTL 2 through twenty-second contact holes CNT 22 .
  • the alignment electrodes ALE may receive a driving voltage or a high-potential voltage from the horizontal voltage line HVDL and may provide the driving voltage or the high-potential voltage to the first electrodes RME 1 .
  • the first electrodes RME 1 may be separated from the alignment electrodes ALE after the alignment of the light-emitting elements ED.
  • the first electrode RME 1 of the first pixel SP 1 may be connected to a fifth connection electrode CE 5 of the second metal layer MTL 2 through a seventeenth contact hole CNT 17 .
  • the first electrode RME 1 of the first pixel SP 1 may receive a driving current through a first transistor ST 1 .
  • the first electrode RME 1 of the first pixel SP 1 may provide the driving current to the first light-emitting elements ED 1 of the first pixel SP 1 through a first contact electrode CTE 1 .
  • the second electrode RME 2 of the first pixel SP 1 may be connected to a second voltage line VSL of the second metal layer MTL 2 through a twenty-fourth contact hole CNT 24 . Accordingly, the second electrode RME 2 of the first pixel SP 1 may receive a low-potential voltage from the second voltage line VSL.
  • the first electrode RME 1 of the second pixel SP 2 may be connected to a tenth connection electrode CE 10 of the second metal layer MTL 2 through a nineteenth contact hole CNT 19 .
  • the first electrode RME 1 of the second pixel SP 2 may receive a driving current through a first transistor ST 1 .
  • the first electrode RME 1 of the second pixel SP 2 may provide the driving current to the first light-emitting elements ED 1 of the second pixel SP 2 through a first contact electrode CTE 1 .
  • the second electrode RME 2 of the second pixel SP 2 may be connected to a second voltage line VSL of the second metal layer MTL 2 through a twenty-fifth contact hole CNT 25 . Accordingly, the second electrode RME 2 of the second pixel SP 2 may receive a low-potential voltage from the second voltage line VSL. The second electrode RME 2 of the second pixel SP 2 may overlap the pixel circuits of the first, second, and third pixels SP 1 , SP 2 , and SP 3 .
  • the second electrode RME 2 of the second pixel SP 2 covers first capacitor electrodes CPE 1 of the first, second, and third pixels SP 1 , SP 2 , and SP 3 , any variations that may be caused by coupling capacitors of the first capacitor electrodes CPE 1 can be minimized, and horizontal crosstalk can be prevented.
  • the first electrode RME 1 of the third pixel SP 3 may be connected to a fourteenth connection electrode CE 14 of the second metal layer MTL 2 through a twenty-first contact hole CNT 21 .
  • the first electrode RME 1 of the third pixel SP 3 may receive a driving current through a first transistor ST 1 .
  • the first electrode RME 1 of the third pixel SP 3 may provide the driving current to the first light-emitting elements ED 1 of the third pixel SP 3 through a first contact electrode CTE 1 .
  • the second electrode RME 2 of the third pixel SP 3 may be connected to a second voltage line VSL of the second metal layer MTL 2 through a twenty-third contact hole CNT 23 . Accordingly, the second electrode RME 2 of the third pixel SP 3 may receive a low-potential voltage from the second voltage line VSL.
  • the first light-emitting elements ED 1 , the second light-emitting elements ED 2 , the third light-emitting elements ED 3 , and the fourth light-emitting elements ED 4 may be aligned between the first electrodes RME 1 and the second electrodes RME 2 .
  • the first insulating film PAS 1 may cover the first electrodes RME 1 and the second electrodes RME 2 .
  • the first light-emitting elements ED 1 , the second light-emitting elements ED 2 , the third light-emitting elements ED 3 , and the fourth light-emitting elements ED 4 may be insulated from the first electrodes RME 1 and the second electrodes RME 2 by the first insulating film PAS 1 .
  • the first electrodes RME 1 and the second electrodes RME 2 may receive alignment signals, and electric fields may be formed between the first electrodes RME 1 and the second electrodes RME 2 .
  • the first light-emitting elements ED 1 , the second light-emitting elements ED 2 , the third light-emitting elements ED 3 , and the fourth light-emitting elements ED 4 may be sprayed onto the first electrodes RME 1 and the second electrodes RME 2 by inkjet printing and may be aligned by dielectrophoretic forces from the electric fields between the first electrodes RME 1 and the second electrodes RME 2 .
  • the first light-emitting elements ED 1 , the second light-emitting elements ED 2 , the third light-emitting elements ED 3 , and the fourth light-emitting elements ED 4 may be aligned between the first electrodes RME 1 and the second electrodes RME 2 along the second direction (or the Y-axis direction).
  • First, second, third, fourth, and fifth contact electrodes CTE 1 , CTE 2 , CTE 3 , CTE 4 , and CTE 5 of each of the first, second, and third pixels SP 1 , SP 2 , and SP 3 may be disposed in a fourth metal layer MTL 4 .
  • the second insulating film PAS 2 may be disposed on the middle parts of the light-emitting elements ED.
  • the third insulating film PAS 3 may cover the first and second insulating films PAS 1 and PAS 2 and the first, second, third, fourth, and fifth contact electrodes CTE 1 , CTE 2 , CTE 3 , CTE 4 , and CTE 5 of each of the first, second, and third pixels SP 1 , SP 2 , and SP 3 .
  • the second and third insulating films PAS 2 and PAS 3 may insulate the first, second, third, fourth, and fifth contact electrodes CTE 1 , CTE 2 , CTE 3 , CTE 4 , and CTE 5 of each of the first, second, and third pixels SP 1 , SP 2 , and SP 3 from one another.
  • the first contact electrode CTE 1 of the first pixel SP 1 may be disposed on the second electrode RME 2 of the first pixel SP 1 and may be connected to the first electrode RME 1 of the first pixel SP 1 through a contact hole overlapping the seventeenth contact hole CNT 17 .
  • the first contact electrode CTE 1 of the first pixel SP 1 may be connected between the first electrode RME 1 and first ends of the first light-emitting elements ED 1 of the first pixel SP 1 .
  • the first contact electrode CTE 1 of the first pixel SP 1 may correspond to the anodes of the first light-emitting elements ED 1 of the first pixel SP 1 , but the disclosure is not limited thereto.
  • the second contact electrode CTE 2 of the first pixel SP 1 may be insulated from the first and second electrodes RME 1 and RME 2 of the first pixel SP 1 .
  • a first part of the second contact electrode CTE 2 of the first pixel SP 1 may be disposed on the first electrode RME 1 of the first pixel SP 1 and may extend in the second direction (or the Y-axis direction).
  • a second part of the second contact electrode CTE 2 of the first pixel SP 1 may be disposed on the second electrode RME 2 of the third pixel SP 3 and may extend in the second direction (or the Y-axis direction).
  • the second part of the second contact electrode CTE 2 of the first pixel SP 1 may extend from the lower side of the first part of the second contact electrode CTE 2 of the first pixel SP 1 .
  • the second contact electrode CTE 2 of the first pixel SP 1 may be connected between second ends of the first light-emitting elements ED 1 of the first pixel SP 1 and first ends of the second light-emitting elements ED 2 of the first pixel SP 1 .
  • the second contact electrode CTE 2 of the first pixel SP 1 may correspond to the third node N 3 of FIG. 4 .
  • the second contact electrode CTE 2 of the first pixel SP 1 may correspond to the cathodes of the first light-emitting elements ED 1 of the first pixel SP 1 , but the disclosure is not limited thereto.
  • the second contact electrode CTE 2 of the first pixel SP 1 may correspond to the anodes of the second light-emitting elements ED 2 of the first pixel SP 1 , but the disclosure is not limited thereto.
  • the third contact electrode CTE 3 of the first pixel SP 1 may be insulated from the first and second electrodes RME 1 and RME 2 of the first pixel SP 1 .
  • a first part of the third contact electrode CTE 3 of the first pixel SP 1 may be disposed on the first electrode RME 1 of the first pixel SP 1 and may extend in the second direction (or the Y-axis direction).
  • a second part of the third contact electrode CTE 3 of the first pixel SP 1 may be disposed on the first electrode RME 1 of the first pixel SP 1 , on the right side of the first part of the third contact electrode CTE 3 of the first pixel SP 1 .
  • the third contact electrode CTE 3 of the first pixel SP 1 may be connected between second ends of the second light-emitting elements ED 2 of the first pixel SP 1 and first ends of the third light-emitting elements ED 3 of the first pixel SP 1 .
  • the third contact electrode CTE 3 of the first pixel SP 1 may correspond to the fourth node N 4 of FIG. 4 .
  • the third contact electrode CTE 3 of the first pixel SP 1 may correspond to the cathodes of the second light-emitting elements ED 2 of the first pixel SP 1 , but the disclosure is not limited thereto.
  • the third contact electrode CTE 3 of the first pixel SP 1 may correspond to the anodes of the third light-emitting elements ED 3 of the first pixel SP 1 , but the disclosure is not limited thereto.
  • the fourth contact electrode CTE 4 of the first pixel SP 1 may be insulated from the first and second electrodes RME 1 and RME 2 of the first pixel SP 1 .
  • a first part of the fourth contact electrode CTE 4 of the first pixel SP 1 may be disposed on the second electrode RME 2 of the first pixel SP 1 and may extend in the second direction (or the Y-axis direction).
  • a second part of the fourth contact electrode CTE 4 of the first pixel SP 1 may be disposed on the first electrode RME 1 of the first pixel SP 1 and may extend in the second direction (or the Y-axis direction).
  • the second part of the fourth contact electrode CTE 4 of the first pixel SP 1 may extend from the upper side of the first part of the fourth contact electrode CTE 4 of the first pixel SP 1 .
  • the fourth contact electrode CTE 4 of the first pixel SP 1 may be connected between second ends of the third light-emitting elements ED 3 of the first pixel SP 1 and first ends of the fourth light-emitting elements ED 4 of the first pixel SP 1 .
  • the fourth contact electrode CTE 4 of the first pixel SP 1 may correspond to the fifth node N 5 of FIG. 4 .
  • the fourth contact electrode CTE 4 of the first pixel SP 1 may correspond to the cathodes of the third light-emitting elements ED 3 of the first pixel SP 1 , but the disclosure is not limited thereto.
  • the fourth contact electrode CTE 4 of the first pixel SP 1 may correspond to the anodes of the fourth light-emitting elements ED 4 of the first pixel SP 1 , but the disclosure is not limited thereto.
  • the fifth contact electrode CTE 5 of the first pixel SP 1 may be insulated from the first and second electrodes RME 1 and RME 2 of the first pixel SP 1 .
  • a first part of the fifth contact electrode CTE 5 of the first pixel SP 1 may be disposed on the second electrode RME 2 of the first pixel SP 1 and may extend in the second direction (or the Y-axis direction).
  • a second part of the fifth contact electrode CTE 5 of the first pixel SP 1 may extend from the first part of the fifth contact electrode CTE 5 of the first pixel SP 1 over to the twenty-fourth contact hole CNT 24 .
  • the second part of the fifth contact electrode CTE 5 of the first pixel SP 1 may extend from the lower side of the first part of the fifth contact electrode CTE 5 of the first pixel SP 1 .
  • the fifth contact electrode CTE 5 of the first pixel SP 1 may be connected between second ends of the fourth light-emitting elements ED 4 of the first pixel SP 1 and the second electrode RME 2 of the first pixel SP 1 .
  • the fifth contact electrode CTE 5 of the first pixel SP 1 may correspond to the cathodes of the fourth light-emitting elements ED 4 of the first pixel SP 1 , but the disclosure is not limited thereto.
  • the fifth contact electrode CTE 5 of the first pixel SP 1 may receive a low-potential voltage from the second electrode RME 2 of the first pixel SP 1 .

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US18/104,478 2022-04-06 2023-02-01 Display device Pending US20230326936A1 (en)

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