US20230246023A1 - Method for fabricating semiconductor device - Google Patents

Method for fabricating semiconductor device Download PDF

Info

Publication number
US20230246023A1
US20230246023A1 US18/298,322 US202318298322A US2023246023A1 US 20230246023 A1 US20230246023 A1 US 20230246023A1 US 202318298322 A US202318298322 A US 202318298322A US 2023246023 A1 US2023246023 A1 US 2023246023A1
Authority
US
United States
Prior art keywords
layer
semiconductor
silicon
based device
buried oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US18/298,322
Inventor
Zhi-Biao Zhou
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
United Microelectronics Corp
Original Assignee
United Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by United Microelectronics Corp filed Critical United Microelectronics Corp
Priority to US18/298,322 priority Critical patent/US20230246023A1/en
Assigned to UNITED MICROELECTRONICS CORP. reassignment UNITED MICROELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZHOU, Zhi-biao
Publication of US20230246023A1 publication Critical patent/US20230246023A1/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8221—Three dimensional integrated circuits stacked in different levels
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H01L27/0694—Integrated circuits having a three-dimensional layout comprising components formed on opposite sides of a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823481—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate

Definitions

  • the present invention generally relates to semiconductor fabrication technology, and particularly to a method for fabricating semiconductor device with silicon-based device and the semiconductor-based device.
  • the integrated circuit may also include the radiofrequency (RF) component in co-operation with the circuit which is not involved in the RF operation.
  • the fabrication may also use the silicon-on-insulator (SOI) substrate to fabricate the silicon-based device.
  • the RF component may also be the RF power amplifier (PA) or RF power management unit (PMU) or any related component.
  • the performance of the RF components formed from the silicon-based device may be not sufficient.
  • the RF components may be formed from a GaN-based device, which has better performance under RF operation.
  • the invention provides a semiconductor device and a fabrication method thereof, in which the semiconductor-based device and the Si-base device can be formed at both sides of a buried layer, based on the SOI fabrication process.
  • the invention provides a semiconductor device, which comprises a buried oxide layer, having a first side and a second side.
  • a silicon-based device layer is disposed on the first side of the buried oxide layer.
  • the silicon-based device layer comprises a first interconnection structure.
  • a semiconductor-based device layer is disposed on the second side of the buried oxide layer.
  • the semiconductor-based device layer comprises a second interconnection structure.
  • the silicon-based device layer comprises a silicon layer on the first side of the buried oxide layer and the semiconductor-based device layer comprises a semiconductor layer on the second side of the buried oxide layer.
  • the buried oxide layer and the silicon layer form a silicon-on-insulator (SOI) structure.
  • SOI silicon-on-insulator
  • the buried oxide layer and the semiconductor layer form a semiconductor-on-insulator structure.
  • the semiconductor-based device layer comprises a semiconductor-based device on the semiconductor layer and the silicon-based device layer comprises a silicon-based device on the silicon layer.
  • the buried oxide layer has a thickness to mechanically support the semiconductor-based device layer by direct contact.
  • the first interconnection layer comprises a first route structure and a first inter-layer dielectric layer enclosing the first route structure.
  • the second interconnection layer comprises a second route structure and a second inter-layer dielectric layer enclosing the second route structure.
  • the semiconductor device further comprises a third route structure in the buried oxide layer, to electrically connect the first route structure and the second route structure.
  • the third route structure comprises a via through the buried oxide layer to electrically connect the first route structure and the second route structure.
  • the semiconductor-based device layer comprises a semiconductor-based device operated in a radio frequency (RF) range.
  • RF radio frequency
  • the invention also provides a method for fabricating semiconductor device.
  • the method comprises providing a staked layer of a semiconductor layer, a buried oxide layer and a silicon layer.
  • a silicon-based device layer is formed, comprising the silicon layer on the buried oxide layer.
  • a first interconnection layer is formed over the silicon-based device layer.
  • a semiconductor-based device layer is formed, comprising the semiconductor layer on the buried oxide layer.
  • a second interconnection layer is formed over the semiconductor-based device layer.
  • the step of providing the staked layer comprising: forming the semiconductor layer on a supporting substrate; forming the buried oxide layer on the semiconductor layer; and forming the silicon layer on the buried oxide layer.
  • the supporting substrate is removed to expose the semiconductor layer before the step of forming the semiconductor-based device layer.
  • the buried oxide layer and the silicon layer form a silicon-on-insulator (SOI) structure.
  • the buried oxide layer and the semiconductor layer form a semiconductor-on-insulator structure.
  • the semiconductor-based device layer comprises a semiconductor-based device on the semiconductor layer and the silicon-based device layer comprises a silicon-based device on the silicon layer.
  • the buried oxide layer has a thickness to mechanically support the semiconductor-based device layer by direct contact.
  • the step of forming the first interconnection layer comprises forming a first route structure and a first inter-layer dielectric layer enclosing the first route structure.
  • the step of forming the second interconnection layer comprises forming a second route structure and a second inter-layer dielectric layer enclosing the second route structure.
  • the method further comprises forming a third route structure in the buried oxide layer, to electrically connect the first route structure and the second route structure.
  • the third route structure comprises a via through the buried oxide layer to electrically connect the first route structure and the second route structure.
  • the semiconductor-based device layer comprises a semiconductor-based device operated in a radio frequency (RF) range.
  • RF radio frequency
  • FIGS. 1 A to 1 E are drawings, schematically illustrating the method for fabricating semiconductor device, according to an embodiment of the invention.
  • the invention is directed to semiconductor device with silicon-based device and the semiconductor-based device, which are integrated and is fabricated based on the SOI structure.
  • the invention takes the SOI structure to fabricate the usual silicon-based device.
  • the invention additionally introduces a semiconductor layer on the SOI structure, so the semiconductor-base device can be continuously fabricated over the silicon-based device from the opposite side, in which the buried oxide layer belonging to the SOI structure may be commonly used to fabricate the semiconductor-based device.
  • FIG. 1 A to FIG. 1 E are drawings, schematically illustrating the method for fabricating semiconductor device, according to an embodiment of the invention.
  • a substrate 100 is provided for mechanical supporting.
  • the substrate 100 in an embodiment may be a silicon substrate or a glass substrate.
  • a semiconductor layer 102 is formed on the substrate 100 .
  • a buried oxide layer 104 is formed on the semiconductor layer 102 and a silicon layer 106 is formed on the buried oxide layer 104 .
  • the semiconductor layer 102 , the buried oxide layer 104 , and the silicon layer 106 form a stack structure foe fabrication base, in which the silicon layer 106 on the buried oxide layer 104 forms the SOI structure.
  • the semiconductor layer 102 here may be one of GaN, Ga 2 O 3 , GaO, SiC, HSiC, AlN, AlGaN, etc. in an embodiment.
  • the semiconductor layer 102 may provide the channel for the semiconductor-based transistor in an embodiment.
  • the semiconductor layer 102 comprises gallium may be used to integrate with a silicon-based device at two sides of the whole device.
  • the silicon layer 106 is patterned to provide the silicon base for the silicon-based devices 108 , such as the metal-oxide-semiconductor (MOS) transistors.
  • the silicon-based device 108 may also be any other device involving the silicon layer 106 .
  • the silicon-based device 108 needs the route structure 114 to interconnect to other device components.
  • the structures of the silicon-based device 108 and the route structure 114 are formed through the inter-layer dielectric layer 116 .
  • the route structure 114 with the inter-layer dielectric layer 116 is known as the interconnection structure.
  • the silicon-based device layer 202 is formed on the buried oxide layer 104 at one side.
  • the silicon-based device layer 202 includes the silicon-based device 108 and the interconnection structure of the route structure 114 with the inter-layer dielectric layer 116 .
  • the silicon-based device 108 includes a portion of the silicon layer 106 , a device structure 110 on the silicon layer 106 , and a contact 112 to contact the device structure 110 with the silicon layer 106 .
  • the silicon-based device 108 may be a MOS transistor, switch, or any suitable device based on silicon material, but not limited to.
  • the silicon-based device layer 202 is formed on the buried oxide layer 104 , which may also be referred as a base layer 200 , which is integrated with the silicon-based device layer 202 as a first device layer 204 .
  • the first device layer 204 is flipped onto another supporting substrate 150 , so the substrate 100 is at top.
  • the substrate 100 is removed.
  • a polishing or an etching process may be performed to gradually removed the substrate 100 .
  • the substrate 100 is then completely removed to expose the semiconductor layer 102 .
  • the semiconductor layer 102 is patterned to provide the semiconductor base for the semiconductor-based device 302 .
  • the semiconductor-based device 302 may include the semiconductor layer 102 and the device structure 304 on the semiconductor layer 102 and further the contact 306 as needed.
  • the semiconductor-based device 302 in the embodiment represent a general structure. As to the application for the RF device, it can be the power amplifier (PA), power management unit (PMU), or any suitable device based on semiconductor material.
  • PA power amplifier
  • PMU power management unit
  • the inter-connection structure including the route structure 308 and the inter-layer dielectric layer 310 , is also subsequently fabricated.
  • another route structure 312 is also fabricated through the buried oxide layer 104 , so to interconnect the route structure 308 and the route structure 114 .
  • the semiconductor-based device 302 and the silicon-based device 108 are properly interconnected as a single integrated circuit.
  • the semiconductor-based device layer 206 is referred, including the related various device structures.
  • the semiconductor-based device layer 206 is formed on the buried oxide layer at another side opposite to the silicon-based device layer 202 .
  • the buried oxide layer 104 provides the mechanical base for forming the semiconductor-based device 302 .
  • the thickness of the buried oxide layer 104 is sufficient to support the fabrication of the semiconductor-based device layer 202 .
  • the thickness of the buried oxide layer 104 may be about 500 angstroms but the invention is not limited to.
  • the semiconductor-based device 302 is directly fabricated over the buried oxide layer 104 and the semiconductor layer 102 .
  • the supporting substrate 150 is removed, so to have the integrated structures at both sides of the buried oxide layer 104 .
  • the fabrication of the semiconductor-based device in the invention may be straightforwardly fabricated.
  • the whole structure may efficiently integrate the semiconductor-based device 302 with the silicon-based device 108 .
  • the silicon-based device layer 202 and/or the semiconductor-based device may also include other related passive devices in fabrication process.
  • the circuit of all-in-one structure may be easily fabricated, in which the RF component may be involved.
  • the package size of the semiconductor device can be achieved.

Abstract

A method for fabricating a semiconductor device is provided, including following steps. Providing a staked layer of a semiconductor layer, a buried oxide layer and a silicon layer. Forming a silicon-based device layer comprising the silicon layer on the buried oxide layer. Forming a first interconnection layer over the silicon-based device layer. Forming a semiconductor-based device layer comprising the semiconductor layer on the buried oxide layer. Forming a second interconnection layer over the semiconductor-based device layer.

Description

    CROSS-REFERENCE TO RELATED APPLICATION
  • This application is a divisional application of and claims the priority benefit of a prior application serial no. 16/262,779, filed on Jan. 30, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
    • BACKGROUND 1. Field of the Invention
  • The present invention generally relates to semiconductor fabrication technology, and particularly to a method for fabricating semiconductor device with silicon-based device and the semiconductor-based device.
    • 2. Description of Related Art
  • To have more functionality and better performance, an integrated circuit is designed with various semiconductor devices. In an example, the integrated circuit may also include the radiofrequency (RF) component in co-operation with the circuit which is not involved in the RF operation. In addition, to fabricate the integrated circuit, the fabrication may also use the silicon-on-insulator (SOI) substrate to fabricate the silicon-based device. In addition, the RF component may also be the RF power amplifier (PA) or RF power management unit (PMU) or any related component.
  • However, the performance of the RF components formed from the silicon-based device may be not sufficient. Then, the RF components may be formed from a GaN-based device, which has better performance under RF operation.
  • How to properly integrate the silicon-based device and the GaN-based device together as an integrated circuit is still an issue to develop in semiconductor fabrication technology.
    • SUMMARY OF THE INVENTION
  • The invention provides a semiconductor device and a fabrication method thereof, in which the semiconductor-based device and the Si-base device can be formed at both sides of a buried layer, based on the SOI fabrication process.
  • In an embodiment, the invention provides a semiconductor device, which comprises a buried oxide layer, having a first side and a second side. A silicon-based device layer is disposed on the first side of the buried oxide layer. The silicon-based device layer comprises a first interconnection structure. A semiconductor-based device layer is disposed on the second side of the buried oxide layer. The semiconductor-based device layer comprises a second interconnection structure.
  • In an embodiment, as to the semiconductor device, the silicon-based device layer comprises a silicon layer on the first side of the buried oxide layer and the semiconductor-based device layer comprises a semiconductor layer on the second side of the buried oxide layer.
  • In an embodiment, as to the semiconductor device, the buried oxide layer and the silicon layer form a silicon-on-insulator (SOI) structure.
  • In an embodiment, as to the semiconductor device, the buried oxide layer and the semiconductor layer form a semiconductor-on-insulator structure.
  • In an embodiment, as to the semiconductor device, the semiconductor-based device layer comprises a semiconductor-based device on the semiconductor layer and the silicon-based device layer comprises a silicon-based device on the silicon layer.
  • In an embodiment, as to the semiconductor device, the buried oxide layer has a thickness to mechanically support the semiconductor-based device layer by direct contact.
  • In an embodiment, as to the semiconductor device, the first interconnection layer comprises a first route structure and a first inter-layer dielectric layer enclosing the first route structure. The second interconnection layer comprises a second route structure and a second inter-layer dielectric layer enclosing the second route structure.
  • In an embodiment, as to the semiconductor device, it further comprises a third route structure in the buried oxide layer, to electrically connect the first route structure and the second route structure.
  • In an embodiment, as to the semiconductor device, the third route structure comprises a via through the buried oxide layer to electrically connect the first route structure and the second route structure.
  • In an embodiment, as to the semiconductor device, the semiconductor-based device layer comprises a semiconductor-based device operated in a radio frequency (RF) range.
  • In an embodiment, the invention also provides a method for fabricating semiconductor device. The method comprises providing a staked layer of a semiconductor layer, a buried oxide layer and a silicon layer. A silicon-based device layer is formed, comprising the silicon layer on the buried oxide layer. A first interconnection layer is formed over the silicon-based device layer. A semiconductor-based device layer is formed, comprising the semiconductor layer on the buried oxide layer. A second interconnection layer is formed over the semiconductor-based device layer.
  • In an embodiment, as to the method for fabricating semiconductor device, the step of providing the staked layer comprising: forming the semiconductor layer on a supporting substrate; forming the buried oxide layer on the semiconductor layer; and forming the silicon layer on the buried oxide layer. The supporting substrate is removed to expose the semiconductor layer before the step of forming the semiconductor-based device layer.
  • In an embodiment, as to the method for fabricating semiconductor device, the buried oxide layer and the silicon layer form a silicon-on-insulator (SOI) structure.
  • In an embodiment, as to the method for fabricating semiconductor device, the buried oxide layer and the semiconductor layer form a semiconductor-on-insulator structure.
  • In an embodiment, as to the method for fabricating semiconductor device, the semiconductor-based device layer comprises a semiconductor-based device on the semiconductor layer and the silicon-based device layer comprises a silicon-based device on the silicon layer.
  • In an embodiment, as to the method for fabricating semiconductor device, the buried oxide layer has a thickness to mechanically support the semiconductor-based device layer by direct contact.
  • In an embodiment, as to the method for fabricating semiconductor device, the step of forming the first interconnection layer comprises forming a first route structure and a first inter-layer dielectric layer enclosing the first route structure. The step of forming the second interconnection layer comprises forming a second route structure and a second inter-layer dielectric layer enclosing the second route structure.
  • In an embodiment, as to the method for fabricating semiconductor device, the method further comprises forming a third route structure in the buried oxide layer, to electrically connect the first route structure and the second route structure.
  • In an embodiment, as to the method for fabricating semiconductor device, the third route structure comprises a via through the buried oxide layer to electrically connect the first route structure and the second route structure.
  • In an embodiment, as to the method for fabricating semiconductor device, the semiconductor-based device layer comprises a semiconductor-based device operated in a radio frequency (RF) range.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
  • FIGS. 1A to 1E are drawings, schematically illustrating the method for fabricating semiconductor device, according to an embodiment of the invention.
    •  DESCRIPTION OF THE EMBODIMENTS
  • The invention is directed to semiconductor device with silicon-based device and the semiconductor-based device, which are integrated and is fabricated based on the SOI structure.
  • Several embodiments are provided for describing the invention but the invention is not limited to the embodiments as provided.
  • The invention takes the SOI structure to fabricate the usual silicon-based device. However, the invention additionally introduces a semiconductor layer on the SOI structure, so the semiconductor-base device can be continuously fabricated over the silicon-based device from the opposite side, in which the buried oxide layer belonging to the SOI structure may be commonly used to fabricate the semiconductor-based device.
  • FIG. 1A to FIG. 1E are drawings, schematically illustrating the method for fabricating semiconductor device, according to an embodiment of the invention.
  • Referring to FIG. 1A, to have the SOI structure, a substrate 100 is provided for mechanical supporting. The substrate 100 in an embodiment may be a silicon substrate or a glass substrate. A semiconductor layer 102 is formed on the substrate 100. A buried oxide layer 104 is formed on the semiconductor layer 102 and a silicon layer 106 is formed on the buried oxide layer 104. The semiconductor layer 102, the buried oxide layer 104, and the silicon layer 106 form a stack structure foe fabrication base, in which the silicon layer 106 on the buried oxide layer 104 forms the SOI structure.
  • As to be noted, the semiconductor layer 102 here may be one of GaN, Ga2O3, GaO, SiC, HSiC, AlN, AlGaN, etc. in an embodiment. The semiconductor layer 102 may provide the channel for the semiconductor-based transistor in an embodiment. However, the semiconductor layer 102 comprises gallium may be used to integrate with a silicon-based device at two sides of the whole device.
  • Referring to FIG. 1B, the silicon layer 106 is patterned to provide the silicon base for the silicon-based devices 108, such as the metal-oxide-semiconductor (MOS) transistors. The silicon-based device 108 may also be any other device involving the silicon layer 106.
  • As usually known, the silicon-based device 108 needs the route structure 114 to interconnect to other device components. Generally as to fabrication, the structures of the silicon-based device 108 and the route structure 114 are formed through the inter-layer dielectric layer 116. The route structure 114 with the inter-layer dielectric layer 116 is known as the interconnection structure. Generally, the silicon-based device layer 202 is formed on the buried oxide layer 104 at one side. The silicon-based device layer 202 includes the silicon-based device 108 and the interconnection structure of the route structure 114 with the inter-layer dielectric layer 116. The silicon-based device 108 includes a portion of the silicon layer 106, a device structure 110 on the silicon layer 106, and a contact 112 to contact the device structure 110 with the silicon layer 106. In an embodiment, the silicon-based device 108 may be a MOS transistor, switch, or any suitable device based on silicon material, but not limited to.
  • So far, as to the fabrication, the silicon-based device layer 202 is formed on the buried oxide layer 104, which may also be referred as a base layer 200, which is integrated with the silicon-based device layer 202 as a first device layer 204.
  • Referring to FIG. 1C, the first device layer 204 is flipped onto another supporting substrate 150, so the substrate 100 is at top. The substrate 100 is removed. In an embodiment, if the substrate 100 is a silicon substrate, then a polishing or an etching process may be performed to gradually removed the substrate 100. Referring to FIG. 1D, the substrate 100 is then completely removed to expose the semiconductor layer 102.
  • Referring to FIG. 1E, the semiconductor layer 102 is patterned to provide the semiconductor base for the semiconductor-based device 302. The semiconductor-based device 302 may include the semiconductor layer 102 and the device structure 304 on the semiconductor layer 102 and further the contact 306 as needed. The semiconductor-based device 302 in the embodiment represent a general structure. As to the application for the RF device, it can be the power amplifier (PA), power management unit (PMU), or any suitable device based on semiconductor material. In order to interconnect the semiconductor-based device 302 to the other part, the inter-connection structure, including the route structure 308 and the inter-layer dielectric layer 310, is also subsequently fabricated.
  • Further, another route structure 312, include the via structure, is also fabricated through the buried oxide layer 104, so to interconnect the route structure 308 and the route structure 114. As a result, the semiconductor-based device 302 and the silicon-based device 108 are properly interconnected as a single integrated circuit. Generally, the semiconductor-based device layer 206 is referred, including the related various device structures. The semiconductor-based device layer 206 is formed on the buried oxide layer at another side opposite to the silicon-based device layer 202.
  • In fabrication, the buried oxide layer 104 provides the mechanical base for forming the semiconductor-based device 302. The thickness of the buried oxide layer 104 is sufficient to support the fabrication of the semiconductor-based device layer 202. In an embodiment, the thickness of the buried oxide layer 104 may be about 500 angstroms but the invention is not limited to. In the invention, the semiconductor-based device 302 is directly fabricated over the buried oxide layer 104 and the semiconductor layer 102.
  • In addition, the supporting substrate 150 is removed, so to have the integrated structures at both sides of the buried oxide layer 104. The fabrication of the semiconductor-based device in the invention may be straightforwardly fabricated. The whole structure may efficiently integrate the semiconductor-based device 302 with the silicon-based device 108.
  • Further, the silicon-based device layer 202 and/or the semiconductor-based device may also include other related passive devices in fabrication process. As a result, the circuit of all-in-one structure may be easily fabricated, in which the RF component may be involved. The package size of the semiconductor device can be achieved.
  • It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.

Claims (10)

What is claimed is:
1. A method for fabricating a semiconductor device, comprising:
providing a staked layer of a semiconductor layer, a buried oxide layer and a silicon layer;
forming a silicon-based device layer comprising the silicon layer on the buried oxide layer;
forming a first interconnection layer over the silicon-based device layer;
forming a semiconductor-based device layer comprising the semiconductor layer on the buried oxide layer; and
forming a second interconnection layer over the semiconductor-based device layer.
2. The method of claim 1, wherein the step of providing the staked layer comprising:
forming the semiconductor layer on a supporting substrate;
forming the buried oxide layer on the semiconductor layer; and
forming the silicon layer on the buried oxide layer,
wherein the supporting substrate is removed to expose the semiconductor layer before the step of forming the semiconductor-based device layer.
3. The method of claim 2, wherein the buried oxide layer and the silicon layer form a silicon-on-insulator (SOI) structure.
4. The method of claim 2, wherein the buried oxide layer and the semiconductor layer form a semiconductor-on-insulator structure.
5. The method of claim 2, wherein the semiconductor-based device layer comprises a semiconductor-based device on the semiconductor layer and the silicon-based device layer comprises a silicon-based device on the silicon layer.
6. The method of claim 1, wherein the buried oxide layer has a thickness to mechanically support the semiconductor-based device layer by direct contact.
7. The method of claim 1,
wherein the step of forming the first interconnection layer comprises forming a first route structure and a first inter-layer dielectric layer enclosing the first route structure,
wherein the step of forming the second interconnection layer comprises forming a second route structure and a second inter-layer dielectric layer enclosing the second route structure.
8. The method of claim 1, further comprising:
forming a third route structure in the buried oxide layer, to electrically connect the first route structure and the second route structure.
9. The method of claim 8, wherein the third route structure comprises a via through the buried oxide layer to electrically connect the first route structure and the second route structure.
10. The method of claim 1, wherein the semiconductor-based device layer comprises a semiconductor-based device operated in a radio frequency (RF) range.
US18/298,322 2019-01-30 2023-04-10 Method for fabricating semiconductor device Pending US20230246023A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US18/298,322 US20230246023A1 (en) 2019-01-30 2023-04-10 Method for fabricating semiconductor device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/262,779 US11664372B2 (en) 2019-01-30 2019-01-30 Semiconductor device integrating silicon-based device with semiconductor-based device and method for fabricating the same
US18/298,322 US20230246023A1 (en) 2019-01-30 2023-04-10 Method for fabricating semiconductor device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US16/262,779 Division US11664372B2 (en) 2019-01-30 2019-01-30 Semiconductor device integrating silicon-based device with semiconductor-based device and method for fabricating the same

Publications (1)

Publication Number Publication Date
US20230246023A1 true US20230246023A1 (en) 2023-08-03

Family

ID=71731531

Family Applications (2)

Application Number Title Priority Date Filing Date
US16/262,779 Active 2039-06-24 US11664372B2 (en) 2019-01-30 2019-01-30 Semiconductor device integrating silicon-based device with semiconductor-based device and method for fabricating the same
US18/298,322 Pending US20230246023A1 (en) 2019-01-30 2023-04-10 Method for fabricating semiconductor device

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US16/262,779 Active 2039-06-24 US11664372B2 (en) 2019-01-30 2019-01-30 Semiconductor device integrating silicon-based device with semiconductor-based device and method for fabricating the same

Country Status (1)

Country Link
US (2) US11664372B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11476248B2 (en) * 2019-12-26 2022-10-18 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional integrated circuit and fabrication thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR900008647B1 (en) 1986-03-20 1990-11-26 후지쓰 가부시끼가이샤 A method for manufacturing three demensional i.c.
US9142620B2 (en) 2012-08-24 2015-09-22 Rf Micro Devices, Inc. Power device packaging having backmetals couple the plurality of bond pads to the die backside
JP6143598B2 (en) 2013-08-01 2017-06-07 株式会社東芝 Semiconductor device
US10347656B2 (en) * 2016-07-18 2019-07-09 Semiconductor Components Industries, Llc Semiconductor device and monolithic semiconductor device including a power semiconductor device and a control circuit
US10847624B2 (en) * 2016-09-27 2020-11-24 Intel Corporation Methods and apparatus to form GaN-based transistors during back-end-of-the-line processing
US10784348B2 (en) * 2017-03-23 2020-09-22 Qualcomm Incorporated Porous semiconductor handle substrate
US10629620B2 (en) * 2018-09-10 2020-04-21 International Business Machines Corporation Fully depleted semiconductor-on-insulator transistors with different buried dielectric layer charges and different threshold voltages
US20200135766A1 (en) * 2018-10-30 2020-04-30 Qualcomm Incorporated Monolithic integration of gan hemt and si cmos
US11538803B2 (en) * 2018-12-14 2022-12-27 Intel Corporation Integration of III-V transistors in a silicon CMOS stack
US11721677B2 (en) * 2018-12-27 2023-08-08 Intel Corporation Microelectronic assemblies having an integrated capacitor
US11011411B2 (en) * 2019-03-22 2021-05-18 International Business Machines Corporation Semiconductor wafer having integrated circuits with bottom local interconnects

Also Published As

Publication number Publication date
US20200243515A1 (en) 2020-07-30
US11664372B2 (en) 2023-05-30

Similar Documents

Publication Publication Date Title
US10109548B2 (en) Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US7232708B2 (en) Multi-mode integrated circuit structure
KR100423780B1 (en) Semiconductor substrate and method for fabricating the same
JP5091445B2 (en) Semiconductor device and manufacturing method thereof
US7579623B2 (en) Stacked transistors and process
US20200135766A1 (en) Monolithic integration of gan hemt and si cmos
US20050082531A1 (en) Double silicon-on-insulator (SOI) metal oxide semiconductor field effect transistor (MOSFET) structures
US20090115052A1 (en) Hybrid silicon/non-silicon electronic device with heat spreader
US20230246023A1 (en) Method for fabricating semiconductor device
US9793389B1 (en) Apparatus and method of fabrication for GaN/Si transistors isolation
US11211308B2 (en) Semiconductor device and manufacturing method thereof
US20150249056A1 (en) Semiconductor-on-insulator with back side support layer
JP2006229218A (en) Method for manufacturing semiconductor device and resulting device
US6048777A (en) Fabrication of high power semiconductor devices with respective heat sinks for integration with planar microstrip circuitry
JP4872409B2 (en) Manufacturing method of semiconductor device
US10686037B2 (en) Semiconductor structure with insulating substrate and fabricating method thereof
US7666735B1 (en) Method for forming semiconductor devices with active silicon height variation
US10164101B1 (en) Transistor with improved channel mobility
US10074650B2 (en) Deep trench isolation for RF devices on SOI
US9349748B2 (en) Method for forming deep trench isolation for RF devices on SOI
US20090159974A1 (en) Semiconductor device
US7880261B2 (en) Isolation technique allowing both very high and low voltage circuits to be fabricated on the same chip
CN117650170A (en) High electron mobility transistor

Legal Events

Date Code Title Description
AS Assignment

Owner name: UNITED MICROELECTRONICS CORP., TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:ZHOU, ZHI-BIAO;REEL/FRAME:063336/0364

Effective date: 20190128

STPP Information on status: patent application and granting procedure in general

Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION

STPP Information on status: patent application and granting procedure in general

Free format text: NON FINAL ACTION MAILED