US20230231695A1 - Clock Synchronization Loop - Google Patents
Clock Synchronization Loop Download PDFInfo
- Publication number
- US20230231695A1 US20230231695A1 US17/579,630 US202217579630A US2023231695A1 US 20230231695 A1 US20230231695 A1 US 20230231695A1 US 202217579630 A US202217579630 A US 202217579630A US 2023231695 A1 US2023231695 A1 US 2023231695A1
- Authority
- US
- United States
- Prior art keywords
- clock
- compute nodes
- compute
- compute node
- master
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004891 communication Methods 0.000 claims abstract description 12
- 230000001360 synchronised effect Effects 0.000 claims abstract description 8
- 238000012545 processing Methods 0.000 claims description 32
- 238000000034 method Methods 0.000 claims description 29
- 238000009826 distribution Methods 0.000 claims description 9
- 230000000903 blocking effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 8
- 230000006870 function Effects 0.000 description 4
- 238000001914 filtration Methods 0.000 description 3
- 238000009877 rendering Methods 0.000 description 3
- 230000007257 malfunction Effects 0.000 description 2
- 230000006855 networking Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000003860 storage Methods 0.000 description 2
- 230000003190 augmentative effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
- H04L7/0012—Synchronisation information channels, e.g. clock distribution lines by comparing receiver clock with transmitter clock
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0658—Clock or time synchronisation among packet nodes
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0679—Clock or time synchronisation in a network by determining clock distribution path in a network
Definitions
- the present invention relates to computer systems, and in particular, but not exclusively to, clock synchronization.
- Clock and frequency synchronization among network devices is used in many network applications.
- One application of using a synchronized clock value is for measuring latency between two devices. If the clocks are not synchronized the resulting latency measurement will be inaccurate.
- Synchronous Ethernet is an International Telecommunication Union Telecommunication (ITU-T) Standardization Sector standard for computer networking that facilitates the transference of clock signals over the Ethernet physical layer.
- SyncE enables clock synchronization inside a network with respect to a master clock.
- Each network element e.g., a switch, a network interface card (MC), or router
- MC network interface card
- SyncE provides synchronization with respect to clock frequency.
- the actual clock value (e.g., in Coordinated Universal Time (UTC) fomiat) is handled by higher layer standards and protocols, such as Precision Time Protocol (PTP).
- UTC Coordinated Universal Time
- PTP Precision Time Protocol
- Time, clock and frequency synchronization is crucial in some of the modern computer network applications. It enables 5G and 6G networks, and is proven to enhance the performance of data center workloads.
- the SyncE standard allows improving Precision Time Protocol (PTP) accuracy by having less accumulated drift between PTP messages, and helps achieve an accurate time solution for an extended period after completely losing a PTP source.
- PTP Precision Time Protocol
- a synchronized communication system including a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
- the system includes a controller to selectively block and unblock distribution of the master clock frequency in the closed loop responsively to one of the compute nodes being designated as a master clock.
- the compute nodes include at least one of the following a data processing unit (DPU), graphics processing unit (GPU), switch, network interface controller.
- DPU data processing unit
- GPU graphics processing unit
- switch network interface controller
- each of the compute nodes includes one or more ports to transmit and receive respective communication signals over respective network links, and clock synchronization circuitry to process at least one of the respective communication signals received by the one or more ports so as to recover a respective remote clock.
- each of the compute nodes includes clock synchronization circuitry to recover a remote clock, a clock input port connected to another clock output port of a first one of the compute nodes via a first one of the clock connections, and configured to receive a clock signal at the master clock frequency from the first compute node, and a clock output port connected to another clock input port of a second one of the compute nodes via a second one of the clock connections.
- the first compute node and the second compute node are a same one of the compute nodes.
- the clock synchronization circuitry is configured to discipline a local clock signal to the master clock frequency responsively to the recovered respective remote clock, or the received clock signal, and output the disciplined local clock signal via the clock output port to the second compute node.
- the clock synchronization circuitry includes a frequency synthesizer.
- the frequency synthesizer is a frequency jitter synchronizer.
- the frequency synthesizer is a jitter network synchronizer clock.
- the clock synchronization circuitry is configured to discipline a local clock signal to the master clock frequency responsively to the recovered respective remote clock, and output the disciplined local clock signal via the clock output port to the second compute node.
- the clock synchronization circuitry is configured to ignore the clock signal received by the clock input port.
- the system includes a controller to selectively block distribution of the master clock frequency in the closed loop by instructing the clock synchronization circuitry to ignore the clock signal received by the clock input port responsively to one of the compute nodes being designated as a master clock.
- the clock synchronization circuitry is configured to discipline a local clock signal to the master clock frequency responsively to the received clock signal, and output the disciplined local clock signal via the clock output port to the second compute node.
- the compute nodes are configured to distribute the master clock frequency via respective ones of the clock connections using at least one of a one pulse per second (PPS) signal, or a 10 mega. Hertz ( 10 MHz) signal.
- PPS pulse per second
- 10 MHz 10 mega. Hertz
- a synchronized communication method including connecting compute nodes with clock connections in a closed loop configuration, and distributing among the compute nodes a master clock frequency from any selected one of the compute nodes.
- the method includes selectively blocking and unblocking distribution of the master clock frequency in the closed loop responsively to one of the compute nodes being designated as a master clock.
- the compute nodes include at least one of the following a data processing unit (DPU), graphics processing unit (GPU), switch, network interface controller.
- DPU data processing unit
- GPU graphics processing unit
- switch network interface controller
- the method includes recovering a remote clock, connecting a clock input port to another clock output port of a first one of the compute nodes via a first one of the clock connections, receiving a clock signal at the master clock frequency from the first compute node, and connecting a clock output port to another clock input port of a second one of the compute nodes via a second one of the clock connections.
- first compute node and the second compute node are a same one of the compute nodes.
- the method includes disciplining a local clock signal to the master clock frequency responsively to the recovered respective remote clock, or the received clock signal, and outputting the disciplined local clock signal via the clock output port to the second compute node.
- the method includes disciplining a local clock signal to the master clock frequency responsively to the recovered respective remote clock, and outputting the disciplined local clock signal via the clock output port to the second compute node.
- the method includes ignoring the clock signal received by the clock input port.
- the method includes selectively blocking distribution of the master clock frequency in the closed loop by instructing clock synchronization circuitry to ignore the clock signal received by the clock input port responsively to one of the compute nodes being designated as a master clock.
- the method includes disciplining a local clock signal to the master clock frequency responsively to the received clock signal, and outputting the disciplined local clock signal via the clock output port to the second compute node.
- the method includes distributing the master clock frequency via respective ones of the clock connections using at least one of a one pulse per second (PPS) signal, or a 10 mega Hertz (10 MHz) signal.
- PPS pulse per second
- 10 MHz 10 mega Hertz
- FIG. 1 is a block diagram view of a clock synchronization system with one compute node designated as a master clock constructed and operative in accordance with an embodiment of the present invention
- FIG. 2 is a block diagram view of the clock synchronization system of FIG. 1 with another compute node designated as the master clock;
- FIG. 3 is a flowchart including steps in a method of operation of a controller of the system of FIG. 1 ;
- FIG. 4 is a flowchart including steps in a method of operation of clock synchronization circuitry in a compute node in the system of FIG. 1 ;
- FIG. 5 is a block diagram view of a clock synchronization system with two compute nodes constructed and operative in accordance with an alternative embodiment of the present invention.
- FIG. 6 is a more detailed block diagram view of a compute node in the system of FIG. 1 .
- Clock synchronization between compute nodes remains an unsolved challenge in the networking industry.
- One solution is to use SyncE clock chaining by chaining multiple SyncE capable devices together so that the master clock is distributed from one compute node at the root of the chain to other compute nodes in the chain.
- the root is defined by wiring topology.
- SyncE clock chaining may have some limitations including imposing a local clock hierarchy that is dictated by the physical wiring, introducing a possible “single point of failure” since the root controls the frequency of the entire chain. For example, if the compute node at the root malfunctions, it then becomes impossible to distribute the clock among the remaining compute nodes. Therefore, if the master clock moves to another of the compute nodes, the master clock cannot be distributed based on the physical wiring.
- Embodiments of the present invention solve at least some of the above problems by connecting compute nodes using clock connections to connect the compute nodes in a closed loop configuration.
- compute node 1 is connected to compute node 2 , which is connected to compute node 3 , which is connected to compute node 1 , forming a closed loop.
- the closed loop may then be used to distribute a master clock frequency among the compute nodes from any selected one of the compute nodes in the closed loop by passing the master clock frequency from compute node to compute node in the closed loop. For example, if one of the compute nodes is designated as a master clock, the master clock frequency is distributed from the compute node designated as the master clock to the other compute nodes via the clock connections of the closed loop.
- the master clock frequency is distributed from the compute node of the newly designated master clock to the other compute nodes via the clock connections of the closed loop. Therefore, if one of the compute nodes malfunctions, it is still possible to operate another one of the compute nodes to distribute the master clock frequency.
- a clock output port of one compute node is connected to the clock input port of another compute node with a cable or other connection (e.g., a trace on a circuit board), and so on, until all the compute nodes are connected together in a closed loop.
- the clock output port of node 1 is connected to the clock input port of node 2 , and so on.
- the clock output port of node 3 is connected to the clock input port of node 1 , thereby completing the loop.
- a compute node in the closed loop uses the received clock signal to discipline its local clock signal. The received clock signal may then be output via the clock output port of that compute node to the next compute node in the chain, and so on.
- the compute node designated as the master clock should not use a clock signal received from another compute node to discipline its local clock signal. Instead, the compute node designated as the master clock disciplines its local clock signal from a recovered remote clock. It is this recovered remote clock which is distributed around the loop to the other compute nodes.
- software or firmware running on a controller breaks the chain of the closed loop so that the compute node designated as the master clock does not use a clock signal received via its clock input port. Therefore, software or firmware may instruct the compute node designated as the master clock to ignore the received clock signal at its clock input port and by default use the recovered remote clock to discipline its local clock signal.
- software or firmware running on a controller breaks the chain of the closed loop so that the compute node designated as the master clock does not receive a clock signal via its clock input port. Therefore, in some embodiments, the software or firmware running on the controller may instruct the compute node, which would otherwise pass its clock via its clock output port to the compute node of the designated master clock, to not output a clock signal to the compute node of the designated master clock.
- Each of the compute nodes may include clock synchronization circuitry which performs at least some of the following: recovering a remote clock and disciplining a local clock signal based on the recovered remote clock, receiving the clock signal via the chain, discipling the local clock signal based on the received clock signal, and passing the local clock signal to the next compute node in the chain.
- the clock synchronization circuitry may include a frequency jitter synchronizer, for example, a low or ultra-low frequency jitter synchronizer.
- An example of a suitable frequency synthesizer is Ultra-Low Jitter Network Synchronizer Clock LMK 05318 commercially available from Texas Instruments Inc., 12500 TI Boulevard Dallas, Tex. 75243 USA.
- FIG. 1 is a block diagram view of a clock synchronization system 10 with one compute node 12 - 2 designated as a master clock constructed and operative in accordance with an embodiment of the present invention.
- the system 10 includes a plurality of compute nodes 12 (labeled compute nodes 12 - 1 , 12 - 2 , 12 - 3 ), and a controller 14 .
- Each compute node 12 may include processing circuitry 16 , one or more ports 18 , clock synchronization circuitry 20 (which optionally includes a frequency synchronizer 22 ), an oscillator 24 , a clock input port 26 , and a clock output port 28 .
- a plurality of clock connections 30 are configured to connect the compute nodes 12 in a closed loop configuration.
- compute node 12 - 1 is connected to compute node 12 - 2 , which is connected to compute node 12 - 3 , which in turn is connected to compute node 12 - 1 via the clock connections 30 as described in more detail below.
- FIG. 1 shows three compute nodes 12 connected together in a closed loop configuration.
- the system 10 may include two compute nodes 12 connected together in a closed loop configuration, described in more detail with reference to FIG. 5 .
- the system 10 may include more than three compute nodes 12 connected together in a closed loop configuration.
- the compute nodes 12 may be disposed on the same printed circuit board (not shown) with the clock connections 30 being implemented using printed circuit board (PCB) traces (not shown) on the circuit board between the compute nodes 12 .
- PCB printed circuit board
- the processing circuitry 16 may include hardwired processing circuitry and/or one or more processors on which to execute software.
- the software may be downloaded to the compute node 12 or disposed on the compute node 12 at manufacture.
- the processing circuitry 16 may include packet processing circuitry which may include a physical layer (PHY) chip and MAC chip (not shown).
- the processing circuitry 16 may include switching circuitry, and/or a data processing unit (DPU) and/or graphics processing unit (GPU) or any suitable processor, described in more detail with reference to FIG. 6 .
- DPU data processing unit
- GPU graphics processing unit
- the port(s) 18 are configured to transmit and receive respective communication signals over respective network links, for example, to receive a clock synchronization signal or clock synchronization packets from a remote clock 32 .
- the clock synchronization signal or clock synchronization packets may be received via any suitable interface via any suitable communication method and protocol.
- the clock input port 26 of one of the compute nodes 12 is connected to the clock output port 28 of another one of the compute nodes 12 (e.g., compute node 12 - 3 ) via one of the clock connections 30 , and configured to receive a clock signal at the master clock frequency from the other compute node 12 (e.g., compute node 12 - 3 ).
- the clock output port 28 of one of the compute nodes 12 is connected to the clock input port 26 of another one of the compute nodes 12 (e.g., compute node 12 - 2 ) via one of the clock connections 30 .
- the clock output port 28 of the compute node 12 - 2 is connected to the clock input port 26 of the compute node 12 - 3 via one of the clock connections 30 .
- the compute nodes 12 are configured to distribute among the compute nodes 12 a master clock frequency from any selected one of the compute nodes, for example, the computer node 12 - 2 designated as the master clock.
- the compute node 12 - 2 disciplines its local clock signal from the remote clock 32 and is designated as the master clock, for example by the controller 14 .
- the compute node 12 - 2 distributes its local clock signal as the master clock frequency via the clock output port 28 of compute node 12 - 2 to the clock input port 26 of compute node 12 - 3 .
- the compute node 12 - 3 disciplines its local clock signal responsively to the received clock signal received at the clock input port 26 of compute node 12 - 3 .
- the compute node 12 - 3 distributes its local clock signal as the master clock frequency via the clock output port 28 of compute node 12 - 3 to the clock input port 26 of compute node 12 - 1 .
- the compute node 12 - 1 disciplines its local clock signal responsively to the received clock signal received at the clock input port 26 of compute node 12 - 1 .
- the compute node 12 - 1 is instructed by the controller 14 not to distribute its local clock signal via the clock output port 28 of compute node 12 - 1 .
- the compute node 12 - 1 distributes its local clock signal as the master clock frequency via the clock output port 28 of compute node 12 - 1 to the clock input port 26 of compute node 12 - 2 , which is instructed by the controller 14 to ignore the received clock signal received at the clock input port 26 of compute node 12 - 2 .
- the compute nodes 12 may be configured to distribute the master clock frequency via respective clock connections 30 in the form of any signal which is scaled proportional to master clock frequency using one pulse per second (PPS) signal(s) or 10 mega Hertz (10 MHz) signal(s).
- PPS pulse per second
- the scaling factor may be used by the clock synchronization circuitry 20 of the outputting compute node 12 to scale the master clock frequency to one PPS or 10 MHz, for example, and by the clock synchronization circuitry 20 of the receiving compute node 12 to rebuild the received signal (e.g., one PPS or 10 MHz) to the master clock frequency.
- the frequency synchronizer 22 is a frequency jitter synchronizer or a jitter network synchronizer clock.
- the frequency synchronizer 22 may be configured to tune a network frequency, feed the clock of the compute node 12 , and provide phase lock loop (PLL) capabilities.
- the frequency synchronizer 22 include an application-specific integrated circuit (ASIC) and/or a programmable device with analog circuitry mainly for phase lock loop (PLL) capabilities.
- the frequency synchronizer 22 may be a low or ultra-low frequency jitter synchronizer.
- An example of a suitable frequency synthesizer is Ultra-Low Jitter Network Synchronizer Clock LMK05318 commercially available from Texas Instruments Inc., 12500 TI Boulevard, Dallas, Tex. 75243 USA.
- the frequency synchronizer 22 adjusts the output of the oscillator 24 to provide a local clock signal based on a clock recovered from the remote clock 32 .
- the clock signal received at the clock input port 26 is used by the frequency synchronizer 22 to drive the local clock signal, generally without using the output of the oscillator 24 .
- the frequency synchronizer 22 is configured to use the clock signal received at the clock input port 26 if such a clock signal is received. If not, the frequency synchronizer 22 disciplines the local clock signal based on the output of the oscillator 24 and/or a recovered remote clock. Therefore, in some embodiments, software or firmware running on the controller 14 breaks the chain of the closed loop so that the compute node 12 - 2 designated as the master clock does not use a clock signal received at its clock input port 26 or does not receive a clock signal at its clock input port 26 , as described in more detail with reference to FIG. 3 .
- each compute node 12 looks for a clock signal being received at its own clock input port 26 and if a clock signal is not found, the respective compute node 12 uses a local clock, for example, based on an output of the oscillator 24 in that compute node 12 . Therefore, the first compute node 12 to boot up outputs a clock signal based on a local clock from its clock output port 28 to the next compute node 12 in the closed loop. The next compute node 12 then detects the clock signal input via its clock input port 26 and uses the received clock signal to discipline its local clock signal, and so on.
- one of the compute nodes 12 When one of the compute nodes 12 is designated as a master clock, that compute node 12 does not use the clock signal received at its clock input port 26 , but disciplines its local clock signal based on the remote clock 32 and outputs its local clock signal via its clock output port 28 to the next compute node 12 in the loop, and so on. Another option is to assign one of the compute nodes 12 as a default master clock.
- FIG. 2 is a block diagram view of the clock synchronization system of FIG. 1 with compute node 12 - 3 designated as the master clock.
- the master clock may be moved from one compute node 12 to another due to many reasons, for example, the remote clock 32 used by one of the compute nodes 12 previously designated as the master clock may now be non-functional or deemed to be less accurate than a remote clock used by another one of the compute nodes 12 now designated as the master clock.
- the compute node 12 - 3 is now designated as the master clock (for example, by the controller 14 ), and disciplines its local clock signal from the remote clock 32 .
- the compute node 12 - 3 may: ignore any clock signal received at its clock input port 26 ; or the controller 14 may instruct the compute node 12 - 2 to cease outputting the local clock signal of compute node 12 - 2 via the clock output port 28 of compute node 12 - 2 .
- the compute node 12 - 3 distributes its local clock signal as the master clock frequency via the clock output port 28 of compute node 12 - 3 to the clock input port 26 of the compute node 12 - 1 .
- the compute node 12 - 1 disciplines its local clock signal responsively to the received clock signal received at the clock input port 26 of compute node 12 - 1 .
- the compute node 12 - 1 distributes its local clock signal as the master clock frequency via the clock output port 28 of compute node 12 - 1 to the clock input port 26 of compute node 12 - 2 .
- the compute node 12 - 2 disciplines its local clock signal responsively to the received clock signal received at the clock input port 26 of compute node 12 - 2 .
- the compute node 12 - 2 is instructed by the controller 14 not to distribute its local clock signal via the clock output port 28 of compute node 12 - 2 .
- the compute node 12 - 2 distributes its local clock signal as the master clock frequency via the clock output port 28 of compute node 12 - 2 to the clock input port 26 of compute node 12 - 3 , which is instructed by the controller 14 to ignore the received clock signal received at the clock input port 26 of compute node 12 - 3 .
- FIG. 3 is a flowchart 300 including steps in a method of operation of the controller 14 of the system 10 of FIG. 1 .
- the controller 14 is configured to run a software daemon which knows the topology of the system 10 (i.e., how the compute nodes 12 are connected in the closed loop) and which compute node 12 is the master clock (e.g., SyncE master) so that the software daemon knows where to block and unblock the closed loop. If the compute nodes 12 are disposed in different hosts, then the hosts may need to communicate with respect to blocking and unblocking the closed loop.
- a software daemon which knows the topology of the system 10 (i.e., how the compute nodes 12 are connected in the closed loop) and which compute node 12 is the master clock (e.g., SyncE master) so that the software daemon knows where to block and unblock the closed loop. If the compute nodes 12 are disposed in different hosts, then the hosts may need to communicate with respect to blocking and unblocking the closed loop.
- the controller 14 is configured to identify or designate one of the compute nodes 12 as the master clock (block 302 ).
- the controller 14 is configured to selectively block and unblock distribution of the master clock frequency in the closed loop responsively to one of the compute nodes 12 being designated as a master clock (block 304 ).
- the controller 14 is configured to instruct the clock synchronization circuitry 20 of the compute node 12 designated as the master clock to ignore the clock signal received at its clock input port 26 responsively to that compute node 12 being designated as the master clock (block 306 ).
- the controller 14 is configured to instruct the clock synchronization circuitry 20 of the compute node 12 (designated as a slave clock prior and) located immediately prior to the compute node 12 designated as the master clock in the closed loop to not send its local clock signal via its clock output port 28 to the compute node 12 designated as the master clock (block 308 ).
- controller 14 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. In some embodiments, at least some of the functions of the controller 14 may be carried out by a programmable processor under the control of suitable software. This software may be downloaded to a device in electronic form, over a network, for example. Alternatively, or additionally, the software may be stored in tangible, non-transitory computer-readable storage media, such as optical, magnetic, or electronic memory.
- FIG. 4 is a flowchart 400 including steps in a method of operation of the clock synchronization circuitry 20 in one of the compute nodes 12 (e.g., compute node 12 - 3 ) in the system 10 of FIG. 1 .
- the flowchart 400 is first traversed assuming that the compute node 12 - 3 is designated as a slave clock.
- the clock synchronization circuitry 20 of the compute node 12 - 3 is configured to generate a local clock signal responsively to an output from the oscillator 24 (block 402 ).
- the clock synchronization circuitry 20 of the compute node 12 - 3 is configured to recover a remote clock, e.g., from the remote clock 32 (block 404 ).
- the step of block 404 may include the clock synchronization circuitry 20 being configured to process respective communication signal(s) received by the respective port(s) 18 so as to recover a respective remote clock (block 406 ).
- the clock synchronization circuitry 20 of the compute node 12 - 3 is configured to receive a clock signal via the clock input port 26 of the compute node 12 - 3 (block 408 ) from the previous compute node 12 - 2 in the closed loop.
- the clock synchronization circuitry 20 of the compute node 12 - 3 is configured to discipline its local clock signal to the master clock frequency responsively to the received clock signal (block 410 ).
- the clock synchronization circuitry 20 of the compute node 12 - 3 is configured to output the disciplined local clock signal via the clock output port 28 of the compute node 12 - 3 to the next compute node 12 - 1 in the closed loop (block 412 ).
- the flowchart 400 is now traversed assuming that the compute node 12 - 3 is now designated as a master clock.
- One or more of the steps of blocks 402 - 408 may be performed. If a clock signal is received by the clock synchronization circuitry 20 of the compute node 12 - 3 via the clock input port 26 of compute node 12 - 3 , the clock synchronization circuitry 20 of the compute node 12 - 3 is configured to ignore the clock signal received by the clock input port 26 (block 414 ). The clock synchronization circuitry 20 of compute node 12 - 3 is configured to discipline the local clock signal of compute node 12 - 3 to the master clock frequency responsively to the recovered remote clock (recovered in the step of blocks 404 and/or 406 ) (block 416 ). The clock synchronization circuitry 20 of the compute node 12 - 3 is then configured to perform the step of block 412 .
- the functions of the clock synchronization circuitry 20 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. In some embodiments, at least some of the functions of the clock synchronization circuitry 20 may be carried out by a programmable processor under the control of suitable software. This software may be downloaded to a device in electronic form, over a network, for example. Alternatively, or additionally, the software may be stored in tangible, non-transitory computer-readable storage media, such as optical, magnetic, or electronic memory.
- FIG. 5 is a block diagram view of a clock synchronization system 500 with two compute nodes 12 constructed and operative in accordance with an alternative embodiment of the present invention.
- the clock synchronization system 500 is substantially the same as the system 10 except that in the clock synchronization system 500 there are only two computes node 12 .
- the clock synchronization system 500 may be compared to combining compute nodes 12 - 1 , 12 - 3 of system 10 into the same compute node 12 - 1 , which is in a closed loop with the compute node 12 - 2 .
- the clock output port 28 of compute node 12 - 1 is connected to the clock input port 26 of compute node 12 - 2 via one of the clock connections 30
- the clock output port 28 of compute node 12 - 2 is connected to the clock input port 26 of compute node 12 - 1 via one of the clock connections 30 thereby forming the closed loop.
- the compute node 12 may include any one or more of the following: a data processing unit (DPU) 600 , a graphics processing unit (GPU) 602 , a switch 604 , or a network interface controller (NIC) 606 .
- DPU data processing unit
- GPU graphics processing unit
- NIC network interface controller
- GPUs Graphics processing units
- graphics objects are employed to generate three-dimensional (3D) graphics objects and two-dimensional (2D) graphics objects for a variety of applications, including feature films, computer games, virtual reality (VR) and augmented reality (AR) experiences, mechanical design, and/or the like.
- a modern GPU includes texture processing hardware to generate the surface appearance, referred to herein as the “surface texture,” for 3D objects in a 3D graphics scene.
- the texture processing hardware applies the surface appearance to a 3D object by “wrapping” the appropriate surface texture around the 3D object. This process of generating and applying surface textures to 3D objects results in a highly realistic appearance for those 3D objects in the 3D graphics scene.
- the texture processing hardware is configured to perform a variety of texture-related instructions, including texture operations and texture loads.
- the texture processing hardware generates accesses texture information by generating memory references, referred to herein as “queries,” to a texture memory.
- the texture processing hardware retrieves surface texture information from the texture memory under varying circumstances, such as while rendering object surfaces in a 3D graphics scene for display on a display device, while rendering 2D graphics scene, or during compute operations.
- Textels used to texture or shade object surfaces in a 3D graphics scene.
- the texture processing hardware and associated texture cache are optimized for efficient, high throughput read-only access to support the high demand for texture information during graphics rendering, with little or no support for write operations.
- the texture processing hardware includes specialized functional units to perform various texture operations, such as level of detail (LOD) computation, texture sampling, and texture filtering.
- LOD level of detail
- a texture operation involves querying multiple texels around a particular point of interest in 3D space, and then performing various filtering and interpolation operations to determine a final color at the point of interest.
- a texture load typically queries a single texel, and returns that directly to the user application for further processing.
- filtering and interpolating operations typically involve querying four or more texels per processing thread
- the texture processing hardware is conventionally built to accommodate generating multiple queries per thread. For example, the texture processing hardware could be built to accommodate up to four texture memory queries is performed in a single memory cycle. In that manner, the texture processing hardware is able to query and receive most or all of the needed texture information in one memory cycle.
Abstract
In one embodiment, a synchronized communication system includes a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
Description
- The present invention relates to computer systems, and in particular, but not exclusively to, clock synchronization.
- Clock and frequency synchronization among network devices is used in many network applications. One application of using a synchronized clock value is for measuring latency between two devices. If the clocks are not synchronized the resulting latency measurement will be inaccurate.
- Synchronous Ethernet (SyncE) is an International Telecommunication Union Telecommunication (ITU-T) Standardization Sector standard for computer networking that facilitates the transference of clock signals over the Ethernet physical layer. In particular, SyncE enables clock synchronization inside a network with respect to a master clock. Each network element (e.g., a switch, a network interface card (MC), or router) needs to recover the master clock from high-speed data received from the master device clock source and use the recovered master clock for its own data transmission in a manner such that the master clock spreads throughout the network. SyncE provides synchronization with respect to clock frequency. The actual clock value (e.g., in Coordinated Universal Time (UTC) fomiat) is handled by higher layer standards and protocols, such as Precision Time Protocol (PTP).
- Time, clock and frequency synchronization is crucial in some of the modern computer network applications. It enables 5G and 6G networks, and is proven to enhance the performance of data center workloads. The SyncE standard allows improving Precision Time Protocol (PTP) accuracy by having less accumulated drift between PTP messages, and helps achieve an accurate time solution for an extended period after completely losing a PTP source.
- There is also provided in accordance with still another embodiment of the present disclosure, a synchronized communication system, including a plurality of compute nodes, and clock connections to connect the compute nodes in a closed loop configuration, wherein the compute nodes are configured to distribute among the compute nodes a master clock frequency from any selected one of the compute nodes.
- Further in accordance with an embodiment of the present disclosure, the system includes a controller to selectively block and unblock distribution of the master clock frequency in the closed loop responsively to one of the compute nodes being designated as a master clock.
- Still further in accordance with an embodiment of the present disclosure the compute nodes include at least one of the following a data processing unit (DPU), graphics processing unit (GPU), switch, network interface controller.
- Additionally in accordance with an embodiment of the present disclosure each of the compute nodes includes one or more ports to transmit and receive respective communication signals over respective network links, and clock synchronization circuitry to process at least one of the respective communication signals received by the one or more ports so as to recover a respective remote clock.
- Moreover in accordance with an embodiment of the present disclosure each of the compute nodes includes clock synchronization circuitry to recover a remote clock, a clock input port connected to another clock output port of a first one of the compute nodes via a first one of the clock connections, and configured to receive a clock signal at the master clock frequency from the first compute node, and a clock output port connected to another clock input port of a second one of the compute nodes via a second one of the clock connections.
- Further in accordance with an embodiment of the present disclosure the first compute node and the second compute node are a same one of the compute nodes.
- Still further in accordance with an embodiment of the present disclosure the clock synchronization circuitry is configured to discipline a local clock signal to the master clock frequency responsively to the recovered respective remote clock, or the received clock signal, and output the disciplined local clock signal via the clock output port to the second compute node.
- Additionally in accordance with an embodiment of the present disclosure the clock synchronization circuitry includes a frequency synthesizer.
- Moreover, in accordance with an embodiment of the present disclosure the frequency synthesizer is a frequency jitter synchronizer.
- Further in accordance with an embodiment of the present disclosure the frequency synthesizer is a jitter network synchronizer clock.
- Still further in accordance with an embodiment of the present disclosure the clock synchronization circuitry is configured to discipline a local clock signal to the master clock frequency responsively to the recovered respective remote clock, and output the disciplined local clock signal via the clock output port to the second compute node.
- Additionally in accordance with an embodiment of the present disclosure the clock synchronization circuitry is configured to ignore the clock signal received by the clock input port.
- Moreover, in accordance with an embodiment of the present disclosure, the system includes a controller to selectively block distribution of the master clock frequency in the closed loop by instructing the clock synchronization circuitry to ignore the clock signal received by the clock input port responsively to one of the compute nodes being designated as a master clock.
- Further in accordance with an embodiment of the present disclosure the clock synchronization circuitry is configured to discipline a local clock signal to the master clock frequency responsively to the received clock signal, and output the disciplined local clock signal via the clock output port to the second compute node.
- Still further in accordance with an embodiment of the present disclosure the compute nodes are configured to distribute the master clock frequency via respective ones of the clock connections using at least one of a one pulse per second (PPS) signal, or a 10 mega. Hertz (10MHz) signal.
- There is also provided in accordance with still another embodiment of the present disclosure, a synchronized communication method, including connecting compute nodes with clock connections in a closed loop configuration, and distributing among the compute nodes a master clock frequency from any selected one of the compute nodes.
- Additionally in accordance with an embodiment of the present disclosure, the method includes selectively blocking and unblocking distribution of the master clock frequency in the closed loop responsively to one of the compute nodes being designated as a master clock.
- Moreover, in accordance with an embodiment of the present disclosure the compute nodes include at least one of the following a data processing unit (DPU), graphics processing unit (GPU), switch, network interface controller.
- Further in accordance with an embodiment of the present disclosure, the method includes recovering a remote clock, connecting a clock input port to another clock output port of a first one of the compute nodes via a first one of the clock connections, receiving a clock signal at the master clock frequency from the first compute node, and connecting a clock output port to another clock input port of a second one of the compute nodes via a second one of the clock connections.
- Still further in accordance with an embodiment of the present disclosure the first compute node and the second compute node are a same one of the compute nodes.
- Additionally in accordance with an embodiment of the present disclosure, the method includes disciplining a local clock signal to the master clock frequency responsively to the recovered respective remote clock, or the received clock signal, and outputting the disciplined local clock signal via the clock output port to the second compute node.
- Moreover, in accordance with an embodiment of the present disclosure, the method includes disciplining a local clock signal to the master clock frequency responsively to the recovered respective remote clock, and outputting the disciplined local clock signal via the clock output port to the second compute node.
- Further in accordance with an embodiment of the present disclosure, the method includes ignoring the clock signal received by the clock input port.
- Still further in accordance with an embodiment of the present disclosure, the method includes selectively blocking distribution of the master clock frequency in the closed loop by instructing clock synchronization circuitry to ignore the clock signal received by the clock input port responsively to one of the compute nodes being designated as a master clock.
- Additionally in accordance with an embodiment of the present disclosure, the method includes disciplining a local clock signal to the master clock frequency responsively to the received clock signal, and outputting the disciplined local clock signal via the clock output port to the second compute node.
- Moreover, in accordance with an embodiment of the present disclosure, the method includes distributing the master clock frequency via respective ones of the clock connections using at least one of a one pulse per second (PPS) signal, or a 10 mega Hertz (10 MHz) signal.
- The present invention will be understood from the following detailed description, taken in conjunction with the drawings in which:
-
FIG. 1 is a block diagram view of a clock synchronization system with one compute node designated as a master clock constructed and operative in accordance with an embodiment of the present invention; -
FIG. 2 is a block diagram view of the clock synchronization system ofFIG. 1 with another compute node designated as the master clock; -
FIG. 3 is a flowchart including steps in a method of operation of a controller of the system ofFIG. 1 ; -
FIG. 4 is a flowchart including steps in a method of operation of clock synchronization circuitry in a compute node in the system ofFIG. 1 ; -
FIG. 5 is a block diagram view of a clock synchronization system with two compute nodes constructed and operative in accordance with an alternative embodiment of the present invention; and -
FIG. 6 is a more detailed block diagram view of a compute node in the system ofFIG. 1 . - Clock synchronization between compute nodes remains an unsolved challenge in the networking industry. One solution is to use SyncE clock chaining by chaining multiple SyncE capable devices together so that the master clock is distributed from one compute node at the root of the chain to other compute nodes in the chain. The root is defined by wiring topology.
- SyncE clock chaining may have some limitations including imposing a local clock hierarchy that is dictated by the physical wiring, introducing a possible “single point of failure” since the root controls the frequency of the entire chain. For example, if the compute node at the root malfunctions, it then becomes impossible to distribute the clock among the remaining compute nodes. Therefore, if the master clock moves to another of the compute nodes, the master clock cannot be distributed based on the physical wiring.
- One solution to the above problems is to transfer information regarding frequency differences between the root and the new master clock via some centralized entity, such as a SyncE software daemon running on a central processing unit (CPU). However, this solution adds complexity to the software—hardware/firmware interfaces, and to the software itself, and may add inaccuracies to the timing solution due to latencies and jitter of the control messages exchanged between the devices and the managing software. Additionally, this solution may add CPU load due to exchanging messages and performing calculations. It should be noted that CPU utilization is extremely important in 5G use cases where SyncE is commonly required.
- Embodiments of the present invention, solve at least some of the above problems by connecting compute nodes using clock connections to connect the compute nodes in a closed loop configuration. For example, compute node 1 is connected to compute node 2, which is connected to compute node 3, which is connected to compute node 1, forming a closed loop. The closed loop may then be used to distribute a master clock frequency among the compute nodes from any selected one of the compute nodes in the closed loop by passing the master clock frequency from compute node to compute node in the closed loop. For example, if one of the compute nodes is designated as a master clock, the master clock frequency is distributed from the compute node designated as the master clock to the other compute nodes via the clock connections of the closed loop. If at a later time another one of the compute nodes is designated as the master clock (for example, due to the previous compute node designated as a master malfunctioning), the master clock frequency is distributed from the compute node of the newly designated master clock to the other compute nodes via the clock connections of the closed loop. Therefore, if one of the compute nodes malfunctions, it is still possible to operate another one of the compute nodes to distribute the master clock frequency.
- In some embodiments, a clock output port of one compute node is connected to the clock input port of another compute node with a cable or other connection (e.g., a trace on a circuit board), and so on, until all the compute nodes are connected together in a closed loop. For example, the clock output port of node 1 is connected to the clock input port of node 2, and so on. The clock output port of node 3 is connected to the clock input port of node 1, thereby completing the loop. Upon detecting a clock signal at its clock input port, a compute node in the closed loop uses the received clock signal to discipline its local clock signal. The received clock signal may then be output via the clock output port of that compute node to the next compute node in the chain, and so on.
- In some embodiments, the compute node designated as the master clock should not use a clock signal received from another compute node to discipline its local clock signal. Instead, the compute node designated as the master clock disciplines its local clock signal from a recovered remote clock. It is this recovered remote clock which is distributed around the loop to the other compute nodes. In some embodiments, software or firmware running on a controller breaks the chain of the closed loop so that the compute node designated as the master clock does not use a clock signal received via its clock input port. Therefore, software or firmware may instruct the compute node designated as the master clock to ignore the received clock signal at its clock input port and by default use the recovered remote clock to discipline its local clock signal. In other embodiments, software or firmware running on a controller breaks the chain of the closed loop so that the compute node designated as the master clock does not receive a clock signal via its clock input port. Therefore, in some embodiments, the software or firmware running on the controller may instruct the compute node, which would otherwise pass its clock via its clock output port to the compute node of the designated master clock, to not output a clock signal to the compute node of the designated master clock.
- Each of the compute nodes may include clock synchronization circuitry which performs at least some of the following: recovering a remote clock and disciplining a local clock signal based on the recovered remote clock, receiving the clock signal via the chain, discipling the local clock signal based on the received clock signal, and passing the local clock signal to the next compute node in the chain. The clock synchronization circuitry may include a frequency jitter synchronizer, for example, a low or ultra-low frequency jitter synchronizer. An example of a suitable frequency synthesizer is Ultra-Low Jitter Network Synchronizer Clock LMK05318 commercially available from Texas Instruments Inc., 12500 TI Boulevard Dallas, Tex. 75243 USA.
- Reference is now made to
FIG. 1 , which is a block diagram view of aclock synchronization system 10 with one compute node 12-2 designated as a master clock constructed and operative in accordance with an embodiment of the present invention. Thesystem 10 includes a plurality of compute nodes 12 (labeled compute nodes 12-1, 12-2, 12-3), and acontroller 14. Eachcompute node 12 may include processingcircuitry 16, one ormore ports 18, clock synchronization circuitry 20 (which optionally includes a frequency synchronizer 22), anoscillator 24, aclock input port 26, and aclock output port 28. - A plurality of
clock connections 30 are configured to connect thecompute nodes 12 in a closed loop configuration. For example, compute node 12-1 is connected to compute node 12-2, which is connected to compute node 12-3, which in turn is connected to compute node 12-1 via theclock connections 30 as described in more detail below. -
FIG. 1 shows threecompute nodes 12 connected together in a closed loop configuration. Thesystem 10 may include twocompute nodes 12 connected together in a closed loop configuration, described in more detail with reference toFIG. 5 . Thesystem 10 may include more than threecompute nodes 12 connected together in a closed loop configuration. Thecompute nodes 12 may be disposed on the same printed circuit board (not shown) with theclock connections 30 being implemented using printed circuit board (PCB) traces (not shown) on the circuit board between thecompute nodes 12. - The
processing circuitry 16 may include hardwired processing circuitry and/or one or more processors on which to execute software. The software may be downloaded to thecompute node 12 or disposed on thecompute node 12 at manufacture. Theprocessing circuitry 16 may include packet processing circuitry which may include a physical layer (PHY) chip and MAC chip (not shown). Theprocessing circuitry 16 may include switching circuitry, and/or a data processing unit (DPU) and/or graphics processing unit (GPU) or any suitable processor, described in more detail with reference toFIG. 6 . - The port(s) 18 are configured to transmit and receive respective communication signals over respective network links, for example, to receive a clock synchronization signal or clock synchronization packets from a
remote clock 32. The clock synchronization signal or clock synchronization packets may be received via any suitable interface via any suitable communication method and protocol. - The
clock input port 26 of one of the compute nodes 12 (e.g., compute node 12-1) is connected to theclock output port 28 of another one of the compute nodes 12 (e.g., compute node 12-3) via one of theclock connections 30, and configured to receive a clock signal at the master clock frequency from the other compute node 12 (e.g., compute node 12-3). Theclock output port 28 of one of the compute nodes 12 (e.g., compute node 12-1) is connected to theclock input port 26 of another one of the compute nodes 12 (e.g., compute node 12-2) via one of theclock connections 30. Theclock output port 28 of the compute node 12-2 is connected to theclock input port 26 of the compute node 12-3 via one of theclock connections 30. - In general, the
compute nodes 12 are configured to distribute among the compute nodes 12 a master clock frequency from any selected one of the compute nodes, for example, the computer node 12-2 designated as the master clock. - In the example of
FIG. 1 , the compute node 12-2 disciplines its local clock signal from theremote clock 32 and is designated as the master clock, for example by thecontroller 14. The compute node 12-2 distributes its local clock signal as the master clock frequency via theclock output port 28 of compute node 12-2 to theclock input port 26 of compute node 12-3. The compute node 12-3 disciplines its local clock signal responsively to the received clock signal received at theclock input port 26 of compute node 12-3. The compute node 12-3 distributes its local clock signal as the master clock frequency via theclock output port 28 of compute node 12-3 to theclock input port 26 of compute node 12-1. The compute node 12-1 disciplines its local clock signal responsively to the received clock signal received at theclock input port 26 of compute node 12-1. In some embodiments, the compute node 12-1 is instructed by thecontroller 14 not to distribute its local clock signal via theclock output port 28 of compute node 12-1. In other embodiments, the compute node 12-1 distributes its local clock signal as the master clock frequency via theclock output port 28 of compute node 12-1 to theclock input port 26 of compute node 12-2, which is instructed by thecontroller 14 to ignore the received clock signal received at theclock input port 26 of compute node 12-2. - The
compute nodes 12 may be configured to distribute the master clock frequency viarespective clock connections 30 in the form of any signal which is scaled proportional to master clock frequency using one pulse per second (PPS) signal(s) or 10 mega Hertz (10 MHz) signal(s). The scaling factor may be used by theclock synchronization circuitry 20 of the outputtingcompute node 12 to scale the master clock frequency to one PPS or 10 MHz, for example, and by theclock synchronization circuitry 20 of the receivingcompute node 12 to rebuild the received signal (e.g., one PPS or 10 MHz) to the master clock frequency. - In some embodiments, the
frequency synchronizer 22 is a frequency jitter synchronizer or a jitter network synchronizer clock. Thefrequency synchronizer 22 may be configured to tune a network frequency, feed the clock of thecompute node 12, and provide phase lock loop (PLL) capabilities. In some embodiments, thefrequency synchronizer 22 include an application-specific integrated circuit (ASIC) and/or a programmable device with analog circuitry mainly for phase lock loop (PLL) capabilities. Thefrequency synchronizer 22 may be a low or ultra-low frequency jitter synchronizer. An example of a suitable frequency synthesizer is Ultra-Low Jitter Network Synchronizer Clock LMK05318 commercially available from Texas Instruments Inc., 12500 TI Boulevard, Dallas, Tex. 75243 USA. - In the compute node 12-2 designated as the master clock, the
frequency synchronizer 22 adjusts the output of theoscillator 24 to provide a local clock signal based on a clock recovered from theremote clock 32. In the compute node(s) 12-1, 12-3 not designated as the master clock, the clock signal received at theclock input port 26 is used by thefrequency synchronizer 22 to drive the local clock signal, generally without using the output of theoscillator 24. - In some embodiments, the
frequency synchronizer 22 is configured to use the clock signal received at theclock input port 26 if such a clock signal is received. If not, thefrequency synchronizer 22 disciplines the local clock signal based on the output of theoscillator 24 and/or a recovered remote clock. Therefore, in some embodiments, software or firmware running on thecontroller 14 breaks the chain of the closed loop so that the compute node 12-2 designated as the master clock does not use a clock signal received at itsclock input port 26 or does not receive a clock signal at itsclock input port 26, as described in more detail with reference toFIG. 3 . - When the
compute nodes 12 boot up, each computenode 12 looks for a clock signal being received at its ownclock input port 26 and if a clock signal is not found, therespective compute node 12 uses a local clock, for example, based on an output of theoscillator 24 in thatcompute node 12. Therefore, thefirst compute node 12 to boot up outputs a clock signal based on a local clock from itsclock output port 28 to thenext compute node 12 in the closed loop. Thenext compute node 12 then detects the clock signal input via itsclock input port 26 and uses the received clock signal to discipline its local clock signal, and so on. When one of thecompute nodes 12 is designated as a master clock, that computenode 12 does not use the clock signal received at itsclock input port 26, but disciplines its local clock signal based on theremote clock 32 and outputs its local clock signal via itsclock output port 28 to thenext compute node 12 in the loop, and so on. Another option is to assign one of thecompute nodes 12 as a default master clock. - Reference is now made to
FIG. 2 , which is a block diagram view of the clock synchronization system ofFIG. 1 with compute node 12-3 designated as the master clock. The master clock may be moved from onecompute node 12 to another due to many reasons, for example, theremote clock 32 used by one of thecompute nodes 12 previously designated as the master clock may now be non-functional or deemed to be less accurate than a remote clock used by another one of thecompute nodes 12 now designated as the master clock. - In the example of
FIG. 2 , the compute node 12-3 is now designated as the master clock (for example, by the controller 14), and disciplines its local clock signal from theremote clock 32. The compute node 12-3 may: ignore any clock signal received at itsclock input port 26; or thecontroller 14 may instruct the compute node 12-2 to cease outputting the local clock signal of compute node 12-2 via theclock output port 28 of compute node 12-2. The compute node 12-3 distributes its local clock signal as the master clock frequency via theclock output port 28 of compute node 12-3 to theclock input port 26 of the compute node 12-1. The compute node 12-1 disciplines its local clock signal responsively to the received clock signal received at theclock input port 26 of compute node 12-1. The compute node 12-1 distributes its local clock signal as the master clock frequency via theclock output port 28 of compute node 12-1 to theclock input port 26 of compute node 12-2. The compute node 12-2 disciplines its local clock signal responsively to the received clock signal received at theclock input port 26 of compute node 12-2. As mentioned above, in some embodiments, the compute node 12-2 is instructed by thecontroller 14 not to distribute its local clock signal via theclock output port 28 of compute node 12-2. In other embodiments, the compute node 12-2 distributes its local clock signal as the master clock frequency via theclock output port 28 of compute node 12-2 to theclock input port 26 of compute node 12-3, which is instructed by thecontroller 14 to ignore the received clock signal received at theclock input port 26 of compute node 12-3. - Reference is now made to
FIG. 3 , which is aflowchart 300 including steps in a method of operation of thecontroller 14 of thesystem 10 ofFIG. 1 . - In some embodiments, the
controller 14 is configured to run a software daemon which knows the topology of the system 10 (i.e., how thecompute nodes 12 are connected in the closed loop) and which computenode 12 is the master clock (e.g., SyncE master) so that the software daemon knows where to block and unblock the closed loop. If thecompute nodes 12 are disposed in different hosts, then the hosts may need to communicate with respect to blocking and unblocking the closed loop. - The
controller 14 is configured to identify or designate one of thecompute nodes 12 as the master clock (block 302). Thecontroller 14 is configured to selectively block and unblock distribution of the master clock frequency in the closed loop responsively to one of thecompute nodes 12 being designated as a master clock (block 304). In some embodiments, thecontroller 14 is configured to instruct theclock synchronization circuitry 20 of thecompute node 12 designated as the master clock to ignore the clock signal received at itsclock input port 26 responsively to that computenode 12 being designated as the master clock (block 306). In other embodiments, thecontroller 14 is configured to instruct theclock synchronization circuitry 20 of the compute node 12 (designated as a slave clock prior and) located immediately prior to thecompute node 12 designated as the master clock in the closed loop to not send its local clock signal via itsclock output port 28 to thecompute node 12 designated as the master clock (block 308). - In practice, some or all of the functions of the
controller 14 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. In some embodiments, at least some of the functions of thecontroller 14 may be carried out by a programmable processor under the control of suitable software. This software may be downloaded to a device in electronic form, over a network, for example. Alternatively, or additionally, the software may be stored in tangible, non-transitory computer-readable storage media, such as optical, magnetic, or electronic memory. - Reference is now made to
FIG. 4 , which is aflowchart 400 including steps in a method of operation of theclock synchronization circuitry 20 in one of the compute nodes 12 (e.g., compute node 12-3) in thesystem 10 ofFIG. 1 . - The
flowchart 400 is first traversed assuming that the compute node 12-3 is designated as a slave clock. - When the compute node 12-3 first boots up, the
clock synchronization circuitry 20 of the compute node 12-3 is configured to generate a local clock signal responsively to an output from the oscillator 24 (block 402). After a short delay, assuming there is still no clock signal received by theclock input port 26 of the compute node 12-3, theclock synchronization circuitry 20 of the compute node 12-3 is configured to recover a remote clock, e.g., from the remote clock 32 (block 404). The step ofblock 404 may include theclock synchronization circuitry 20 being configured to process respective communication signal(s) received by the respective port(s) 18 so as to recover a respective remote clock (block 406). Theclock synchronization circuitry 20 of the compute node 12-3 is configured to receive a clock signal via theclock input port 26 of the compute node 12-3 (block 408) from the previous compute node 12-2 in the closed loop. Theclock synchronization circuitry 20 of the compute node 12-3 is configured to discipline its local clock signal to the master clock frequency responsively to the received clock signal (block 410). Theclock synchronization circuitry 20 of the compute node 12-3 is configured to output the disciplined local clock signal via theclock output port 28 of the compute node 12-3 to the next compute node 12-1 in the closed loop (block 412). - The
flowchart 400 is now traversed assuming that the compute node 12-3 is now designated as a master clock. - One or more of the steps of blocks 402-408 may be performed. If a clock signal is received by the
clock synchronization circuitry 20 of the compute node 12-3 via theclock input port 26 of compute node 12-3, theclock synchronization circuitry 20 of the compute node 12-3 is configured to ignore the clock signal received by the clock input port 26 (block 414). Theclock synchronization circuitry 20 of compute node 12-3 is configured to discipline the local clock signal of compute node 12-3 to the master clock frequency responsively to the recovered remote clock (recovered in the step ofblocks 404 and/or 406) (block 416). Theclock synchronization circuitry 20 of the compute node 12-3 is then configured to perform the step ofblock 412. - In practice, some or all of the functions of the
clock synchronization circuitry 20 may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. In some embodiments, at least some of the functions of theclock synchronization circuitry 20 may be carried out by a programmable processor under the control of suitable software. This software may be downloaded to a device in electronic form, over a network, for example. Alternatively, or additionally, the software may be stored in tangible, non-transitory computer-readable storage media, such as optical, magnetic, or electronic memory. - Reference is now made to
FIG. 5 , which is a block diagram view of aclock synchronization system 500 with twocompute nodes 12 constructed and operative in accordance with an alternative embodiment of the present invention. - The
clock synchronization system 500 is substantially the same as thesystem 10 except that in theclock synchronization system 500 there are only twocomputes node 12. Theclock synchronization system 500 may be compared to combining compute nodes 12-1, 12-3 ofsystem 10 into the same compute node 12-1, which is in a closed loop with the compute node 12-2. - In the
clock synchronization system 500, theclock output port 28 of compute node 12-1 is connected to theclock input port 26 of compute node 12-2 via one of theclock connections 30, and theclock output port 28 of compute node 12-2 is connected to theclock input port 26 of compute node 12-1 via one of theclock connections 30 thereby forming the closed loop. - Reference is now made to
FIG. 6 , which is a more detailed block diagram view of one of thecompute nodes 12 in thesystem 10 ofFIG. 1 . Thecompute node 12 may include any one or more of the following: a data processing unit (DPU) 600, a graphics processing unit (GPU) 602, a switch 604, or a network interface controller (NIC) 606. - Graphics processing units (GPUs) are employed to generate three-dimensional (3D) graphics objects and two-dimensional (2D) graphics objects for a variety of applications, including feature films, computer games, virtual reality (VR) and augmented reality (AR) experiences, mechanical design, and/or the like. A modern GPU includes texture processing hardware to generate the surface appearance, referred to herein as the “surface texture,” for 3D objects in a 3D graphics scene. The texture processing hardware applies the surface appearance to a 3D object by “wrapping” the appropriate surface texture around the 3D object. This process of generating and applying surface textures to 3D objects results in a highly realistic appearance for those 3D objects in the 3D graphics scene.
- The texture processing hardware is configured to perform a variety of texture-related instructions, including texture operations and texture loads. The texture processing hardware generates accesses texture information by generating memory references, referred to herein as “queries,” to a texture memory. The texture processing hardware retrieves surface texture information from the texture memory under varying circumstances, such as while rendering object surfaces in a 3D graphics scene for display on a display device, while rendering 2D graphics scene, or during compute operations.
- Surface texture information includes texture elements (referred to herein as “texels”) used to texture or shade object surfaces in a 3D graphics scene. The texture processing hardware and associated texture cache are optimized for efficient, high throughput read-only access to support the high demand for texture information during graphics rendering, with little or no support for write operations. Further, the texture processing hardware includes specialized functional units to perform various texture operations, such as level of detail (LOD) computation, texture sampling, and texture filtering.
- In general, a texture operation involves querying multiple texels around a particular point of interest in 3D space, and then performing various filtering and interpolation operations to determine a final color at the point of interest. By contrast, a texture load typically queries a single texel, and returns that directly to the user application for further processing. Because filtering and interpolating operations typically involve querying four or more texels per processing thread, the texture processing hardware is conventionally built to accommodate generating multiple queries per thread. For example, the texture processing hardware could be built to accommodate up to four texture memory queries is performed in a single memory cycle. In that manner, the texture processing hardware is able to query and receive most or all of the needed texture information in one memory cycle.
- Various features of the invention which are, for clarity, described in the contexts of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable sub-combination.
- The embodiments described above are cited by way of example, and the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the invention includes both combinations and sub-combinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.
Claims (26)
1. A synchronized communication system, comprising:
a plurality of compute nodes including a first compute node, one or more intermediate compute nodes, and a last compute node; and
clock connections to connect the compute nodes in a closed loop configuration, wherein:
each of the compute nodes has an output connected to an input of a next one of the compute nodes via a respective one of the clock connections, while the last compute node has an output connected to an input of the first compute node via another respective one of the clock connections;
the compute nodes are configured to distribute among the compute nodes, via ones of the clock connections, a master clock frequency from any selected one of the compute nodes, which is designated as a master clock;
at a first time one of the plurality of compute nodes is designated as the master clock and is configured to distribute the master clock frequency among the compute nodes; and
at a second time another one of the plurality of compute nodes is designated as the master clock, and is configured to distribute the master clock frequency among the compute nodes.
2. The system according to claim 1 , further comprising a controller to selectively block and unblock distribution of the master clock frequency in the closed loop responsively to one of the compute nodes being designated as a master clock.
3. The system according to claim 1 , wherein the compute nodes include at least one of the following: a data processing unit (DPU), graphics processing unit (GPU), switch, network interface controller.
4. The system according to claim 1 , wherein each of the compute nodes comprises:
one or more ports to transmit and receive respective communication signals over respective network links; and
clock synchronization circuitry to process at least one of the respective communication signals received by the one or more ports so as to recover a respective remote clock.
5. The system according to claim 1 , wherein the first compute node comprises:
clock synchronization circuitry to recover a remote clock;
a clock input port connected to a clock output port of a third compute node of the plurality of compute nodes via a first one of the clock connections, and configured to receive a clock signal at the master clock frequency from the third compute node; and
a clock output port connected to a clock input port of a the second compute node of the plurality of compute nodes via a second one of the clock connections.
6. The system according to claim 5 , wherein the third compute node and the second compute node are a same one of the compute nodes.
7. The system according to claim 5 , wherein the clock synchronization circuitry is configured to:
discipline a local clock signal to the master clock frequency responsively to: the recovered respective remote clock; or the received clock signal; and
output the disciplined local clock signal via the clock output port to the second compute node.
8. The system according to claim 7 , wherein the clock synchronization circuitry comprises a frequency synthesizer.
9. The system according to claim 8 , wherein the frequency synthesizer is a frequency jitter synchronizer.
10. The system according to claim 8 , wherein the frequency synthesizer is a jitter network synchronizer clock.
11. The system according to claim 5 , wherein the clock synchronization circuitry is configured to:
discipline a local clock signal to the master clock frequency responsively to the recovered respective remote clock; and
output the disciplined local clock signal via the clock output port to the second compute node.
12. The system according to claim 11 , wherein the clock synchronization circuitry is configured to ignore the clock signal received by the clock input port.
13. The system according to claim 12 , further comprising a controller to selectively block distribution of the master clock frequency in the closed loop by instructing the clock synchronization circuitry to ignore the clock signal received by the clock input port responsively to one of the compute nodes being designated as a master clock.
14. The system according to claim 5 , wherein the clock synchronization circuitry is configured to:
discipline a local clock signal to the master clock frequency responsively to the received clock signal; and
output the disciplined local clock signal via the clock output port to the second compute node.
15. The system according to claim 1 , wherein the compute nodes are configured to distribute the master clock frequency via respective ones of the clock connections using at least one of: a one pulse per second (PPS) signal; or a 10 mega Hertz (10 MHz) signal.
16. A synchronized communication method, comprising:
connecting compute nodes including a first compute node, one or more intermediate compute nodes, and a last compute node, with clock connections in a closed loop configuration so that each of the compute nodes has an output connected to an input of a next one of the compute nodes via a respective one of the clock connections, while the last compute node has an output connected to an input of the first compute node via another respective one of the clock connections;
distributing among the compute nodes, via ones of the clock connections, a master clock frequency from any selected one of the compute nodes, which is designated as a master clock;
at a first time, designating one of the plurality of compute nodes as the master clock and distributing the master clock frequency among the compute nodes; and
at a second time, designating another one of the plurality of compute nodes as the master clock, and distributing the master clock frequency among the compute nodes.
17. The method according to claim 16 , further comprising selectively blocking and unblocking distribution of the master clock frequency in the closed loop responsively to one of the compute nodes being designated as a master clock.
18. The method according to claim 16 , wherein the compute nodes include at least one of the following: a data processing unit (DPU), graphics processing unit (GPU), switch, network interface controller.
19. The method according to claim 16 , further comprising:
recovering a remote clock;
connecting a clock input port to a clock output port of a third compute node of the plurality of compute nodes via a first one of the clock connections;
receiving a clock signal at the master clock frequency from the third compute node; and
connecting a clock output port to a clock input port of a second compute node of the plurality of compute nodes via a second one of the clock connections.
20. The method according to claim 19 , wherein the third compute node and the second compute node are a same one of the compute nodes.
21. The method according to claim 19 , further comprising:
disciplining a local clock signal to the master clock frequency responsively to: the recovered respective remote clock; or the received clock signal; and
outputting the disciplined local clock signal via the clock output port to the second compute node.
22. The method according to claim 19 , further comprising:
disciplining a local clock signal to the master clock frequency responsively to the recovered respective remote clock; and
outputting the disciplined local clock signal via the clock output port to the second compute node.
23. The method according to claim 22 , further comprising ignoring the clock signal received by the clock input port.
24. The method according to claim 23 , further comprising selectively blocking distribution of the master clock frequency in the closed loop by instructing clock synchronization circuitry to ignore the clock signal received by the clock input port responsively to one of the compute nodes being designated as a master clock.
25. The method according to claim 19 , further comprising:
disciplining a local clock signal to the master clock frequency responsively to the received clock signal; and
outputting the disciplined local clock signal via the clock output port to the second compute node.
26. The method according to claim 16 , further comprising distributing the master clock frequency via respective ones of the clock connections using at least one of: a one pulse per second (PPS) signal; or a 10 mega Hertz (10 MHz) signal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/579,630 US11706014B1 (en) | 2022-01-20 | 2022-01-20 | Clock synchronization loop |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US17/579,630 US11706014B1 (en) | 2022-01-20 | 2022-01-20 | Clock synchronization loop |
Publications (2)
Publication Number | Publication Date |
---|---|
US11706014B1 US11706014B1 (en) | 2023-07-18 |
US20230231695A1 true US20230231695A1 (en) | 2023-07-20 |
Family
ID=87161302
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US17/579,630 Active US11706014B1 (en) | 2022-01-20 | 2022-01-20 | Clock synchronization loop |
Country Status (1)
Country | Link |
---|---|
US (1) | US11706014B1 (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020031199A1 (en) * | 2000-02-02 | 2002-03-14 | Rolston David Robert Cameron | Method and apparatus for distributed synchronous clocking |
US6718476B1 (en) * | 2000-11-27 | 2004-04-06 | Sony Corporation | Method of synchronizing each local clock to a master clock in a data bus system |
US10014937B1 (en) * | 2016-03-11 | 2018-07-03 | Juniper Networks, Inc. | Timing synchronization and intrusion detection via an optical supervisory channel (OSC) |
Family Cites Families (141)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3065052A (en) | 1957-08-27 | 1962-11-20 | Barium And Chemicals Inc | Purification of strontium nitrate |
SE466123B (en) | 1989-04-25 | 1991-12-16 | Kvaser Consultant Ab | DEVICE FOR SYNCONIZING DATA IN A COMPUTER SYSTEM INCLUDING A COMMON SERIAL DATA COMMUNICATION CHANNEL |
DE4140017C2 (en) | 1991-12-04 | 1995-01-05 | Nec Electronics Germany | Method for operating computer units communicating with one another via a data bus by serial data exchange |
CA2091962A1 (en) | 1992-03-31 | 1993-10-01 | Mark L. Witsaman | Clock synchronization system |
US5564285A (en) | 1994-09-22 | 1996-10-15 | Thermo King Corporation | Method of converting a time based data logger to a time and random event based data logger |
US5491792A (en) | 1994-09-23 | 1996-02-13 | Forney International, Inc. | Sequence of events system using a redundant analog I/O board system |
US5592486A (en) | 1995-03-17 | 1997-01-07 | Advanced Micro Devices, Inc. | System and method for efficiently monitoring information in a network having a plurality of repeaters |
GB2298951B (en) | 1995-03-17 | 1999-10-27 | Olivetti Res Ltd | Addition of time information |
US5896524A (en) | 1997-02-06 | 1999-04-20 | Digital Equipment Corporation | Off-line clock synchronization for multiprocessor event traces |
US6289023B1 (en) | 1997-09-25 | 2001-09-11 | Hewlett-Packard Company | Hardware checksum assist for network protocol stacks |
US6084856A (en) | 1997-12-18 | 2000-07-04 | Advanced Micro Devices, Inc. | Method and apparatus for adjusting overflow buffers and flow control watermark levels |
US6144714A (en) | 1998-01-06 | 2000-11-07 | Maker Communications, Inc. | Programmable fractional frequency digital frequency synthesizer for synchronous residual time stamp service clock regenerator phase locked loop |
US6199169B1 (en) | 1998-03-31 | 2001-03-06 | Compaq Computer Corporation | System and method for synchronizing time across a computer cluster |
US6449291B1 (en) | 1998-11-24 | 2002-09-10 | 3Com Corporation | Method and apparatus for time synchronization in a communication system |
US6556638B1 (en) | 1999-02-22 | 2003-04-29 | Godigital Networks Corporation | Method and apparatus for providing increased data speed using synchronization and bit robbing techniques |
US6535926B1 (en) | 1999-09-30 | 2003-03-18 | Rockwell Automation Technologies, Inc. | Time synchronization system for industrial control network using global reference pulses |
US6643787B1 (en) | 1999-10-19 | 2003-11-04 | Rambus Inc. | Bus system optimization |
US6807134B2 (en) | 1999-12-28 | 2004-10-19 | Matsushita Electric Industrial Co., Ltd. | Asymmetry detection apparatus, jitter detection apparatus, and recording/reproduction apparatus |
US7254116B2 (en) | 2000-04-07 | 2007-08-07 | Broadcom Corporation | Method and apparatus for transceiver noise reduction in a frame-based communications network |
US7023816B2 (en) | 2000-12-13 | 2006-04-04 | Safenet, Inc. | Method and system for time synchronization |
WO2002080440A1 (en) | 2001-03-29 | 2002-10-10 | Nokia Corporation | Method for synchronizing a first clock to a second clock, processing unit and synchronization system |
US7415609B1 (en) | 2001-04-23 | 2008-08-19 | Diebold, Incorporated | Automated banking machine system and method |
US7650158B2 (en) | 2001-08-21 | 2010-01-19 | Broadcom Corporation | System and method for synchronizing wireless communication devices |
US6918049B2 (en) | 2002-03-26 | 2005-07-12 | Semtech Corporation | Method and apparatus for controlling the phase of the clock output of a digital clock |
US7245627B2 (en) | 2002-04-23 | 2007-07-17 | Mellanox Technologies Ltd. | Sharing a network interface card among multiple hosts |
US7334124B2 (en) | 2002-07-22 | 2008-02-19 | Vormetric, Inc. | Logical access block processing protocol for transparent secure file storage |
US7111184B2 (en) | 2002-09-06 | 2006-09-19 | Freescale Semiconductor, Inc. | System and method for deterministic communication across clock domains |
US7447975B2 (en) | 2002-09-12 | 2008-11-04 | Hewlett-Packard Development Company, L.P. | Supporting cyclic redundancy checking for PCI-X |
US7209525B2 (en) | 2002-11-18 | 2007-04-24 | Agere Systems Inc. | Clock and data recovery with extended integration cycles |
US7076715B2 (en) | 2003-01-31 | 2006-07-11 | Rockwell Automation Technologies, Inc. | Safety network using phantom address information |
US7254646B2 (en) | 2003-06-23 | 2007-08-07 | Hewlett-Packard Development Company, L.P. | Analysis of causal relations between intercommunicating nodes |
US7340630B2 (en) | 2003-08-08 | 2008-03-04 | Hewlett-Packard Development Company, L.P. | Multiprocessor system with interactive synchronization of local clocks |
US7483448B2 (en) | 2004-03-10 | 2009-01-27 | Alcatel-Lucent Usa Inc. | Method and system for the clock synchronization of network terminals |
US7412475B1 (en) | 2004-03-23 | 2008-08-12 | Sun Microsystems, Inc. | Error detecting arithmetic circuits using hexadecimal digital roots |
US20050268183A1 (en) | 2004-05-25 | 2005-12-01 | Barmettler Mark G | Local area network measurement test device |
US7403547B2 (en) | 2004-07-15 | 2008-07-22 | Arris International, Inc. | Method and system for synchronizing separated edge QAM devices located remotely from a CMTS |
US7440474B1 (en) | 2004-09-15 | 2008-10-21 | Avaya Inc. | Method and apparatus for synchronizing clocks on packet-switched networks |
US7623552B2 (en) | 2004-10-14 | 2009-11-24 | Temic Automotive Of North America, Inc. | System and method for time synchronizing nodes in an automotive network using input capture |
US7983769B2 (en) | 2004-11-23 | 2011-07-19 | Rockwell Automation Technologies, Inc. | Time stamped motion control network protocol that enables balanced single cycle timing and utilization of dynamic data structures |
US7496686B2 (en) | 2005-01-28 | 2009-02-24 | Gencsus | Localizing a remote event timestamp from a network device with an independent clock method and apparatus |
US7750685B1 (en) | 2005-03-17 | 2010-07-06 | Rf Micro Devices, Inc. | Frequency measurement based frequency locked loop synthesizer |
JP2007017158A (en) | 2005-07-05 | 2007-01-25 | Sharp Corp | Test circuit, delay circuit, clock generating circuit, and image sensor |
JP4624898B2 (en) | 2005-09-28 | 2011-02-02 | 富士通株式会社 | Optical transmission equipment |
EP1772795A1 (en) | 2005-10-10 | 2007-04-11 | STMicroelectronics (Research & Development) Limited | Fast buffer pointer across clock |
JP2007134928A (en) | 2005-11-10 | 2007-05-31 | Renesas Technology Corp | Rf analog signal processing unit and mobile terminal device with mounted signal processing unit |
US7636767B2 (en) | 2005-11-29 | 2009-12-22 | Cisco Technology, Inc. | Method and apparatus for reducing network traffic over low bandwidth links |
US7447931B1 (en) | 2005-12-09 | 2008-11-04 | Rockwell Automation Technologies, Inc. | Step time change compensation in an industrial automation network |
US7558156B2 (en) | 2006-01-06 | 2009-07-07 | Agilent Technologies, Inc. | Acoustic location and enhancement |
US7487229B2 (en) | 2006-03-30 | 2009-02-03 | Intel Corporation | Methods and apparatus to synchronize local times at nodes in a computer network |
US20080069150A1 (en) | 2006-09-19 | 2008-03-20 | Sig Harold Badt | Precision Time Protocol Emulation for Network Supportive of Circuit Emulation Services |
US8341454B1 (en) | 2007-12-28 | 2012-12-25 | Marvell International Ltd. | Rendering a video stream based on digital clock generated based on timing information |
US7941684B2 (en) | 2008-02-28 | 2011-05-10 | Advanced Micro Devices, Inc. | Synchronization of processor time stamp counters to master counter |
JP5223427B2 (en) | 2008-04-09 | 2013-06-26 | 日本電気株式会社 | Clock synchronization system |
US8467418B2 (en) | 2008-11-10 | 2013-06-18 | Rockstar Consortium Us Lp | Differential timing transfer over synchronous ethernet using digital frequency generators and control word signaling |
US8370675B2 (en) | 2009-01-28 | 2013-02-05 | Mellanox Technologies Ltd. | Precise clock synchronization |
US20100280858A1 (en) | 2009-04-30 | 2010-11-04 | Embarq Holdings Company, Llc | System and method for a small form pluggable ethernet demarcation device |
US8953581B1 (en) | 2009-05-13 | 2015-02-10 | Dust Networks, Inc. | Timing synchronization for wireless networks |
US8407478B2 (en) | 2009-07-07 | 2013-03-26 | Mellanox Technologies Ltd. | Control message signature for device control |
JP5429867B2 (en) | 2009-10-23 | 2014-02-26 | Necインフロンティア株式会社 | Communication apparatus and network synchronization method |
US8649271B2 (en) | 2010-01-25 | 2014-02-11 | Ixia | Testing network equipment |
US8797880B2 (en) | 2010-02-09 | 2014-08-05 | Juniper Networks, Inc. | Remote network device component testing |
EP2408128B1 (en) | 2010-07-15 | 2017-06-07 | Alcatel Lucent | Interworking agent adapted to interact between network and Precision Time Protocol entities |
US8615091B2 (en) | 2010-09-23 | 2013-12-24 | Bose Corporation | System for accomplishing bi-directional audio data and control communications |
US8935511B2 (en) | 2010-10-11 | 2015-01-13 | International Business Machines Corporation | Determining processor offsets to synchronize processor time values |
US9025490B2 (en) | 2011-01-17 | 2015-05-05 | Shahram Davari | Network device |
US8930647B1 (en) | 2011-04-06 | 2015-01-06 | P4tents1, LLC | Multiple class memory systems |
US9331805B2 (en) | 2011-05-06 | 2016-05-03 | Fts Computertechnik Gmbh | Network and method for implementing a high-availability grand master clock |
US8989589B2 (en) | 2011-08-18 | 2015-03-24 | Cisco Technology, Inc. | Method and apparatus for testing using a transceiver module |
US8904216B2 (en) | 2011-09-02 | 2014-12-02 | Iota Computing, Inc. | Massively multicore processor and operating system to manage strands in hardware |
CN103051406B (en) | 2011-10-17 | 2017-02-08 | 中兴通讯股份有限公司 | Clock synchronization method and system in 1588-2008 protocol |
US9397960B2 (en) | 2011-11-08 | 2016-07-19 | Mellanox Technologies Ltd. | Packet steering |
US8879552B2 (en) | 2012-02-22 | 2014-11-04 | Telefonaktiebolaget L M Ericsson (Publ) | Precision time protocol offloading in a PTP boundary clock |
WO2013137863A1 (en) | 2012-03-13 | 2013-09-19 | Rambus Inc. | Clock and data recovery having shared clock generator |
US9690674B2 (en) | 2012-03-30 | 2017-06-27 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and system for robust precision time protocol synchronization |
US8806284B2 (en) | 2012-05-02 | 2014-08-12 | Avalanche Technology Inc. | Method for bit-error rate testing of resistance-based RAM cells using a reflected signal |
US9130687B2 (en) | 2012-05-23 | 2015-09-08 | Anue Systems, Inc. | System and method for direct passive monitoring of packet delay variation and time error in network packet communications |
US8861664B2 (en) | 2012-06-15 | 2014-10-14 | Smsc Holdings S.A.R.L. | Communication system and method for synchronizing a plurality of network nodes after a network lock condition occurs |
KR101327221B1 (en) | 2012-07-06 | 2013-11-11 | 주식회사 실리콘웍스 | Clock generator, data receiver and recovering method for master clock |
EP2701318B1 (en) | 2012-08-22 | 2015-04-15 | Alcatel Lucent | A method for synchronizing distributed clocks by the precision time protocol, in a telecommunication network |
US9100167B2 (en) | 2012-11-30 | 2015-08-04 | Broadcom Corporation | Multilane SERDES clock and data skew alignment for multi-standard support |
US9549234B1 (en) | 2012-12-28 | 2017-01-17 | Enginuity Communications Corporation | Methods and apparatuses for implementing a layer 3 internet protocol (IP) echo response function on a small form-factor pluggable (SFP) transceiver and providing a universal interface between an SFP transceiver and network equipment |
CN103901955A (en) | 2012-12-28 | 2014-07-02 | 鸿富锦精密工业(深圳)有限公司 | Fastening structure and keyboard plate combination with same |
US9071234B2 (en) | 2013-03-07 | 2015-06-30 | Raytheon Company | High-resolution link-path delay estimator and method for estimating a signal-path delay |
US9450854B2 (en) | 2013-03-14 | 2016-09-20 | Exfo Inc. | Pass-through test device |
US20140281036A1 (en) | 2013-03-14 | 2014-09-18 | Silicon Graphics International Corp. | Synchronizing Scheduler Interrupts Across Multiple Computing Nodes |
US9172647B2 (en) | 2013-04-25 | 2015-10-27 | Ixia | Distributed network test system |
US20150078405A1 (en) | 2013-09-18 | 2015-03-19 | Alcatel Lucent Canada Inc. | Monitoring clock accuracy in asynchronous traffic environments |
US9270395B2 (en) | 2014-05-05 | 2016-02-23 | Telefonaktiebolaget L M Ericsson (Publ) | Method for robust PTP synchronization with default 1588V2 profile |
GB2527529B (en) | 2014-06-24 | 2021-07-14 | Advanced Risc Mach Ltd | A device controller and method for performing a plurality of write transactions atomically within a non-volatile data storage device |
US9787418B2 (en) | 2014-09-09 | 2017-10-10 | Endace Technology Limited | Pluggable time signal adapter modules for selecting a time reference interface |
US9971619B2 (en) | 2014-10-15 | 2018-05-15 | Keysight Technologies Singapore (Holdings) Pte Ltd | Methods and systems for forwarding network packets within virtual machine host systems |
US9344265B2 (en) | 2014-10-15 | 2016-05-17 | Anue Systems, Inc. | Network packet timing synchronization for virtual machine host systems |
US9928193B2 (en) | 2014-11-14 | 2018-03-27 | Cavium, Inc. | Distributed timer subsystem |
US10063449B2 (en) | 2014-12-31 | 2018-08-28 | Telefonaktiebolaget Lm Ericsson (Publ) | Apparatus and method to use PTP timestamps for one-way delay and delay variation measurement in IP networks |
US9819541B2 (en) | 2015-03-20 | 2017-11-14 | Cisco Technology, Inc. | PTP over IP in a network topology with clock redundancy for better PTP accuracy and stability |
RO131471A2 (en) | 2015-04-21 | 2016-10-28 | Ixia, A California Corporation | Methods, systems and computer-readable media for testing quality of recovered clock |
US10027601B2 (en) | 2015-06-03 | 2018-07-17 | Mellanox Technologies, Ltd. | Flow-based packet modification |
US20180188698A1 (en) | 2015-06-10 | 2018-07-05 | Smart Energy Instruments Inc. | Accurate time recovery from global navigation satellite system |
US10425360B2 (en) | 2015-10-28 | 2019-09-24 | Ciena Corporation | Frontplane communication network between multiple pluggable modules on a single faceplate |
US9843439B2 (en) | 2016-01-27 | 2017-12-12 | Ciena Corporation | System and method for managing holdover |
WO2017137906A1 (en) | 2016-02-09 | 2017-08-17 | King Abdullah University Of Science And Technology | Ad hoc networking scheme for mobile cyber-physical systems |
US10020905B2 (en) | 2016-04-19 | 2018-07-10 | Centurylink Intellectual Property Llc | Accurate synchronization as a service |
US10054977B2 (en) | 2016-04-28 | 2018-08-21 | International Business Machines Corporation | Controlling system clocks in virtual machines |
US10320952B2 (en) | 2016-05-16 | 2019-06-11 | Mellanox Technologies Tlv Ltd. | System-wide synchronized switch-over of multicast flows |
US10237008B2 (en) | 2016-06-10 | 2019-03-19 | Apple Inc. | Synchronization with different clock transport protocols |
WO2018044775A1 (en) | 2016-08-30 | 2018-03-08 | Sean Iwasaki | Multi-functional circuity for communications networks and methods and devices utilizing same |
US9958497B2 (en) | 2016-08-31 | 2018-05-01 | Te Connectivity Corporation | Testing pluggable module |
US10382191B2 (en) | 2016-11-30 | 2019-08-13 | Juniper Networks, Inc. | Efficient unicast signaling in a precision time protocol enabled packet network |
US10164759B1 (en) | 2016-12-13 | 2018-12-25 | Amazon Technologies, Inc. | Distributed precision time architecture |
CN106817183B (en) | 2016-12-27 | 2019-03-08 | 天津七六四通信导航技术有限公司 | PTP precision time protocol time service module and implementation method in a kind of electric power time service |
US10104148B2 (en) | 2017-01-03 | 2018-10-16 | Globalfoundries Inc. | Nanosecond accuracy under precision time protocol for ethernet by using high accuracy timestamp assist device |
US10396922B2 (en) | 2017-02-07 | 2019-08-27 | Texas Instruments Incorporated | Apparatus and mechanism to support multiple time domains in a single soc for time sensitive network |
US10419323B2 (en) | 2017-04-24 | 2019-09-17 | Cisco Technology, Inc. | Modulation analyzer module |
US9979998B1 (en) | 2017-05-02 | 2018-05-22 | Amazon Technologies, Inc. | System for time synchronization of audio devices |
US10727966B1 (en) | 2017-08-30 | 2020-07-28 | Amazon Technologies, Inc. | Time synchronization with distributed grand master |
US10887211B2 (en) | 2017-09-18 | 2021-01-05 | Microsemi Storage Solutions, Inc. | Indirect packet classification timestamping system and method |
JP2019092107A (en) | 2017-11-16 | 2019-06-13 | 富士通株式会社 | Transceiver, optical transmission device using the same, and method for optimizing pluggable interface |
US20190158909A1 (en) | 2017-11-17 | 2019-05-23 | Qualcomm Incorporated | Extending synchronous media playback to a bluetooth-only sink device in a connected media environment |
US10313103B1 (en) | 2018-01-24 | 2019-06-04 | Ciena Corporation | Systems and methods for precise time synchronization with optical modules |
US10673883B2 (en) | 2018-05-14 | 2020-06-02 | Cisco Technology, Inc. | Time synchronization attack detection in a deterministic network |
US11277455B2 (en) | 2018-06-07 | 2022-03-15 | Mellanox Technologies, Ltd. | Streaming system |
CN108829493A (en) | 2018-06-22 | 2018-11-16 | 山东超越数控电子股份有限公司 | A kind of virtual machine method for synchronizing time and device |
US11483127B2 (en) | 2018-11-18 | 2022-10-25 | Mellanox Technologies, Ltd. | Clock synchronization |
US11283454B2 (en) | 2018-11-26 | 2022-03-22 | Mellanox Technologies, Ltd. | Synthesized clock synchronization between network devices |
US10778406B2 (en) | 2018-11-26 | 2020-09-15 | Mellanox Technologies, Ltd. | Synthesized clock synchronization between networks devices |
US11283535B2 (en) | 2019-03-20 | 2022-03-22 | Arris Enterprises Llc | Method of remotely monitoring the timing performance of a PTP slave |
US11299168B2 (en) | 2019-04-16 | 2022-04-12 | Baidu Usa Llc | Time synchronization scheme between different computation nodes in autonomous driving system |
US10944852B2 (en) | 2019-04-23 | 2021-03-09 | Cisco Technology, Inc. | Computer network packet transmission timing |
US11265096B2 (en) | 2019-05-13 | 2022-03-01 | Intel Corporation | High accuracy time stamping for multi-lane ports |
US20200401434A1 (en) | 2019-06-19 | 2020-12-24 | Vmware, Inc. | Precision time protocol in a virtualized environment |
US11652561B2 (en) | 2019-06-21 | 2023-05-16 | Intel Corporation | Techniques for determining timestamp inaccuracies in a transceiver |
US11543852B2 (en) | 2019-11-07 | 2023-01-03 | Mellanox Technologies, Ltd. | Multihost clock synchronization |
US11336318B2 (en) | 2020-01-14 | 2022-05-17 | Dell Products L.P. | Transceiver device port configuration and monitoring system |
US11271874B2 (en) | 2020-02-05 | 2022-03-08 | Mellanox Technologies, Ltd. | Network adapter with time-aware packet-processing pipeline |
US11070304B1 (en) | 2020-02-25 | 2021-07-20 | Mellanox Technologies, Ltd. | Physical hardware clock chaining |
EP4128589A1 (en) | 2020-03-23 | 2023-02-08 | Marvell Israel (M.I.S.L) LTD. | One-step timestamping in network devices |
CN113542090B (en) | 2020-04-14 | 2023-07-14 | 宁波弘讯科技股份有限公司 | EtherCAT master-slave station integrated network bridge controller and control method |
US20210328900A1 (en) | 2020-04-20 | 2021-10-21 | Mellanox Technologies, Ltd. | Time-Synchronization Testing in a Network Element |
US11552871B2 (en) | 2020-06-14 | 2023-01-10 | Mellanox Technologies, Ltd. | Receive-side timestamp accuracy |
US20220066978A1 (en) | 2020-08-27 | 2022-03-03 | Qualcomm Incorporated | Missed clock compensation for radio frequency front end timed-trigger accuracy |
US11817994B2 (en) | 2021-01-25 | 2023-11-14 | Yahoo Assets Llc | Time series trend root cause identification |
-
2022
- 2022-01-20 US US17/579,630 patent/US11706014B1/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020031199A1 (en) * | 2000-02-02 | 2002-03-14 | Rolston David Robert Cameron | Method and apparatus for distributed synchronous clocking |
US6718476B1 (en) * | 2000-11-27 | 2004-04-06 | Sony Corporation | Method of synchronizing each local clock to a master clock in a data bus system |
US10014937B1 (en) * | 2016-03-11 | 2018-07-03 | Juniper Networks, Inc. | Timing synchronization and intrusion detection via an optical supervisory channel (OSC) |
Also Published As
Publication number | Publication date |
---|---|
US11706014B1 (en) | 2023-07-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5867765B2 (en) | Multi-protocol I / O interconnect time synchronization | |
US8745431B2 (en) | Compound universal serial bus architecture providing precision synchronisation to an external timebase | |
US11050501B2 (en) | Performing PHY-level hardware timestamping and time synchronization in cost-sensitive environments | |
US11543852B2 (en) | Multihost clock synchronization | |
CN110417503B (en) | Method for testing clock network delay and digital communication equipment | |
US20210152266A1 (en) | Communication apparatus, communication system, communication method, and computer readable medium | |
CN103634092A (en) | High precision timer in CPU cluster | |
KR20030064379A (en) | System and method for synchronizing a skip pattern and initializing a clock forwarding interface in a multiple-clock system | |
GB2568270A (en) | Communication device, cascaded network and internal synchronization method | |
CN110572532B (en) | Synchronization device for splicer and splicing processing system | |
US11706014B1 (en) | Clock synchronization loop | |
US20040193931A1 (en) | System and method for transferring data from a first clock domain to a second clock domain | |
US20210152322A1 (en) | Communication apparatus, communication system, communication method, and computer readable medium | |
US7100065B2 (en) | Controller arrangement for synchronizer data transfer between a core clock domain and bus clock domain each having its own individual synchronizing controller | |
US7436917B2 (en) | Controller for clock synchronizer | |
US7694176B2 (en) | Fault-tolerant computer and method of controlling same | |
US20230370305A1 (en) | Boundary Clock Synchronized Loop | |
US11757608B2 (en) | Communication apparatus, communication system, communication method, and computer readable medium | |
US11552777B2 (en) | Time domains synchronization in a system on chip | |
JPH11265313A (en) | Storage device | |
GB2386714A (en) | Data transfer between processors using a system with an independent data transfer clock. | |
US8380896B2 (en) | Data packer for packing and aligning write data | |
US20230367358A1 (en) | Scalable Boundary Clock | |
US11917045B2 (en) | Scalable synchronization of network devices | |
CN117792558B (en) | Method, apparatus, device and medium for integrating high precision time |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FEPP | Fee payment procedure |
Free format text: ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: BIG.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |