US20230215479A1 - Low power memory device with column and row line switches for specific memory cells - Google Patents
Low power memory device with column and row line switches for specific memory cells Download PDFInfo
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- US20230215479A1 US20230215479A1 US18/182,382 US202318182382A US2023215479A1 US 20230215479 A1 US20230215479 A1 US 20230215479A1 US 202318182382 A US202318182382 A US 202318182382A US 2023215479 A1 US2023215479 A1 US 2023215479A1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/408—Address circuits
- G11C11/4085—Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/18—Bit line organisation; Bit line lay-out
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
- H03K19/1733—Controllable logic circuits
- H03K19/1737—Controllable logic circuits using multiplexers
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/005—Transfer gates, i.e. gates coupling the sense amplifier output to data lines, I/O lines or global bit lines
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
Definitions
- the present invention relates to a memory device, and more particularly, to a memory device with low power consumption.
- FIG. 1 is a diagram showing a memory device of the prior art.
- the memory device 100 comprises a plurality of memory cells MC, a plurality of word lines WL0-WL 255 , and a plurality of bit lines BL0-BL 255 .
- the memory cells MC are arranged in a matrix form. For example, the memory cells are arranged into a matrix having 256 rows and 256 columns.
- the word lines WL0-WL 255 are elongated along a first direction A, and each of the word lines WL0-WL 255 is configured to select a corresponding row of the memory cells MC for a read/write operation.
- the bit lines BL0-BL 255 are elongated along a second direction B different from the first direction A, and each of the bit lines BL0-BL 255 is configured to transmit data of a corresponding column of the memory cells MC.
- FIG. 2 is a diagram showing a memory device 200 with a first bit line arrangement of the prior art.
- the plurality of memory cells MC are divided into a predetermined number (such as 8) of memory blocks bk 0 - bk 7 , and each of the memory blocks bk 0 - bk 7 comprises 32 columns of the memory cells MC.
- the memory device 200 further comprises a plurality of multiplexers MUX0-MUX7.
- Each of the multiplexers MUX0-MUX7 is coupled to bit lines ( bit 0 _ bk 0 to bit 31 _ bk 7 ) of 32 columns of the memory cells MC of a corresponding memory block bk 0 - bk 7 .
- the multiplexer MUX0 is coupled to bit lines ( bit 0 _ bk 0 to bit 31 _ bk 0 ) of 32 columns of the memory cells MC of the memory block bk0
- the multiplexer MUX7 is coupled to bit lines ( bit 0 _ bk 7 to bit 31 _ bk 7 ) of 32 columns of the memory cells MC of the memory block bk7,and so on.
- FIG. 3 is a diagram showing a memory device 300 with a second bit line arrangement of the prior art.
- the memory device 300 with the second bit line arrangement further comprises a plurality of multiplexers MUX0-MUX31.
- the bit lines ( bit 0 _ bk 0 to bit 31 _ bk 7 ) of each memory block bk 0 - bk 7 are scattered sequentially.
- the multiplexer MUX0 is coupled to bit lines ( bit 0 _ bk 0 to bit0_bk7) of first columns of the memory cells of the memory blocks bk 0 - bk 7
- the multiplexer MUX31 is coupled to bit lines ( bit 31 _ bk 0 to bit 31 _ bk 7 ) of 32th columns of the memory cells of the memory blocks bk 0 - bk 7 , and so on.
- the second bit line arrangement of FIG. 3 can simplify wiring.
- the memory devices 100 , 200 , 300 of the prior art when one of the word lines WL0-WL 255 selects a corresponding row of the memory cells MC, all the bit lines BL0-BL 255 are coupled to corresponding selected memory cells for the read/write operation. However, during the read/write operation, some of the bit lines BL0-BL 255 are not required to transmit data. The idle bit lines consume power during the read/write operation, such that the memory device 100 of the prior art has higher power consumption.
- the present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; at least one column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal, and a second terminal, each of the column switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; and a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a row word line, a first terminal, and a second terminal, each of the row switches configured to
- the present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; at least one column word line elongated along the second direction; and a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line, each of the column switches configured to control conduction between the at least one bit line and one of the memory cell groups; wherein a plurality of the memory units are arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding
- the present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; at least one column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line.
- FIG. 1 is a diagram showing a memory device of the prior art.
- FIG. 2 is a diagram showing a memory device with a first bit line arrangement of the prior art.
- FIG. 3 is a diagram showing a memory device with a second bit line arrangement of the prior art.
- FIG. 4 is a diagram showing a memory unit with a first word line arrangement of the present invention.
- FIG. 5 is a diagram showing a memory device of the present invention with the first word line arrangement and the first bit line arrangement.
- FIG. 6 is a diagram showing a memory device of the present invention with the first word line arrangement and the second bit line arrangement.
- FIG. 7 is a diagram showing a memory unit with a first embodiment of a second word line arrangement of the present invention.
- FIG. 8 is a diagram showing a memory unit with a second embodiment of the second word line arrangement of the present invention.
- FIG. 9 is a diagram showing a memory unit with a first embodiment of a third word line arrangement of the present invention.
- FIG. 10 is a diagram showing a memory unit with a second embodiment of the third word line arrangement of the present invention.
- FIG. 11 is a diagram showing a memory device of the present invention with the third word line arrangement and the first bit line arrangement.
- FIG. 12 is a diagram showing a portion of the memory device of FIG. 11 .
- FIG. 13 is a diagram showing a memory device of the present invention with the third word line arrangement and the second bit line arrangement.
- FIG. 14 is a diagram showing a portion of the memory device of FIG. 13 .
- FIG. 15 is a diagram showing a memory unit with a first embodiment of a fourth word line arrangement of the present invention.
- FIG. 16 is a diagram showing a memory unit with a second embodiment of the fourth word line arrangement of the present invention.
- FIG. 17 is a diagram showing a memory device of the present invention with the fourth word line arrangement and the first bit line arrangement.
- FIG. 18 is a diagram showing a memory device of the present invention with the fourth word line arrangement and the second bit line arrangement.
- FIG. 19 is a diagram showing an embodiment of a switch of the memory device of the present invention.
- FIGS. 20 - 22 are diagrams showing examples of the memory device of the present invention configured to operate in a byte enable mode.
- FIG. 4 is a diagram showing a memory unit with a first word line arrangement of the present invention.
- FIG. 5 is a diagram showing a memory device 400 a of the present invention with the first word line arrangement and the first bit line arrangement.
- a column of the memory cells MC and related signal lines/switches are represented by a memory unit in FIG. 5 .
- arrangements of memory cells MC, word lines WL0-WL 255 , bit lines ( bit 0 _ bk 0 to bit 31 _ bk 7 ) and multiplexers MUX 0 -MUX 7 of the memory device 400 a are similar to those of the memory device 200 of FIG. 2 .
- the memory device 400 a further comprises a plurality of column word lines CWL 0 -CWL 7 elongated along the second direction B and a plurality of switches SW.
- Each of the switches SW has a control terminal coupled to a corresponding column word line CWL 0 -CWL 7 , a first terminal coupled to a single memory cell MC, and a second terminal coupled to a corresponding bit line ( bit 0 _ bk 0 to bit 31 _ bk 7 ).
- Each of the column word lines CWL 0 -CWL 7 is configured to control on/off states of the switches SW of a corresponding memory block bk 0 - bk 7 .
- the column word line CWL 0 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk 0
- the column word line CWL 7 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk 7
- each of the column word lines CWL 0 -CWL 7 can control on/off states of all the switches SW of a corresponding memory block bk 0 - bk 7 simultaneously, and the switches SW of different memory blocks bk 0 - bk 7 can be controlled individually.
- the column word lines CWL 0 -CWL 7 can be used to further select the memory cells MC of the specific memory block bk 0 - bk 7 for the read/write operation.
- the column word line CWL 0 transmits a control signal to the control terminals of the switches SW of the memory block bk 0
- the switches SW of the memory block bk 0 are turned on to couple the memory cells MC of the memory block bk 0 to the corresponding bit lines ( bit 0 _ bk 0 to bit 31 _ bk 0 ), for allowing the corresponding bit lines ( bit 0 _ bk 0 to bit 3 1 _ bk 0 ) to transmit data.
- other bit lines corresponding to the memory block bk 1 - bk 7 are not driven to transmit data. Therefore, the power consumption of the memory device 400 a can be reduced.
- the memory cell MC may correspond to a plurality of bit lines.
- the memory cell when the memory cell is a memory cell of SRAM, the memory cell may be selected to couple to two bit lines. Accordingly, two or more column word lines can be arranged to control electrical connections between the memory cell and the two bit lines.
- FIG. 6 is a diagram showing a memory device 500 a of the present invention with the first word line arrangement and the second bit line arrangement.
- a column of the memory cells MC and related signal lines/switches are represented by a memory unit in FIG. 6 .
- arrangements of memory cells MC, word lines WL0-WL 255 , bit lines ( bit 0 _ bk 0 to bit 31 _ bk 7 ) and multiplexers MUX 0 -MUX 31 of the memory device 500 a are similar to those of the memory device 300 of FIG. 3 .
- each of the column word lines CWL 0 -CWL 7 is still configured to control on/off states of the switches SW of a corresponding memory block bk 0 - bk 7 .
- the column word line CWL 0 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk 0
- the column word line CWL 7 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk 7 , and so on.
- each of the column word lines CWL 0 -CWL 7 can control on/off states of all the switches SW of a corresponding memory block bk 0 - bk 7 simultaneously, and the switches SW of different memory blocks bk 0 - bk 7 can be controlled individually.
- the column word lines CWL 0 -CWL 7 can be used to further select the memory cells MC of the specific memory block bk 0 - bk 7 for the read/write operation.
- the word line CWL 0 transmits a control signal to the control terminals of the switches SW of the memory block bk 0
- the switches SW of the memory block bk 0 are turned on to couple the memory cells MC of the memory block bk 0 to the corresponding bit lines ( bit 0 _ bk 0 to bit 31 _ bk 0 ), for allowing the corresponding bit lines ( bit 0 _ bk 0 to bit3 1_bk0) to transmit data.
- other bit lines corresponding to the memory block bk 1 - bk 7 are not driven to transmit data. Therefore, the power consumption of the memory device 500 a can be reduced.
- FIG. 7 is a diagram showing a memory unit with a first embodiment of a second word line arrangement of the present invention.
- a column of the memory cells MC are divided into a predetermined number (such as 32) of memory cell groups, and each of the 32 memory cell groups comprises 8 memory cells.
- the switch SW is coupled between one of the 32 memory cell groups and a corresponding bit line.
- the column word line is configured to turn on/off 32 switches SW of each column of the memory cells MC of a corresponding memory block simultaneously.
- the second word line arrangement of FIG. 7 is applicable to the memory device 400 a of FIG. 5 and the memory device 500 a of FIG. 6 .
- the column word line CWL 0 is coupled to the control terminals of the 32 switches SW of each column of the memory cells MC of the memory block bk 0
- the column word line CWL 7 is coupled to the control terminals of the 32 switches SW of each column of the memory cells MC of the memory block bk 7
- each of the column word lines CWL 0 -CWL 7 can control on/off states of all the switches SW of a corresponding memory block bk 0 - bk 7 simultaneously.
- FIG. 8 is a diagram showing a memory unit with a second embodiment of the second word line arrangement of the present invention.
- the memory cells MC of each memory cell group of FIG. 8 are coupled in series (such as memory cells of a flash memory device).
- the column word line is configured to turn on/off 32 switches SW of each column of the memory cells MC of a corresponding memory block simultaneously.
- the second word line arrangement of FIG. 8 is also applicable to the memory device 400 a of FIG. 5 and the memory device 500 a of FIG. 6 .
- each of the memory cell group comprises 8 memory cells, but the present invention is not limited to it. In other embodiments of the present invention, each of the memory cell group can comprises other number of memory cells according to design requirements.
- the second word line arrangements of FIG. 7 and FIG. 8 comprise fewer switches, in order to reduce overall area of the memory devices.
- FIG. 9 is a diagram showing a memory unit with a first embodiment of a third word line arrangement of the present invention.
- FIG. 11 is a diagram showing a memory device 400 b of the present invention with the third word line arrangement and the first bit line arrangement.
- FIG. 12 is a diagram showing a portion of the memory device 400 b of FIG. 11 .
- a column of the memory cells MC and related signal lines/switches are represented by a memory unit in FIG. 11 , and word lines are omitted in FIGS. 11 and 12 .
- a column of the memory cells MC are divided into a predetermined number (such as 32) of memory cell groups, and each of the 32 memory cell groups comprises 8 memory cells.
- the switch SW is coupled between one of the 32 memory cell groups and a corresponding bit line.
- the memory device 400 b comprises a plurality of row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) elongated along the first direction A, and each of the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) is configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block.
- the row word line RWL 0 _ bk 0 is coupled to the control terminal of the switch SW corresponding to the first memory cell group of each column of the memory block bk 0
- the row word line RWL 31 _ bk 0 is coupled to the control terminal of the switch SW corresponding to the 32th memory cell group of each column of the memory block bk 0
- the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) can further select a specific memory cell group of each column of the memory cells MC of a corresponding memory block bk 0 - bk 7 for transmitting data.
- FIG. 13 is a diagram showing a memory device 500 b of the present invention with the third word line arrangement and the second bit line arrangement.
- FIG. 14 is a diagram showing a portion of the memory device 500 b of FIG. 13 .
- a column of the memory cells MC and related signal lines/switches are represented by a memory unit in FIG. 13 , and word lines are omitted in FIGS. 13 and 14 .
- bit lines ( bit 0 _ bk 0 to bit 31 _ bk 7 ) of each memory block bk 0 - bk 7 are scattered sequentially, the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) in FIGS. 13 - 14 is still configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block.
- the row word line RWL 0 _ bk 0 is coupled to the control terminal of the switch SW corresponding to the first memory cell group of each column of the memory block bk 0
- the row word line RWL 31 _ bk 0 is coupled to the control terminal of the switch SW corresponding to the 32th memory cell group of each column of the memory block bk 0
- the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) can further select a specific memory cell group of each column of the memory cells MC of a corresponding memory block bk 0 - bk 7 for transmitting data.
- FIG. 10 is a diagram showing a memory unit with a second embodiment of the third word line arrangement of the present invention.
- the memory cells MC of each memory cell group of FIG. 10 are coupled in series (such as memory cells of a flash memory device).
- the row word line is configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block.
- the third word line arrangement of FIG. 10 is also applicable to the memory device 400 b of FIG. 11 and the memory device 500 b of FIG. 13 .
- the third word line arrangement Comparing with the first word line arrangement and the second word line arrangement, the third word line arrangement only turns on one switch SW of each column of the memory cells MC for transmitting data. Thus the third word line arrangement can further reduce power consumption of the memory device.
- a number of the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) is a multiple of a number of the column word lines CWL 0 -CWL 7 .
- the third word line arrangement may need to form the plurality of row word lines in different metal layers, but the first word line arrangement and the second word line arrangement can form the plurality of column word lines in a same metal layer.
- each of the memory cell group comprises four memory cells
- the memory device comprises 32 memory blocks
- the 32 row word lines must be form in different metal layers.
- the first word line arrangement and the second word line arrangement only one column word line needs to be arranged within the layout area of the memory cells.
- the column word lines can be formed in a same metal layer.
- FIG. 15 is a diagram showing a memory unit with a first embodiment of a fourth word line arrangement of the present invention.
- FIG. 17 is a diagram showing a memory device 400 c of the present invention with the fourth word line arrangement and the first bit line arrangement.
- a column of the memory cells MC and related signal lines/switches are represented by a memory unit, and word lines are omitted in FIG. 17 .
- the memory device 400 c comprises a plurality of column switches SW 1 and a plurality of row switches SW 2 .
- the column switch SW 1 is controlled by the corresponding column word line CWL 0 -CWL 7 .
- the row switch SW 2 is controlled by the corresponding row word line (RWL 0 _ bk 0 to RWL 31 _ bk 7 ).
- the column switch SW 1 of FIG. 15 operates similarly to the switch SW of FIG. 7
- the row switch SW 2 operates similarly to the switch SW of FIG. 9 .
- the electrical connection of the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) of FIG. 17 is similar to that of FIG. 12 .
- the column switch SW 1 and the row switch SW 2 are coupled between one of the memory cell groups and a corresponding bit line in series ( bit 0 _ bk 0 to bit 31 _ bk 7 ).
- the memory cells MC can be selected by the corresponding word line, column word line CWL 0 -CWL 7 , row word line (RWL 0 _ bk 0 to RWL 31 _ bk 7 ).
- the memory device 400 c can also reduce power consumption. Moreover, the memory device 400 c can operate in two modes. For example, when the column word lines are configured to turn on all the column switches SW 1 in default, the memory device 400 c can operate similarly to the memory device 400 b ; and when branches of column word lines, which extend to the memory units, of each memory block are further grouped into four groups to respectively control eight columns of memory cells to work individually, the memory device 400 c can operate in a byte enable mode for outputting data in byte format.
- each of four row word lines (RWL 0 _ bk 0 _ byte 0 to RWL 0 _ bk 0 _ byte 3 ) of the memory block bk 0 is arranged to control eight columns of memory cells of the first memory cell groups to work individually.
- the fourth word line arrangement needs only eight row word lines to be arranged within the layout area of the eight memory cells of a memory cell group for passing through.
- the third word line arrangement must form the 32 row word lines in different metal layers, but the fourth word line arrangement can form the eight row word lines in a same metal layer. For example, as shown in FIG.
- the row word lines (RWL 0 _ bk 0 _ byte 0 to RWL 0 _ bk 7 _ byte 3 ) corresponding to the first memory cell groups of the eight memory blocks are all arranged to pass through each of the first memory cell groups.
- FIG. 21 for controlling the first memory cell groups of the eight memory blocks of the third word line arrangement to operate in the byte enable mode, the row word lines (RWL 0 _ bk 0 _ byte 0 to RWL 0 _ bk 7 _ byte 3 ) corresponding to the first memory cell groups of the eight memory blocks are all arranged to pass through each of the first memory cell groups.
- branches of column word lines of the memory block bk 0 are grouped into four column word lines (CWL 0 _ byte 0 to CWL 0 _ byte 3 ) to respectively control eight columns of memory cells to operate in the byte enable mode, and the number of the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) of the fourth word line arrangement remains the same.
- the fourth word line arrangement of the memory device 400 c can operate similarly to the third word line arrangement of the memory device 400 b , thus the power consumption of the memory device 400 c and the memory device 400 b are almost the same. Therefore, the fourth word line arrangement has both the advantages of the first/second word line arrangement and the third word line arrangement.
- FIG. 18 is a diagram showing a memory device 500 c of the present invention with the fourth word line arrangement and the second bit line arrangement.
- a column of the memory cells MC and related signal lines/switches are represented by a memory unit, and word lines are omitted in FIG. 18 .
- the electrical connection of the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ) of FIG. 18 is similar to that of FIG. 14 .
- bit lines ( bit 0 _ bk 0 to bit 31 _ bk 7 ) of each memory block bk 0 - bk 7 are scattered sequentially, the column word lines CWL 0 -CWL 7 , the row word lines (RWL 0 _ bk 0 to RWL 31 _ bk 7 ), the column switches SW 1 and the row switches SW 2 of FIG. 18 still operate similarly to those of FIG. 17 . Therefore, no further illustration is provided.
- FIG. 16 is a diagram showing a memory unit with a second embodiment of the fourth word line arrangement of the present invention. Different from the embodiment of FIG. 15 , the memory cells MC of each memory cell group of FIG. 16 are coupled in series (such as memory cells of a flash memory device). Similarly, the fourth word line arrangement of FIG. 16 is also applicable to the memory device 400 c of FIG. 17 and the memory device 500 c of FIG. 18 .
- FIG. 19 is a diagram showing an embodiment of a switch of the memory device of the present invention.
- the aforementioned switches SW, SW 1 , SW 2 can be transistors, but the present invention is not limited to it.
- the switches SW, SW 1 , SW 2 can be other type of switch element for controlling electrical connections between the memory cells and the bit lines.
- the memory cells MC are arranged into a matrix having 256 rows and 256 columns, the plurality of memory cells are divided into 8 memory blocks bk 0 - bk 7 , each of the 8 memory blocks bk 0 - bk 7 comprises 32 columns of the memory cells MC, and each memory cell group comprises 8 memory cells.
- the present invention is not limited to the above embodiment. In other embodiment of the present invention, the numbers of rows and columns of the matrix, the number of the memory blocks in the memory device, the number of columns of the memory cells in the memory block, and the number of the memory cells in the memory cell group can be different from the above numbers and determined according to design requirements.
- the memory device of the present invention comprises the column word lines and/or the row word lines for further selecting specific memory cells to be coupled to corresponding bit lines, such that other bit lines corresponding to the unselected memory cells are not driven to transmit data. Therefore, the memory device of the present invention has lower power consumption.
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Abstract
A memory device includes a plurality of word lines elongated along a first direction, and at least one memory unit. The at least one memory unit includes a plurality of memory cells, at least one bit line, and at least one column word line. The plurality of memory cells are arranged along a second direction different from the first direction. The at least one bit line is elongated along the second direction, and configured to transmit data of a selected memory cell. The at least one column word line is elongated along the second direction, and configured to control electrical connections between the memory cells and the at least one bit line, wherein the selected memory cell is selected by a corresponding word line and the at least one column word line.
Description
- This application is a continuation application of and claims the priority benefit of U.S. Pat. Application Serial No. 15/949,077, filed on Apr. 10, 2018. The U.S. Pat. Application Serial No. 15/949,077 is a continuation application of and claims the priority benefit of U.S. Pat. Application Serial No. 14/840,037, filed on Aug. 30, 2015. The entirety of each of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of this specification.
- The present invention relates to a memory device, and more particularly, to a memory device with low power consumption.
- Please refer to
FIG. 1 .FIG. 1 is a diagram showing a memory device of the prior art. As shown inFIG. 1 , thememory device 100 comprises a plurality of memory cells MC, a plurality of word lines WL0-WL255, and a plurality of bit lines BL0-BL255. The memory cells MC are arranged in a matrix form. For example, the memory cells are arranged into a matrix having 256 rows and 256 columns. The word lines WL0-WL255 are elongated along a first direction A, and each of the word lines WL0-WL255 is configured to select a corresponding row of the memory cells MC for a read/write operation. The bit lines BL0-BL255 are elongated along a second direction B different from the first direction A, and each of the bit lines BL0-BL255 is configured to transmit data of a corresponding column of the memory cells MC. - Please refer to
FIG. 2 .FIG. 2 is a diagram showing amemory device 200 with a first bit line arrangement of the prior art. As shown inFIG. 2 , the plurality of memory cells MC are divided into a predetermined number (such as 8) of memory blocks bk 0-bk 7, and each of the memory blocks bk 0-bk 7 comprises 32 columns of the memory cells MC. Moreover, in addition to the memory cells MC, the word lines WL0-WL255, and the bit lines (bit 0_bk 0 to bit 31_bk 7), thememory device 200 further comprises a plurality of multiplexers MUX0-MUX7. Each of the multiplexers MUX0-MUX7 is coupled to bit lines (bit 0_bk 0 to bit 31_bk 7) of 32 columns of the memory cells MC of a corresponding memory block bk 0-bk 7. For example, the multiplexer MUX0 is coupled to bit lines (bit 0_bk 0 to bit 31_bk 0) of 32 columns of the memory cells MC of the memory block bk0, the multiplexer MUX7 is coupled to bit lines (bit 0_bk 7 to bit 31_bk 7) of 32 columns of the memory cells MC of the memory block bk7,and so on. - Please refer to
FIG. 3 .FIG. 3 is a diagram showing amemory device 300 with a second bit line arrangement of the prior art. As shown inFIG. 3 , in addition to the memory cells MC, the word lines WL0-WL255, and the bit lines (bit 0_bk 0 to bit 31_bk 7), thememory device 300 with the second bit line arrangement further comprises a plurality of multiplexers MUX0-MUX31. Moreover, the bit lines (bit 0_bk 0 to bit 31_bk 7) of each memory block bk 0-bk 7 are scattered sequentially. For example, the multiplexer MUX0 is coupled to bit lines (bit 0_bk 0 to bit0_bk7) of first columns of the memory cells of the memory blocks bk 0-bk 7, the multiplexer MUX31 is coupled to bit lines (bit 31_bk 0 to bit 31_bk 7) of 32th columns of the memory cells of the memory blocks bk 0-bk 7, and so on. Comparing with the first bit line arrangement ofFIG. 2 , the second bit line arrangement ofFIG. 3 can simplify wiring. - In the
memory devices memory device 100 of the prior art has higher power consumption. - The present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; at least one column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal, and a second terminal, each of the column switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; and a plurality of row switches arranged along the second direction, each of the row switches having a control terminal coupled to a row word line, a first terminal, and a second terminal, each of the row switches configured to control conduction between the first terminal and the second terminal according to signals received from the control terminal; wherein each of the column switches and each of the row switches are electrically coupled in series between the at least one bit line and the plurality of memory cells of one of the memory cell groups.
- The present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; at least one column word line elongated along the second direction; and a plurality of column switches arranged along the second direction, each of the column switches having a control terminal coupled to the at least one column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line, each of the column switches configured to control conduction between the at least one bit line and one of the memory cell groups; wherein a plurality of the memory units are arranged along the first direction, a predetermined number of the memory units form a memory block, and the column word lines of the memory units are grouped to control the column switches of corresponding memory blocks respectively.
- The present invention provides a memory device, which comprises a plurality of word lines elongated along a first direction; and at least one memory unit comprising a plurality of memory cell groups arranged along a second direction different from the first direction, each of the memory cell groups comprising a plurality of memory cells; at least one bit line elongated along the second direction, and configured to transmit data of a selected memory cell; at least one column word line elongated along the second direction; a plurality of row word lines elongated along the first direction; wherein the selected memory cell is selected by a corresponding word line, the at least one column word line and a corresponding row word line.
- These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
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FIG. 1 is a diagram showing a memory device of the prior art. -
FIG. 2 is a diagram showing a memory device with a first bit line arrangement of the prior art. -
FIG. 3 is a diagram showing a memory device with a second bit line arrangement of the prior art. -
FIG. 4 is a diagram showing a memory unit with a first word line arrangement of the present invention. -
FIG. 5 is a diagram showing a memory device of the present invention with the first word line arrangement and the first bit line arrangement. -
FIG. 6 is a diagram showing a memory device of the present invention with the first word line arrangement and the second bit line arrangement. -
FIG. 7 is a diagram showing a memory unit with a first embodiment of a second word line arrangement of the present invention. -
FIG. 8 is a diagram showing a memory unit with a second embodiment of the second word line arrangement of the present invention. -
FIG. 9 is a diagram showing a memory unit with a first embodiment of a third word line arrangement of the present invention. -
FIG. 10 is a diagram showing a memory unit with a second embodiment of the third word line arrangement of the present invention. -
FIG. 11 is a diagram showing a memory device of the present invention with the third word line arrangement and the first bit line arrangement. -
FIG. 12 is a diagram showing a portion of the memory device ofFIG. 11 . -
FIG. 13 is a diagram showing a memory device of the present invention with the third word line arrangement and the second bit line arrangement. -
FIG. 14 is a diagram showing a portion of the memory device ofFIG. 13 . -
FIG. 15 is a diagram showing a memory unit with a first embodiment of a fourth word line arrangement of the present invention. -
FIG. 16 is a diagram showing a memory unit with a second embodiment of the fourth word line arrangement of the present invention. -
FIG. 17 is a diagram showing a memory device of the present invention with the fourth word line arrangement and the first bit line arrangement. -
FIG. 18 is a diagram showing a memory device of the present invention with the fourth word line arrangement and the second bit line arrangement. -
FIG. 19 is a diagram showing an embodiment of a switch of the memory device of the present invention. -
FIGS. 20-22 are diagrams showing examples of the memory device of the present invention configured to operate in a byte enable mode. - Please refer to
FIG. 4 andFIG. 5 together.FIG. 4 is a diagram showing a memory unit with a first word line arrangement of the present invention.FIG. 5 is a diagram showing amemory device 400 a of the present invention with the first word line arrangement and the first bit line arrangement. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit inFIG. 5 . As shown in figures, arrangements of memory cells MC, word lines WL0-WL255, bit lines (bit 0_bk 0 to bit 31_bk 7) and multiplexers MUX0-MUX7 of thememory device 400 a are similar to those of thememory device 200 ofFIG. 2 . Thememory device 400 a further comprises a plurality of column word lines CWL0-CWL7 elongated along the second direction B and a plurality of switches SW. Each of the switches SW has a control terminal coupled to a corresponding column word line CWL0-CWL7, a first terminal coupled to a single memory cell MC, and a second terminal coupled to a corresponding bit line (bit 0_bk 0 to bit 31_bk 7). Each of the column word lines CWL0-CWL7 is configured to control on/off states of the switches SW of a corresponding memory block bk 0-bk 7. For example, the column word line CWL0 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of thememory block bk 0, the column word line CWL7 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk 7, and so on. As such, each of the column word lines CWL0-CWL7 can control on/off states of all the switches SW of a corresponding memory block bk 0-bk 7 simultaneously, and the switches SW of different memory blocks bk 0-bk 7 can be controlled individually. - According to the above arrangement, when one of the word lines WL0-WL255 selects a corresponding row of the memory cells MC for a read/write operation, the column word lines CWL0-CWL7 can be used to further select the memory cells MC of the specific memory block bk 0-bk 7 for the read/write operation. For example, when the column word line CWL0 transmits a control signal to the control terminals of the switches SW of the
memory block bk 0, only the switches SW of thememory block bk 0 are turned on to couple the memory cells MC of thememory block bk 0 to the corresponding bit lines (bit 0_bk 0 to bit 31_bk 0), for allowing the corresponding bit lines (bit 0_bk 0 to bit 3 1_bk 0) to transmit data. On the other hand, other bit lines corresponding to the memory block bk 1-bk 7 are not driven to transmit data. Therefore, the power consumption of thememory device 400 a can be reduced. - In addition, the memory cell MC may correspond to a plurality of bit lines. For example, when the memory cell is a memory cell of SRAM, the memory cell may be selected to couple to two bit lines. Accordingly, two or more column word lines can be arranged to control electrical connections between the memory cell and the two bit lines.
- Please refer to
FIG. 4 andFIG. 6 together.FIG. 6 is a diagram showing amemory device 500 a of the present invention with the first word line arrangement and the second bit line arrangement. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit inFIG. 6 . As shown in figures, arrangements of memory cells MC, word lines WL0-WL255, bit lines (bit 0_bk 0 to bit 31_bk 7) and multiplexers MUX0-MUX31 of thememory device 500 a are similar to those of thememory device 300 ofFIG. 3 . Although the bit lines (bit 0_bk 0 to bit 31_bk 7) of each memory block bk 0-bk 7 are scattered sequentially, each of the column word lines CWL0-CWL7 is still configured to control on/off states of the switches SW of a corresponding memory block bk 0-bk 7. For example, the column word line CWL0 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of thememory block bk 0, the column word line CWL7 is coupled to the control terminals of the 256 switches SW of each column of the memory cells MC of the memory block bk 7, and so on. As such, each of the column word lines CWL0-CWL7 can control on/off states of all the switches SW of a corresponding memory block bk 0-bk 7 simultaneously, and the switches SW of different memory blocks bk 0-bk 7 can be controlled individually. - Similarly, when one of the word lines WL0-WL255 selects a corresponding row of the memory cells MC for the read/write operation, the column word lines CWL0-CWL7 can be used to further select the memory cells MC of the specific memory block bk 0-bk 7 for the read/write operation. For example, when the word line CWL0 transmits a control signal to the control terminals of the switches SW of the
memory block bk 0, only the switches SW of thememory block bk 0 are turned on to couple the memory cells MC of thememory block bk 0 to the corresponding bit lines (bit 0_bk 0 to bit 31_bk 0), for allowing the corresponding bit lines (bit 0_bk 0 to bit3 1_bk0) to transmit data. On the other hand, other bit lines corresponding to the memory block bk 1-bk 7 are not driven to transmit data. Therefore, the power consumption of thememory device 500 a can be reduced. - Please refer to
FIG. 7 .FIG. 7 is a diagram showing a memory unit with a first embodiment of a second word line arrangement of the present invention. As shown inFIG. 7 , a column of the memory cells MC are divided into a predetermined number (such as 32) of memory cell groups, and each of the 32 memory cell groups comprises 8 memory cells. The switch SW is coupled between one of the 32 memory cell groups and a corresponding bit line. The column word line is configured to turn on/off 32 switches SW of each column of the memory cells MC of a corresponding memory block simultaneously. - The second word line arrangement of
FIG. 7 is applicable to thememory device 400 a ofFIG. 5 and thememory device 500 a ofFIG. 6 . For example, the column word line CWL0 is coupled to the control terminals of the 32 switches SW of each column of the memory cells MC of thememory block bk 0, the column word line CWL7 is coupled to the control terminals of the 32 switches SW of each column of the memory cells MC of the memory block bk 7, and so on. As such, each of the column word lines CWL0-CWL7 can control on/off states of all the switches SW of a corresponding memory block bk 0-bk 7 simultaneously. - Please refer to
FIG. 8 .FIG. 8 is a diagram showing a memory unit with a second embodiment of the second word line arrangement of the present invention. Different from the embodiment ofFIG. 7 , the memory cells MC of each memory cell group ofFIG. 8 are coupled in series (such as memory cells of a flash memory device). The column word line is configured to turn on/off 32 switches SW of each column of the memory cells MC of a corresponding memory block simultaneously. Similarly, the second word line arrangement ofFIG. 8 is also applicable to thememory device 400 a ofFIG. 5 and thememory device 500 a ofFIG. 6 . - In the embodiments of
FIG. 7 andFIG. 8 , each of the memory cell group comprises 8 memory cells, but the present invention is not limited to it. In other embodiments of the present invention, each of the memory cell group can comprises other number of memory cells according to design requirements. - Comparing with the first word line arrangement of
FIG. 4 , the second word line arrangements ofFIG. 7 andFIG. 8 comprise fewer switches, in order to reduce overall area of the memory devices. - Please refer to
FIG. 9 andFIGS. 11-12 together.FIG. 9 is a diagram showing a memory unit with a first embodiment of a third word line arrangement of the present invention.FIG. 11 is a diagram showing amemory device 400 b of the present invention with the third word line arrangement and the first bit line arrangement.FIG. 12 is a diagram showing a portion of thememory device 400 b ofFIG. 11 . For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit inFIG. 11 , and word lines are omitted inFIGS. 11 and 12 . As shown in figures, a column of the memory cells MC are divided into a predetermined number (such as 32) of memory cell groups, and each of the 32 memory cell groups comprises 8 memory cells. The switch SW is coupled between one of the 32 memory cell groups and a corresponding bit line. Thememory device 400 b comprises a plurality of row word lines (RWL0_bk 0 to RWL31_bk 7) elongated along the first direction A, and each of the row word lines (RWL0_bk 0 to RWL31_bk 7) is configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block. For example, the rowword line RWL0_bk 0 is coupled to the control terminal of the switch SW corresponding to the first memory cell group of each column of thememory block bk 0, the rowword line RWL31_bk 0 is coupled to the control terminal of the switch SW corresponding to the 32th memory cell group of each column of thememory block bk 0, and so on. As such, the row word lines (RWL0_bk 0 to RWL31_bk 7) can further select a specific memory cell group of each column of the memory cells MC of a corresponding memory block bk 0-bk 7 for transmitting data. - Please refer to
FIG. 9 andFIGS. 13-14 together.FIG. 13 is a diagram showing amemory device 500 b of the present invention with the third word line arrangement and the second bit line arrangement.FIG. 14 is a diagram showing a portion of thememory device 500 b ofFIG. 13 . For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit inFIG. 13 , and word lines are omitted inFIGS. 13 and 14 . Although the bit lines (bit 0_bk 0 to bit 31_bk 7) of each memory block bk 0-bk 7 are scattered sequentially, the row word lines (RWL0_bk 0 to RWL31_bk 7) inFIGS. 13-14 is still configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block. For example, the rowword line RWL0_bk 0 is coupled to the control terminal of the switch SW corresponding to the first memory cell group of each column of thememory block bk 0, the rowword line RWL31_bk 0 is coupled to the control terminal of the switch SW corresponding to the 32th memory cell group of each column of thememory block bk 0, and so on. As such, the row word lines (RWL0_bk 0 to RWL31_bk 7) can further select a specific memory cell group of each column of the memory cells MC of a corresponding memory block bk 0-bk 7 for transmitting data. - Please refer to
FIG. 10 .FIG. 10 is a diagram showing a memory unit with a second embodiment of the third word line arrangement of the present invention. Different from the embodiment ofFIG. 9 , the memory cells MC of each memory cell group ofFIG. 10 are coupled in series (such as memory cells of a flash memory device). The row word line is configured to turn on/off one of 32 switches SW of each column of the memory cells MC of a corresponding memory block. Similarly, the third word line arrangement ofFIG. 10 is also applicable to thememory device 400 b ofFIG. 11 and thememory device 500 b ofFIG. 13 . - Comparing with the first word line arrangement and the second word line arrangement, the third word line arrangement only turns on one switch SW of each column of the memory cells MC for transmitting data. Thus the third word line arrangement can further reduce power consumption of the memory device. However, a number of the row word lines (
RWL0_bk 0 to RWL31_bk 7) is a multiple of a number of the column word lines CWL0-CWL7. The third word line arrangement may need to form the plurality of row word lines in different metal layers, but the first word line arrangement and the second word line arrangement can form the plurality of column word lines in a same metal layer. For example, when each of the memory cell group comprises four memory cells, and the memory device comprises 32 memory blocks, there are totally 32 row word lines need to be arranged within a layout area of the four memory cells for passing through. Thus the 32 row word lines must be form in different metal layers. As to the first word line arrangement and the second word line arrangement, only one column word line needs to be arranged within the layout area of the memory cells. Thus the column word lines can be formed in a same metal layer. - Please refer to
FIG. 15 andFIG. 17 together.FIG. 15 is a diagram showing a memory unit with a first embodiment of a fourth word line arrangement of the present invention.FIG. 17 is a diagram showing amemory device 400 c of the present invention with the fourth word line arrangement and the first bit line arrangement. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit, and word lines are omitted inFIG. 17 . As shown in figures, thememory device 400 c comprises a plurality of column switches SW1 and a plurality of row switches SW2. The column switch SW1 is controlled by the corresponding column word line CWL0-CWL7. The row switch SW2 is controlled by the corresponding row word line (RWL0_bk 0 to RWL31_bk 7). The column switch SW1 ofFIG. 15 operates similarly to the switch SW ofFIG. 7 , and the row switch SW2 operates similarly to the switch SW ofFIG. 9 . The electrical connection of the row word lines (RWL0_bk 0 to RWL31_bk 7) ofFIG. 17 is similar to that ofFIG. 12 . The column switch SW1 and the row switch SW2 are coupled between one of the memory cell groups and a corresponding bit line in series (bit 0_bk 0 to bit 31_bk 7). The memory cells MC can be selected by the corresponding word line, column word line CWL0-CWL7, row word line (RWL0_bk 0 to RWL31_bk 7). - According to the above arrangement, the
memory device 400 c can also reduce power consumption. Moreover, thememory device 400 c can operate in two modes. For example, when the column word lines are configured to turn on all the column switches SW1 in default, thememory device 400 c can operate similarly to thememory device 400 b; and when branches of column word lines, which extend to the memory units, of each memory block are further grouped into four groups to respectively control eight columns of memory cells to work individually, thememory device 400 c can operate in a byte enable mode for outputting data in byte format. - When the third word line arrangement in
FIG. 11 is further configured to operate in a byte enable mode, the number of the row word line of a memory block needs to be multiplied by four for respectively controlling eight columns of memory cells to work individually. For example, as shown inFIG. 20 , each of four row word lines (RWL0_bk 0_byte 0 to RWL0_bk 0_byte 3) of thememory block bk 0 is arranged to control eight columns of memory cells of the first memory cell groups to work individually. In other words, there are totally 32 row word lines need to be arranged within a layout area of the eight memory cells of a memory cell group for passing through, where the fourth word line arrangement needs only eight row word lines to be arranged within the layout area of the eight memory cells of a memory cell group for passing through. Thus the third word line arrangement must form the 32 row word lines in different metal layers, but the fourth word line arrangement can form the eight row word lines in a same metal layer. For example, as shown inFIG. 21 , for controlling the first memory cell groups of the eight memory blocks of the third word line arrangement to operate in the byte enable mode, the row word lines (RWL0_bk 0_byte 0 to RWL0_bk 7_byte 3) corresponding to the first memory cell groups of the eight memory blocks are all arranged to pass through each of the first memory cell groups. However, as shown inFIG. 22 , branches of column word lines of thememory block bk 0 are grouped into four column word lines (CWL0_byte 0 to CWL0_byte 3) to respectively control eight columns of memory cells to operate in the byte enable mode, and the number of the row word lines (RWL0_bk 0 to RWL31_bk 7) of the fourth word line arrangement remains the same. As mentioned above, the fourth word line arrangement of thememory device 400 c can operate similarly to the third word line arrangement of thememory device 400 b, thus the power consumption of thememory device 400 c and thememory device 400 b are almost the same. Therefore, the fourth word line arrangement has both the advantages of the first/second word line arrangement and the third word line arrangement. - Please refer to
FIG. 15 andFIG. 18 together.FIG. 18 is a diagram showing amemory device 500 c of the present invention with the fourth word line arrangement and the second bit line arrangement. For ease of illustration, a column of the memory cells MC and related signal lines/switches are represented by a memory unit, and word lines are omitted inFIG. 18 . The electrical connection of the row word lines (RWL0_bk 0 to RWL31_bk 7) ofFIG. 18 is similar to that ofFIG. 14 . Although the bit lines (bit 0_bk 0 to bit 31_bk 7) of each memory block bk 0- bk 7 are scattered sequentially, the column word lines CWL0-CWL7, the row word lines (RWL0_bk 0 to RWL31_bk 7), the column switches SW1 and the row switches SW2 ofFIG. 18 still operate similarly to those ofFIG. 17 . Therefore, no further illustration is provided. - Please refer to
FIG. 16 .FIG. 16 is a diagram showing a memory unit with a second embodiment of the fourth word line arrangement of the present invention. Different from the embodiment ofFIG. 15 , the memory cells MC of each memory cell group ofFIG. 16 are coupled in series (such as memory cells of a flash memory device). Similarly, the fourth word line arrangement ofFIG. 16 is also applicable to thememory device 400 c ofFIG. 17 and thememory device 500 c ofFIG. 18 . - Please refer to
FIG. 19 .FIG. 19 is a diagram showing an embodiment of a switch of the memory device of the present invention. As shown in figures, the aforementioned switches SW, SW1, SW2 can be transistors, but the present invention is not limited to it. The switches SW, SW1, SW2 can be other type of switch element for controlling electrical connections between the memory cells and the bit lines. - In the above embodiments, the memory cells MC are arranged into a matrix having 256 rows and 256 columns, the plurality of memory cells are divided into 8 memory blocks bk 0-bk 7, each of the 8 memory blocks bk 0-bk 7 comprises 32 columns of the memory cells MC, and each memory cell group comprises 8 memory cells. However, the present invention is not limited to the above embodiment. In other embodiment of the present invention, the numbers of rows and columns of the matrix, the number of the memory blocks in the memory device, the number of columns of the memory cells in the memory block, and the number of the memory cells in the memory cell group can be different from the above numbers and determined according to design requirements.
- In contrast to the prior art, the memory device of the present invention comprises the column word lines and/or the row word lines for further selecting specific memory cells to be coupled to corresponding bit lines, such that other bit lines corresponding to the unselected memory cells are not driven to transmit data. Therefore, the memory device of the present invention has lower power consumption.
- Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
Claims (4)
1. A memory device, comprising:
a plurality of word lines;
a plurality of row word lines; and
a plurality of memory blocks, each of the memory blocks comprising a plurality of memory units, each of the memory units comprising:
a plurality of memory cell groups, each of the memory cell groups comprising a plurality of memory cells;
at least one bit line;
a column word line;
a plurality of column switches, each of the column switches having a control terminal coupled to the column word line; and
a plurality of row switches, each of the row switches having a control terminal coupled to a different one of the plurality of row word lines;
wherein each of the column switches and each of the row switches are coupled in series between the at least one bit line and the plurality of memory cells of one of the memory cell groups.
2. The memory device of claim 1 , wherein the plurality of column switches and the plurality of row switches are transistors.
3. A memory device, comprising:
a plurality of word lines; and
a plurality of memory blocks, each of the memory blocks comprising a plurality of memory units, each of the memory units comprising:
a plurality of memory cell groups, each of the memory cell groups comprising a plurality of memory cells;
at least one bit line;
a column word line; and
a plurality of column switches, each of the column switches having a control terminal coupled to the column word line, a first terminal coupled to one of the memory cell groups, and a second terminal coupled to the at least one bit line,
wherein the column word lines of the memory units of the corresponding memory block are grouped to control the column switches of the corresponding memory block.
4. The memory device of claim 3 , wherein the plurality of column switches are transistors.
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US18/182,382 US20230215479A1 (en) | 2015-08-30 | 2023-03-13 | Low power memory device with column and row line switches for specific memory cells |
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JPH0793974A (en) * | 1993-09-22 | 1995-04-07 | Mitsubishi Electric Corp | Semiconductor memory circuit device |
JP3169814B2 (en) | 1995-10-13 | 2001-05-28 | 日本電気株式会社 | Semiconductor storage device |
US6094370A (en) * | 1996-06-10 | 2000-07-25 | Kabushiki Kaisha Toshiba | Semiconductor memory device and various systems mounting them |
US6058065A (en) * | 1998-05-21 | 2000-05-02 | International Business Machines Corporation | Memory in a data processing system having improved performance and method therefor |
JP3853981B2 (en) | 1998-07-02 | 2006-12-06 | 株式会社東芝 | Manufacturing method of semiconductor memory device |
JP3856596B2 (en) * | 1999-05-28 | 2006-12-13 | 富士通株式会社 | Semiconductor memory device |
JP2003273252A (en) * | 2002-03-12 | 2003-09-26 | Mitsubishi Electric Corp | Semiconductor memory device |
JP2003308698A (en) | 2002-04-12 | 2003-10-31 | Toshiba Corp | Nonvolatile semiconductor memory |
US7061792B1 (en) * | 2002-08-10 | 2006-06-13 | National Semiconductor Corporation | Low AC power SRAM architecture |
US6982902B2 (en) * | 2003-10-03 | 2006-01-03 | Infineon Technologies Ag | MRAM array having a segmented bit line |
JP4264022B2 (en) * | 2004-04-06 | 2009-05-13 | パナソニック株式会社 | Semiconductor integrated circuit device and manufacturing method thereof |
DE602004009078T2 (en) * | 2004-10-15 | 2008-06-19 | Stmicroelectronics S.R.L., Agrate Brianza | memory order |
US7196942B2 (en) | 2004-10-20 | 2007-03-27 | Stmicroelectronics Pvt. Ltd. | Configuration memory structure |
JP4713143B2 (en) * | 2004-12-15 | 2011-06-29 | 富士通セミコンダクター株式会社 | Semiconductor memory device |
TWI562380B (en) * | 2005-01-28 | 2016-12-11 | Semiconductor Energy Lab Co Ltd | Semiconductor device, electronic device, and method of manufacturing semiconductor device |
WO2007004253A1 (en) * | 2005-06-30 | 2007-01-11 | Spansion Llc | Nonvolatile memory device and method for controlling nonvolatile memory device |
US7872892B2 (en) | 2005-07-05 | 2011-01-18 | Intel Corporation | Identifying and accessing individual memory devices in a memory channel |
US7729155B2 (en) * | 2005-12-30 | 2010-06-01 | Stmicroelectronics Pvt. Ltd. | High speed, low power, low leakage read only memory |
JP2007273007A (en) | 2006-03-31 | 2007-10-18 | Fujitsu Ltd | Semiconductor memory device |
KR100745376B1 (en) | 2007-05-22 | 2007-08-02 | 삼성전자주식회사 | Semiconductor memory device having advanced data input/output path |
US7978518B2 (en) * | 2007-12-21 | 2011-07-12 | Mosaid Technologies Incorporated | Hierarchical common source line structure in NAND flash memory |
US8130528B2 (en) | 2008-08-25 | 2012-03-06 | Sandisk 3D Llc | Memory system with sectional data lines |
US8004899B2 (en) * | 2009-03-05 | 2011-08-23 | Macronix International Co., Ltd. | Memory array and method of operating a memory |
JP2010277634A (en) | 2009-05-28 | 2010-12-09 | Toshiba Corp | Semiconductor memory |
JP5666108B2 (en) * | 2009-07-30 | 2015-02-12 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | Semiconductor device and system including the same |
US8199575B2 (en) * | 2010-01-08 | 2012-06-12 | Macronix International Co., Ltd. | Memory cell array of memory |
KR20110099564A (en) * | 2010-03-02 | 2011-09-08 | 삼성전자주식회사 | Flash memory device for improving repair efficiency and operation method thereof |
US8179735B2 (en) | 2010-03-26 | 2012-05-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Using differential signals to read data on a single-end port |
US8891313B2 (en) * | 2010-10-19 | 2014-11-18 | Macronix International Co., Ltd. | Memory device and read operation method thereof |
WO2012081159A1 (en) | 2010-12-16 | 2012-06-21 | パナソニック株式会社 | Semiconductor memory device |
CN103339680B (en) * | 2011-02-01 | 2016-04-13 | 松下电器产业株式会社 | Nonvolatile semiconductor memory device |
JP5684079B2 (en) * | 2011-09-21 | 2015-03-11 | 株式会社東芝 | Semiconductor memory device |
JP5703200B2 (en) | 2011-12-01 | 2015-04-15 | 株式会社東芝 | Semiconductor memory device |
US8693236B2 (en) | 2011-12-09 | 2014-04-08 | Gsi Technology, Inc. | Systems and methods of sectioned bit line memory arrays, including hierarchical and/or other features |
US8885382B2 (en) | 2012-06-29 | 2014-11-11 | Intel Corporation | Compact socket connection to cross-point array |
JP2014078305A (en) | 2012-10-11 | 2014-05-01 | Toshiba Corp | Semiconductor storage device |
TW201447906A (en) * | 2013-06-11 | 2014-12-16 | Zhi-Cheng Xiao | Semiconductor memory |
TWI493568B (en) * | 2013-08-19 | 2015-07-21 | Ind Tech Res Inst | Memory device |
US8942041B1 (en) * | 2013-10-31 | 2015-01-27 | Windbond Electronics Corp. | Memory device and column decoder for reducing capacitive coupling effect on adjacent memory cells |
US9385054B2 (en) * | 2013-11-08 | 2016-07-05 | Semiconductor Energy Laboratory Co., Ltd. | Data processing device and manufacturing method thereof |
KR102193444B1 (en) * | 2014-04-28 | 2020-12-21 | 삼성전자주식회사 | Semiconductor memory device and memory system including the same |
TWI552162B (en) | 2014-07-31 | 2016-10-01 | Zhi-Cheng Xiao | Low power memory |
KR20160107566A (en) * | 2015-03-04 | 2016-09-19 | 에스케이하이닉스 주식회사 | Resistance Variable Memory Apparatus and Operation Method Thereof |
US20160189755A1 (en) * | 2015-08-30 | 2016-06-30 | Chih-Cheng Hsiao | Low power memory device |
-
2015
- 2015-08-30 US US14/840,037 patent/US20160189755A1/en not_active Abandoned
- 2015-12-04 EP EP15197994.5A patent/EP3136396A1/en not_active Withdrawn
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2016
- 2016-06-15 TW TW105118704A patent/TWI612533B/en active
- 2016-06-28 CN CN202110789914.0A patent/CN113689903A/en active Pending
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- 2016-06-28 CN CN201610483478.3A patent/CN106486149B9/en active Active
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2018
- 2018-04-10 US US15/949,077 patent/US11631446B2/en active Active
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2020
- 2020-02-26 US US16/801,164 patent/US20200194046A1/en not_active Abandoned
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TWI612533B (en) | 2018-01-21 |
CN106486149A (en) | 2017-03-08 |
TW201709202A (en) | 2017-03-01 |
CN106486149B (en) | 2021-08-13 |
US20160189755A1 (en) | 2016-06-30 |
US20200194046A1 (en) | 2020-06-18 |
EP3136396A1 (en) | 2017-03-01 |
US11631446B2 (en) | 2023-04-18 |
CN106486149B9 (en) | 2021-10-01 |
US20180233186A1 (en) | 2018-08-16 |
CN205959618U (en) | 2017-02-15 |
CN113689903A (en) | 2021-11-23 |
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