CN116386693A - Data writing circuit and memory - Google Patents

Data writing circuit and memory Download PDF

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Publication number
CN116386693A
CN116386693A CN202310410904.0A CN202310410904A CN116386693A CN 116386693 A CN116386693 A CN 116386693A CN 202310410904 A CN202310410904 A CN 202310410904A CN 116386693 A CN116386693 A CN 116386693A
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data
array
selection
identification signal
driving module
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CN116386693B (en
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黄克琴
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The present invention relates to a data writing circuit and a memory. The circuit comprises a controller, a multi-stage driving module and a plurality of read-write buffer modules; the controller is used for decoding the writing command to obtain a column address signal, an array selection signal and a writing identification signal; each stage of driving module is used for driving data to be transmitted to the driving module of the next stage and to the data channels of a plurality of storage arrays of the corresponding level according to the writing identification signal or according to the writing identification signal and the selection identification signal of part of the storage arrays in the array selection signal; and each read-write buffer module is used for transmitting the data on the corresponding connected data channel to the corresponding connected storage array according to the write-in identification signal and the selection identification signal of the corresponding connected storage array. The invention can reduce the difficulty of time sequence matching.

Description

Data writing circuit and memory
Technical Field
The present invention relates to the field of integrated circuits, and in particular, to a data writing circuit and a memory.
Background
A dynamic random access memory (english: dynamic Random Access Memory, abbreviated as DRAM) is a semiconductor memory, and the main principle of action is to use the magnitude of stored charges in a capacitor to represent whether a binary bit (english: bit) is 1 or 0.
DRAM is typically arranged in a two-dimensional matrix with one capacitor and one transistor as one cell, and the basic operating mechanism is divided into Read (Read) and Write (english: write). In the conventional art, when writing data, a column control signal, a writing control signal, and a data signal need to be time-aligned (english) so that the data can be correctly written into the memory cell.
However, considering the variation caused by different channel routing, the reserved timing redundancy (english) is very small when performing timing matching. With the continuous increase in DRAM speed and the continuous increase in capacity, timing matching becomes increasingly difficult.
Disclosure of Invention
Based on this, it is necessary to provide a data writing circuit and a memory that can reduce the difficulty of timing matching.
In a first aspect, there is provided a data write circuit, the circuit comprising:
the controller is used for decoding a writing command to obtain a column address signal, an array selection signal and a writing identification signal, wherein the column address signal comprises a column address of a storage unit for writing data in a storage array, the array selection signal comprises a plurality of selection identification signals of the storage array, the selection identification signals are used for indicating whether the corresponding storage array writes the data, and the writing identification signals are used for indicating whether the circuit writes the data;
The multi-stage driving module is used for connecting a plurality of storage arrays of a corresponding level, the driving module of the next stage and the controller; the driving module of each stage is used for driving the data to be transmitted to the driving module of the next stage and to the data channels of a plurality of storage arrays of the corresponding level according to the writing identification signal or according to the writing identification signal and the selection identification signal of part of the storage arrays;
the read-write buffer modules are connected between the storage array and the data channels of the storage array in a one-to-one correspondence manner and are respectively connected with the controller; and each read-write buffer module is used for transmitting the data on the data channel which is correspondingly connected to the storage array which is correspondingly connected according to the write-in identification signal and the selection identification signal of the storage array which is correspondingly connected.
The data writing circuit comprises a controller, a multistage driving module and a plurality of read-write buffer modules, wherein the controller obtains a column address signal, an array selection signal and a write-in identification signal through decoding of a write-in command, the column address signal comprises a column address of a storage unit to be written with data in a storage array, the array selection signal comprises respective selection identification signals of a plurality of storage arrays, the selection identification signal is used for indicating whether the corresponding storage array is written with data, the write-in identification signal is used for indicating whether the circuit is written with data, and when the data is written, only the array selection signal is needed to be matched with the data signal in a time sequence, so that the difficulty of time sequence matching can be effectively reduced.
And each stage of driving module is connected with the multiple storage arrays of the corresponding level, the driving module of the next stage and the controller, and can drive data to be transmitted to the driving module of the next stage and the data channels of the multiple storage arrays of the corresponding level according to the writing identification signals and the selection identification signals of part of the storage arrays in the array selection signals. And the plurality of read-write buffer modules are connected between the storage arrays and the data channels of the storage arrays in a one-to-one correspondence manner and are respectively connected with the controller, and each read-write buffer module can transmit data on the corresponding connected data channel to the corresponding connected storage array according to the write identification signal and the selection identification signal of the corresponding connected storage array. Therefore, under the control of the array selection signal and the writing identification signal, data can be written into the target storage array, and correct writing of the data is realized.
In one embodiment, the driving module after the first stage is configured to obtain the selection identification signal of the storage array before or after the corresponding level from the array selection signal, and drive the data to be transmitted to the driving module of the next stage and to the data channels of the plurality of storage arrays of the corresponding level according to the obtained selection identification signal and the writing identification signal.
In one embodiment, the driving module after the first stage is configured to obtain the selection identification signal of the storage array before the corresponding level from the array selection signal if the driving module is located in the first half of the multi-stage driving module; and if the storage array is positioned at the second half part of the multi-stage driving module, acquiring the selection identification signals of the storage array after the corresponding level from the array selection signals.
In one embodiment, the driving module in the first half is configured to logically and the write identification signal with the obtained inverse value of each of the selection identification signals, and when the result of the logical and is a target state, drive the data to be transmitted to the driving module in the next stage and to be transmitted to the data channels of the plurality of storage arrays in the corresponding hierarchy;
the driving module in the second half part is used for logically ANDed the writing identification signal with the obtained result of each selection identification signal logical OR, and driving the data to be transmitted to the driving module in the next stage and the data channels of a plurality of storage arrays in the corresponding level when the result of the logical OR is the target state.
In one embodiment, each read-write buffer module is configured to receive the selection identification signal of the corresponding connected storage array, logically and the write identification signal and the received selection identification signal, and transmit the data on the corresponding connected data channel to the corresponding connected storage array when the result of the logical and is a target state.
In one embodiment, the circuit further comprises:
the column address control modules are connected with the storage arrays in a one-to-one correspondence manner and are respectively connected with the controllers; each column address control module is used for receiving the selection identification signal of the corresponding connected storage array and controlling the data to be written into bit lines represented by the column address signals in the corresponding connected storage array according to the received selection identification signal.
In a second aspect, there is provided a data writing circuit, the circuit comprising:
the controller is used for decoding a writing command to obtain a column address signal and an array selection signal, wherein the column address signal comprises column addresses of storage units to be written with data in a storage array, the array selection signal comprises a plurality of selection identification signals of the storage arrays, and the selection identification signals are used for indicating whether the corresponding storage arrays write the data;
The multi-stage driving module is used for connecting a plurality of storage arrays of a corresponding level, the driving module of the next stage and the controller; the driving module of the first stage is used for driving the data to be transmitted into the driving module of the next stage and to be transmitted to the data channels of the storage arrays of the corresponding level; the driving module after the first stage is used for driving the data to be transmitted to the driving module of the next stage and to be transmitted to the data channels of a plurality of storage arrays of the corresponding level according to the selection identification signals of part of the storage arrays in the array selection signals;
the read-write buffer modules are connected between the storage array and the data channels of the storage array in a one-to-one correspondence manner and are respectively connected with the controller; and each read-write buffer module is used for transmitting the data on the data channel which is correspondingly connected to the storage array which is correspondingly connected according to the selection identification signal of the storage array which is correspondingly connected.
The data writing circuit comprises a controller, a multistage driving module and a plurality of read-write buffer modules, wherein the controller obtains a column address signal and an array selection signal through decoding of a writing command, the column address signal comprises a column address of a storage unit for writing data in a storage array, the array selection signal comprises a selection identification signal of each of a plurality of storage arrays, the selection identification signal is used for indicating whether the corresponding storage array writes the data, and when the data is written, only the array selection signal is needed to be subjected to time sequence matching with the data signal, so that the difficulty of time sequence matching can be effectively reduced.
And each stage of driving module is connected with the multiple storage arrays of the corresponding level, the driving module of the next stage and the controller, the driving module of the first stage can drive data to be transmitted to the driving module of the next stage and the data channels of the multiple storage arrays of the corresponding level, and the driving module after the first stage can drive the data to be transmitted to the driving module of the next stage and the data channels of the multiple storage arrays of the corresponding level according to the selection identification signals of part of the storage arrays in the array selection signals. And the plurality of read-write buffer modules are connected between the storage arrays and the data channels of the storage arrays in a one-to-one correspondence manner and are respectively connected with the controller, and each read-write buffer module can transmit the data on the corresponding connected data channel to the corresponding connected storage array according to the selection identification signal of the corresponding connected storage array. Therefore, under the control of the array selection signal, data can be written into the target storage array, and correct writing of the data is realized.
In one embodiment, the controller is further configured to decode a write command to obtain a write identification signal; or alternatively, the process may be performed,
generating a write identification signal according to the array selection signal;
Wherein the write identification signal is used to indicate whether the circuit writes the data; the driving module of the first stage is used for driving the data to be transmitted to the driving module of the next stage and to the data channels of the storage arrays of the corresponding level according to the writing identification signal.
In one embodiment, the driving module after the first stage is configured to obtain the selection identification signal of the storage array before or after the corresponding level from the array selection signal, and drive the data to be transmitted to the driving module of the next stage and to the data channels of the plurality of storage arrays of the corresponding level according to the obtained selection identification signal and the writing identification signal.
In a third aspect, there is provided a memory comprising a plurality of memory arrays and a data write circuit as provided in the first or second aspect.
The memory comprises a plurality of memory arrays and the data writing circuit, so that the correct writing of data can be realized, and the data can be written only by performing time sequence matching on array selection signals and data signals, thereby effectively reducing the difficulty of time sequence matching.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a related art data writing circuit;
FIG. 2 is a schematic diagram of a data writing circuit according to an embodiment;
FIG. 3 is a schematic diagram of a data writing circuit according to an embodiment;
FIG. 4 is a schematic diagram of a memory according to an embodiment.
Reference numerals illustrate:
110. the device comprises a data module, 120, a controller, 130, a storage array, 140, a decoder, 150, a driving module, 160, a column address control module, 170 and a read-write buffer module;
200. the data writing circuit 210, the controller 220, the driving module 230, the read-write buffer module 240, the storage array 250, the column address control module 290 and the data module;
300. the data writing circuit 310, the controller 320, the driving module 330, the read-write buffer module 340, the storage array 350, the column address control module 390 and the data module;
410. Memory array 420, data write circuit.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Examples of the present application are given in the accompanying drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that the terms "first," "second," and the like, as used herein, may be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first resistance may be referred to as a second resistance, and similarly, a second resistance may be referred to as a first resistance, without departing from the scope of the present application. Both the first resistor and the second resistor are resistors, but they are not the same resistor.
It is to be understood that in the following embodiments, "connected" is understood to mean "electrically connected", "communicatively connected", etc., if the connected circuits, modules, units, etc., have electrical or data transfer between them.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof. Also, the term "and/or" as used in this specification includes any and all combinations of the associated listed items.
DRAM is typically arranged in a two-dimensional matrix with one capacitor and one transistor as one cell. The gate of the transistor is electrically connected to a Word Line (WL), the source of the transistor is electrically connected to a Bit Line (BL), and the drain of the transistor is electrically connected to a capacitor. The transistor is controlled to be turned on and off by a voltage on a word line, so that data information stored in the capacitor is read through a bit line or written into the capacitor.
When the DRAM is read, the BL is charged to half of the operation voltage, and then the transistor is turned on to generate the charge sharing phenomenon between the BL and the capacitor. If the internally stored value is 1, the BL voltage will be raised by charge sharing to above half the operating voltage; if the internally stored value is 0, the BL voltage is pulled down to less than half the operating voltage. After the voltage of BL is obtained, half of the operation voltage is used as the reference voltage to be amplified, and whether the internal storage value is 0 or 1 can be judged. When the DRAM is written, the transistor is directly turned on. If the write is 1, raising the voltage of the BL to the operating voltage so that the operating voltage is stored on the capacitor; if 0 is written, the voltage of BL is reduced to 0 to make the amount of charge inside the capacitor smaller to characterize data 0.
The above-described writing process is realized by a data writing circuit. Fig. 1 is a schematic diagram of a data writing circuit in the related art, as shown in fig. 1, a data module 110 and a Controller (english: controller) 120 are disposed on the same side of a plurality of memory arrays (english: array) 130, and the plurality of memory arrays 130 are arranged in a plurality of levels along a direction away from the data module 110 and the Controller 120. Each stage is provided with a Decoder 140 and a driving module 150, and each memory array 130 is provided with a column address control module (english: column address control) 160 and a read/write buffer module (english: read/write buffer) 170.
In data writing, the data module 110 transmits a data signal to the driving module 150 of the first stage, and the driving module 150 of each stage can drive the data channel of each storage array 130 of the same hierarchy to transmit the data signal, and the driving module 150 of the next stage. The read/write buffer module 170 of each memory array 130 may receive data signals from a corresponding data channel.
The controller 120 transmits the write control signal wrBnk and the write address signal wrBnkAdr <2:0> to the decoder 140 of the first stage, and the decoder 140 of each stage transmits the write control signal wrBnk and the write address signal wrBnkAdr <2:0> to the decoder 140 of the next stage, so that the decoder 140 of each stage receives the write control signal wrBnk and the write address signal wrBnkAdr <2:0>. The decoder 140 of each stage transmits the received write control signal wrbn to the driving module 150 of the same level, so that the driving module 150 drives the data channel of each memory array 130 of the same level and the driving module 150 of the next stage according to the write control signal wrbn. The decoder 140 of each stage also transmits the received write address signals WrBnkAdr <2:0> to the read-write buffer modules 170 of the respective memory arrays 130 of the same hierarchy, such that the read-write buffer modules 170 receive data signals from the corresponding data channels according to the write address signals WrBnkAdr <2:0>.
In addition, the controller 120 decodes the write command (English: write command) to obtain the cell enable signals (English: bank enable signal) ColBnk <7:0> and the column address signals (English: column address signal) ColAdr <9:4>, and transmits the cell enable signals ColBnk <7:0> and the column address signals ColAdr <9:4> to the column address control module 160 of each memory array 130. The cell enable signals ColBnk <7:0> are used to select a target memory array of the plurality of memory arrays 130 to be written with data, and control the column address control module 160 of the target memory array to operate. The column address control module 160 of the target memory array decodes the column address signals ColAdr <9:4> to obtain column address information, so that the data signals received by the read-write buffer module 170 are written into the bit lines represented by the column address information. That is, the column address control module 160 decodes the column address signals ColAdr <9:4> according to the cell enable signals colBnk <7:0> to obtain column address information, and the target memory array writes the data signals received by the read-write buffer module 170 into the bit lines represented by the column address information.
Therefore, in the related art, the data signal, the write control signal wrBnk, the write address signal wrBnkAdr <2:0>, the cell enable signal ColBnk <7:0>, and the column address signal ColAdr <9:4> all need to be time-matched so that data can be written correctly. However, in consideration of the variation caused by different channel wirings, the reserved time sequence redundancy is very small when the time sequence matching is performed, so that the time sequence matching of many signals is difficult.
Based on the above, the present application provides a data write circuit. Fig. 2 is a schematic diagram of a data writing circuit according to an embodiment of the present application, and as shown in fig. 2, the data writing circuit 200 includes a controller 210, a multi-stage driving module 220, and a plurality of read-write buffer modules 230.
The controller 210 is configured to decode a write command to obtain column address signals ColAdr <9:4>, array selection signals CAC <7:0>, and write identification signals WrtFlg. Column address signals ColAdr <9:4> characterize the column addresses of the memory cells in the memory array 240 to which data is to be written. The array selection signal CAC <7:0> characterizes a selection identification signal of each of the plurality of memory arrays 240, such as CAC <0>, CAC <1>, CAC <2>, CAC <3>, CAC <4>, CAC <5>, CAC <6>, CAC <7>, the selection identification signal being used to indicate whether the corresponding memory array 240 is writing data, the write identification signal WrtFlg being used to indicate whether the circuit is writing data, the write identification signal WrtFlg being generated based on the array selection signal CAC <7:0>, e.g. the write identification signal WrtFlg being either the result of the array selection signal CAC <7:0>, or the write identification signal WrtFlg and the array selection signal CAC <7:0> being also decoded simultaneously based on another signal, i.e. the write identification signal WrtFlg and the array selection signal CAC <7:0 >.
Each level of driving modules 220 is used to connect the storage array 240 of the corresponding level, the driving module 220 of the next level, and the controller 210. Each stage of driving module 220 is configured to drive data to be transmitted to the next stage of driving module 220 and to the data channels of the plurality of storage arrays 240 of the corresponding hierarchy according to the write identification signal WrtFlg or according to the write identification signal WrtFlg and the selection identification signal of the partial storage arrays 240 of the array selection signal CAC <7:0 >.
The read-write buffer module 230 is connected in series between the corresponding memory array 240 and the data channel of the memory array 240 and is connected to the controller 210. Each read-write buffer module 230 is configured to transmit data on the corresponding connected data channel to the corresponding connected storage array 240 according to the write identification signal WrtFlg and the selection identification signal of the corresponding connected storage array 240.
The data writing circuit 200 includes a controller 210, a multi-stage driving module 220, and a plurality of read-write buffer modules 230, where the controller 210 decodes a write command to obtain column address signals ColAdr <9:4>, array selection signals CAC <7:0>, and write identification signals wrtfrg, the column address signals ColAdr <9:4> include column addresses of memory cells to be written with data in the memory array 240, the array selection signals CAC <7:0> include respective selection identification signals of the plurality of memory arrays 240, the selection identification signals are used to indicate whether the corresponding memory array 240 writes with data, the write identification signals wrtfrg are used to indicate whether the data channels write with data, and the number of signals that need to be time-sequence matched is reduced when the data is written only by time-sequence matching the array selection signals CAC <7:0>, which is beneficial to reducing difficulty of time-sequence matching.
And each stage of driving module 220 is connected to the multiple storage arrays 240 of the corresponding level, the driving module 220 of the next stage and the controller 210, and can drive data to be transmitted to the driving module 220 of the next stage and to the data channels of the multiple storage arrays 240 of the corresponding level according to the write identification signal WrtFlg and the selection identification signal of part of the storage arrays 240 of the array selection signal CAC <7:0 >. Each read-write buffer module 230 is connected in series between the corresponding memory array 240 and the data channel of the memory array 240 and is respectively connected to the controller 210, and each read-write buffer module 230 can transmit the data on the corresponding connected data channel to the corresponding connected memory array 240 according to the write identification signal WrtFlg and the selection identification signal of the corresponding connected memory array 240. Thus, under the control of the array selection signals CAC <7:0> and the write identification signals WrtFlg, data can be written into the target storage array, and correct writing of the data is realized.
In addition, compared with the related art, the method is equivalent to combining the write control signal wrBnk, the write address signal wrBnkAdr <2:0>, and the cell enable signal ColBnk <7:0> into the array selection signal CAC <7:0>, i.e. the array selection signal CAC <7:0> is adopted to replace the write control signal wrBnk, the write address signal wrBnkAdr <2:0>, and the cell enable signal ColBnk <7:0> in the related art to realize corresponding functions. By setting the write identification signal WrtFlg to generate or set homology based on the array selection signal CAC <7:0>, the timing matching of the write identification signal WrtFlg and the array selection signal CAC <7:0> is guaranteed, the write identification signal WrtFlg is easier to match with the data signal in timing, and the situation of timing mismatch is improved. And the number of wires can be reduced, which is more beneficial to layout design and size reduction.
Illustratively, as shown in fig. 2, the controller 210 and the data module 290 are disposed on the same side of the plurality of storage arrays 240, the plurality of storage arrays 240 are arranged in multiple stages in a direction away from the data module 290 and the controller 210, and each stage is provided with a plurality of storage arrays 240 and one driving module 220, and each storage array 240 is correspondingly provided with one read-write buffer module 230.
The controller 210 may include a decoder to decode the write command into column address signals ColAdr <9:4>, array select signals CAC <7:0> and write identification signals WrtFlg. The driving module 220 may be composed of a plurality of cascaded inverters to drive data to be transferred into the driving module 220 of the next stage and onto the data channels of the plurality of memory arrays 240 of the corresponding hierarchy. The driving module 220 may further include a switching tube to control driving according to the write identification signal WrtFlg; alternatively, the driving module 220 may further include a switching tube and a logic gate circuit to control driving according to the write identification signal WrtFlg and the selection identification signal of the partial memory array 240 of the array selection signal CAC <7:0 >. The read/write buffer module 230 may include a switching transistor and a logic gate circuit to transfer data on the corresponding connected data channel to the corresponding connected memory array 240 according to the write identification signal WrtFlg and the selection identification signal of the corresponding connected memory array 240.
Optionally, the driving module 320 of the first stage is configured to transmit driving data to the driving module 220 of the next stage and to data channels of the plurality of storage arrays 240 of the corresponding hierarchy according to the write identification signal WrtFlg.
The driving module 320 after the first stage is configured to drive data to be transferred to the driving module 220 of the next stage and to data channels of the plurality of storage arrays 240 of the corresponding hierarchy according to the write identification signal WrtFlg and the selection identification signal of the partial storage arrays 240 of the array selection signal CAC <7:0 >.
In one embodiment, as shown in fig. 2, the driving module 220 after the first stage is configured to obtain the selection identification signal of the storage array 240 before or after the corresponding level from the array selection signal CAC <7:0>, and transmit the driving data to the driving module 220 of the next stage and to the data channels of the plurality of storage arrays 240 of the corresponding level according to the obtained selection identification signal and the write identification signal WrtFlg.
In the above embodiment, with the related art in which the write address signal WrBnkAdr <2:0> is sequentially transmitted to the decoder 140 of each stage, the driving module 220 of each stage in the present application does not obtain the whole array selection signal CAC <7:0>, but obtains a part of the selection identification signals in the array selection signal CAC <7:0> according to the selection identification signals required by each stage, so that the number of the selection identification signals transmitted to the driving module 220 of each stage can be reduced, and different signals do not need to be set to distinguish and control the read-write buffer module 230 and the column address control module, thereby reducing the difficulty of timing matching.
In addition, since the selection identification signal is used to indicate whether or not the corresponding memory array 240 writes data, there is a correspondence relationship between the selection identification signal and the hierarchy. The selection identification signals of the storage array 240 before or after the corresponding level are obtained from the array selection signals CAC <7:0>, and the required selection identification signals can be obtained according to the positions of the levels, so that data can be transmitted to the correct level.
In one embodiment, as shown in fig. 2, the driving module 220 after the first stage is configured to obtain the selection identification signal of the storage array 240 before the corresponding stage from the array selection signals CAC <7:0> if the driving module 220 is located at the first half of the multi-stage driving module 220; if the memory array is located in the second half of the multi-stage driving module 220, the selection identification signal of the memory array 240 after the corresponding stage is obtained from the array selection signals CAC <7:0 >.
In the above embodiment, if the driving module 220 after the first stage is located at the first half of the multi-stage driving module 220, the selection identification signal of the memory array 240 before the corresponding stage is obtained from the array selection signals CAC <7:0 >; if the data is located in the second half of the multi-stage driving module 220, the selection identification signals of the storage array 240 after the corresponding stage are obtained from the array selection signals CAC <7:0>, so that the number of selection identification signals transmitted to the driving modules 220 of each stage can be reduced as much as possible, and the required selection identification signals are obtained, thereby transmitting the data to the correct stage.
For example, as shown in fig. 2, eight memory arrays 240 are arranged in four stages in a direction away from the data module 290 and the controller 210, each stage being provided with two memory arrays 240 and one driving module 220. The second stage of driving modules 220 is located in the first half of the four stages of driving modules 220, and the selection identification signal of the first stage of memory array 240 is obtained from the array selection signals CAC <7:0 >. The third stage drive module 220 is located in the second half of the fourth stage drive module 220, and the selection identification signals of the third and fourth stage memory arrays 240 are obtained from the array selection signals CAC <7:0 >. The fourth stage driving module 220 is located at the second half of the fourth stage driving module 220, and obtains the selection identification signal of the fourth stage memory array 240 from the array selection signals CAC <7:0 >.
Illustratively, as shown in fig. 2, the first half driving module 220 is configured to logically and the write identification signal WrtFlg and the obtained inverse value of each selection identification signal, and when the result of the logical and is the target state, drive data is transmitted to the driving module 220 of the next stage and to the data channels of the plurality of storage arrays 240 of the corresponding hierarchy.
The second driving module 220 is configured to logically and the write identification signal WrtFlg with the obtained logical or result of each selection identification signal, and transmit driving data to the driving module 220 at the next stage and to the data channels of the multiple storage arrays 240 at the corresponding level when the logical or result is the target state.
In the above embodiment, if the driving module 220 is located in the first half of the multi-stage driving module 220, the driving module 220 obtains the selection identification signal of the storage array 240 before the corresponding stage from the array selection signal CAC <7:0>, at this time, if the corresponding stage of the storage array 240 to be written with data is located before the corresponding stage of the driving module 220, the selection identification signal obtained by the driving module 220 is the enabling level, the driving module 220 performs the logical and of the writing identification signal WrtFlg and the obtained inverse value of each selection identification signal to obtain a result that is not the target state, and the driving data is not transmitted to the driving module 220 of the next stage and the data channels of the plurality of storage arrays 240 of the corresponding stage. If the corresponding level of the storage array 240 to be written with data is located after the corresponding level of the driving module 220, the selection identification signal acquired by the driving module 220 is at the sleep level, and the result obtained by logically and-ing the writing identification signal WrtFlg and the inverse value of each acquired selection identification signal by the driving module 220 is in the target state, so that the driving module can drive the data to be transmitted to the driving module 220 at the next stage and the data channels of the plurality of storage arrays 240 at the corresponding level. It can be seen that the driving module 220 in the first half logically and-sums the write identification signal WrtFlg and the obtained inverse value of each selection identification signal, and drives when the result of the logical and is the target state, so that data can be transmitted to the correct hierarchy.
Similarly, if the driving module 220 is located in the second half of the multi-stage driving module 220, the driving module 220 obtains the selection identification signals of the storage arrays 240 after the corresponding stage from the array selection signals CAC <7:0>, and if the corresponding stage of the storage array 240 to be written with data is located before the corresponding stage of the driving module 220, the selection identification signals obtained by the driving module 220 are at the sleep level, the result obtained by logically and-ing the writing identification signal WrtFlg and the obtained result of each selection identification signal is not the target state, and the data is not driven to be transmitted to the driving module 220 of the next stage and the data channels of the plurality of storage arrays 240 of the corresponding stage. If the corresponding level of the storage array 240 to be written with data is located after the corresponding level of the driving module 220, the selection identification signal acquired by the driving module 220 is an enabling level, so that the data can be driven to be transmitted to the driving module 220 at the next stage and to the data channels of the plurality of storage arrays 240 at the corresponding level. It can be seen that the driving module 220 in the second half logically and-sums the write identification signal WrtFlg and the obtained result of each selection identification signal logical or, and when the result of the logical or is the target state, the driving data is transmitted to the driving module 220 in the next stage and the data channels of the plurality of storage arrays 240 in the corresponding hierarchy, so that the data can be transmitted to the correct hierarchy.
For example, as shown in fig. 2, the second stage driving module 220 is located at the first half of the four stage driving module 220, and logically and sums the write identification signal WrtFlg with the inverse of the selection identification signals CAC <0>, CAC <4> of the first stage memory array 240. The third level driving module 220 is located at the second half of the fourth level driving module 220, and logically ANDes the write identification signal WrtFlg with the selection identification signals CAC <2>, CAC <6> of the third level memory array 240, and the results of the logical OR of the selection identification signals CAC <3>, CAC <7> of the fourth level memory array 240. The fourth stage driver module 220 is located in the second half of the fourth stage driver module 220, and logically ANDs the write identification signal WrtFlg with the results of the logical OR of the select identification signals CAC <3>, CAC <7> of the fourth stage memory array 240.
Alternatively, the logic gates in the first half of the driving module 220 may include a plurality of not gates and at least one and gate, and the logic gates in the second half of the driving module 220 may include at least one or gate and one and gate.
Illustratively, as shown in fig. 2, each read-write buffer module 230 is configured to receive a selection identification signal of the corresponding connected storage array 240, logically and the write identification signal WrtFlg with the received selection identification signal, and transmit data on the corresponding connected data channel to the corresponding connected storage array 240 when the result of the logical and is a target state. In other embodiments, each read-write buffer module 230 receives only the corresponding selection identification signal, and does not receive the write identification signal WrtFlg, and whether to perform data writing is determined by whether the selection identification signal is in the target state.
In the above embodiment, if the storage array 240 is the storage array 240 to be written with data, the selection identification signal of the storage array 240 is the enable level, and at this time, the read-write buffer module 230 logically and-outputs the write identification signal WrtFlg and the received selection identification signal to the target state, and transmits the data on the data channel correspondingly connected to the storage array 240 correspondingly connected. If the storage array 240 is not the storage array 240 to be written with data, the selection identification signal of the storage array 240 is a sleep level, and the result obtained by logically and-ing the write identification signal WrtFlg and the received selection identification signal by the read-write buffer module 230 is not a target state, and the data on the data channel corresponding to the connection is not transmitted to the storage array 240 corresponding to the connection.
For example, as shown in fig. 2, the first read/write buffer module 230 receives the selection identifier signal CAC <0> of the corresponding connected memory array 240, and logically and the write identifier signal WrtFlg with the received selection identifier signal CAC <0 >. The second read-write buffer module 230 receives the selection identification signal CAC <1> of the corresponding connected memory array 240, logically and … … the write identification signal WrtFlg with the received selection identification signal CAC <1>, and the eighth read-write buffer module 230 receives the selection identification signal CAC <7> of the corresponding connected memory array 240, logically and-sums the write identification signal WrtFlg with the received selection identification signal CAC <7 >.
Optionally, the logic gates in the read/write buffer module 230 may include at least one and gate.
In one embodiment, as shown in FIG. 2, data write circuit 200 further includes a plurality of column address control modules 250. The plurality of column address control modules 250 are used for being connected to the memory array 240 in a one-to-one correspondence and respectively connected to the controller 210. Each column address control module 250 is configured to receive a selection identification signal of the corresponding connected storage array 240, and control data to be written into the bit lines characterized by column address signals ColAdr <9:4> in the corresponding connected storage array 240 according to the received selection identification signal.
In the above embodiment, the data writing circuit 200 correspondingly sets the column address control module 250 for each memory array 240, and the column address control module 250 receives the selection identification signal of the corresponding connected memory array 240 and controls the data to be written into the bit lines characterized by the column address signals ColAdr <9:4> in the corresponding connected memory array 240 according to the received selection identification signal, so that the data can be further written into the correct bit lines.
For example, as shown in FIG. 2, the first column address control module 250 receives a select identity signal CAC <0> for the corresponding connected memory array 240. The second column address control module 250 receives the select identity signal CAC <1> … … of the corresponding connected memory array 240 and the eighth column address control module 250 receives the select identity signal CAC <7> of the corresponding connected memory array 240.
Alternatively, the column address control module 250 may include a switching tube.
Based on the same inventive concept, the application also provides a data writing circuit. Fig. 3 is a schematic diagram of a data writing circuit according to an embodiment of the present application, and as shown in fig. 3, the data writing circuit 300 includes a controller 310, a multi-stage driving module 320, and a plurality of read-write buffer modules 330.
The controller 310 is configured to decode the write command to obtain column address signals ColAdr <9:4> and array select signals CAC <7:0>. The column address signals ColAdr <9:4> include the column addresses of the memory cells in the memory array 340 to which data is to be written. The array select signals CAC <7:0> include select identification signals for each of the plurality of memory arrays 340, such as CAC <0>, CAC <1>, CAC <2>, CAC <3>, CAC <4>, CAC <5>, CAC <6>, and CAC <7>, the select identification signals indicating whether the corresponding memory array 240 is writing data.
Each level of driving modules 320 is used to connect a plurality of storage arrays 340 of a corresponding hierarchy, the driving module 320 of the next level, and the controller 310. The driving module 320 of the first stage is used for driving data to be transmitted to the driving module 320 of the next stage and to the data channels of the plurality of storage arrays 340 of the corresponding hierarchy. The driving module 320 after the first stage is configured to drive data to be transmitted to the driving module 320 of the next stage and to data channels of the plurality of memory arrays 340 of the corresponding hierarchy according to the selection identification signals of the partial memory arrays 340 of the array selection signals CAC <7:0>.
The read-write buffer modules 330 are used for being connected between the storage arrays 340 and the data channels of the storage arrays 340 in a one-to-one correspondence manner and are respectively connected with the controller 310. Each read-write buffer module 330 is configured to transmit data on a corresponding connected data channel to the corresponding connected storage array 340 according to the selection identification signal of the corresponding connected storage array 340.
The data writing circuit 300 includes a controller 310, a multi-stage driving module 320, and a plurality of read-write buffer modules 330, where the controller 310 decodes a write command to obtain column address signals ColAdr <9:4> and array selection signals CAC <7:0>, the column address signals ColAdr <9:4> include column addresses of memory cells to be written with data in the memory array 340, the array selection signals CAC <7:0> include respective selection identification signals of the plurality of memory arrays 340, the selection identification signals are used for indicating whether the corresponding memory array 340 writes with data, and when the data is written, only the array selection signals CAC <7:0> and the data signals are needed to be subjected to time sequence matching, so that difficulty of time sequence matching can be effectively reduced.
And each stage of driving module 320 is connected to the multiple storage arrays 340 of the corresponding level, the driving module 320 of the next stage and the controller 310, the driving module 320 of the first stage can drive data to be transmitted to the driving module 320 of the next stage and to the data channels of the multiple storage arrays 340 of the corresponding level, and the driving module 320 after the first stage can drive data to be transmitted to the driving module 320 of the next stage and to the data channels of the multiple storage arrays 340 of the corresponding level according to the selection identification signals of part of the storage arrays 340 of the array selection signals CAC <7:0 >. And the plurality of read-write buffer modules 330 are connected between the storage arrays 340 and the data channels of the storage arrays 340 in a one-to-one correspondence and are respectively connected with the controller 310, each read-write buffer module 330 can transmit the data on the corresponding connected data channel to the corresponding connected storage array 340 according to the selection identification signal of the corresponding connected storage array 340. Thus, under the control of the array selection signal CAC <7:0>, data can be written into the target storage array, and correct writing of the data is realized.
Illustratively, as shown in fig. 3, the controller 310 and the data module 390 are disposed on the same side of the plurality of storage arrays 340, the plurality of storage arrays 340 are arranged in multiple stages along a direction away from the data module 390 and the controller 310, each stage is provided with a plurality of storage arrays 340 and one driving module 320, and each storage array 340 is correspondingly provided with one read-write buffer module 330.
The controller 310 may include a decoder to decode the write command into column address signals ColAdr <9:4> and array select signals CAC <7:0>. The driving module 320 may be composed of a plurality of cascaded inverters to drive data to be transferred into the driving module 320 of the next stage and onto the data channels of the plurality of memory arrays 340 of the corresponding hierarchy. The driving module 320 after the first stage may further include a switching transistor and a logic gate circuit to control driving according to a selection identification signal of a part of the memory array 340 in the array selection signal CAC <7:0>. The read/write buffer module 330 may include a switching tube to transmit data on the corresponding connected data channel to the corresponding connected storage array 340 according to the selection identification signal of the corresponding connected storage array 340.
In one embodiment, the controller 310 is further configured to decode the write command to obtain the write identification signal WrtFlg and the array selection signal CAC <7:0> simultaneously; alternatively, the write identification signal WrtFlg is generated based on the array selection signals CAC <7:0>. The write identification signal is used for indicating whether the circuit writes data or not.
Accordingly, the driving module 320 of the first stage is configured to drive data to be transmitted to the driving module 320 of the next stage and to the data channels of the plurality of storage arrays 340 of the corresponding hierarchy according to the write identification signal WrtFlg.
In the above embodiment, by adding the write identification signal WrtFlg, the driving module 320 of the first stage may transmit driving data to the driving module 320 of the next stage and to the data channels of the multiple storage arrays 340 of the corresponding stage according to the write identification signal WrtFlg, so that when no data is written, the driving module 320 of the first stage may not perform driving, and power consumption of the driving module 320 may be reduced.
The array selection signal CAC <7:0> is obtained by decoding a write command, the write identification signal WrtFlg is obtained by decoding the write command, or the write identification signal WrtFlg is generated according to the array selection signal CAC <7:0>, the write identification signal WrtFlg and the array selection signal CAC <7:0> are homologous signals, the problem of time sequence mismatch is avoided, and the difficulty of time sequence matching is not promoted.
Optionally, the driving module 320 after the first stage is configured to obtain the selection identifier signal of the storage array 340 before or after the corresponding level from the array selection signal CAC <7:0>, and drive data to be transmitted to the driving module 320 of the next stage and to the data channels of the plurality of storage arrays 340 of the corresponding level according to the selection identifier signal alone or according to the obtained selection identifier signal and the write identifier signal WrtFlg.
In the above embodiment, similar to the driving module 220, the number of selection identification signals transmitted to the driving modules 320 of each level can be reduced, and different signals do not need to be set to distinguish and control the read-write buffer module 230 and the column address control module, so that the difficulty of timing matching is reduced. In addition, data can be transferred to the correct hierarchy.
In one embodiment, the driving module 320 after the first stage is configured to obtain the selection identification signal of the storage array 340 before the corresponding level from the array selection signals CAC <7:0> if the driving module 320 is located at the first half of the multi-stage driving module 320; if the memory array is located in the second half of the multi-stage driving module 320, the selection identification signal of the memory array 340 after the corresponding stage is obtained from the array selection signals CAC <7:0 >.
In the above embodiment, like the driving module 220, it is possible to reduce the number of selection identification signals transmitted to the driving modules 320 of the respective tiers as much as possible, and acquire the required selection identification signals so as to transmit data to the correct tier.
Illustratively, the first half driving module 320 is configured to logically and the write identification signal WrtFlg with the obtained inverse value of each selection identification signal, and when the result of the logical and is the target state, drive data is transmitted to the next driving module 320 and to the data channels of the multiple storage arrays 340 of the corresponding hierarchy.
The driving module 320 in the second half is configured to logically and the write identification signal WrtFlg with the obtained logical or result of each selection identification signal, and when the logical or result is the target state, drive data is transmitted to the driving module 320 in the next stage and to the data channels of the multiple storage arrays 340 in the corresponding hierarchy.
Alternatively, the logic gates in the first half of the driving modules 320 may include a plurality of not gates and at least one and gate, and the logic gates in the second half of the driving modules 320 may include at least one or gate.
Illustratively, each read-write buffer module 330 is configured to receive a selection identifier signal of the corresponding connected storage array 340, logically and the write identifier signal WrtFlg with the received selection identifier signal, and transmit data on the data channel of the corresponding connection to the corresponding connected storage array 340 when the result of the logical and is a target state.
Optionally, logic gates in the read/write buffer module 330 may include at least one and gate.
In one embodiment, as shown in FIG. 3, data write circuit 300 further includes a plurality of column address control modules 350. The plurality of column address control modules 350 are used for being connected to the memory array 340 in a one-to-one correspondence and respectively connected to the controller 310. Each column address control module 350 is configured to receive a selection identification signal of the corresponding connected storage array 340, and control data to be written into the bit lines characterized by column address signals ColAdr <9:4> in the corresponding connected storage array 340 according to the received selection identification signal.
Alternatively, the column address control module 350 may include a switching tube.
Based on the same inventive concept, the application also provides a memory. Fig. 4 is a schematic diagram of a memory according to an embodiment of the present application, and as shown in fig. 4, the memory includes a plurality of memory arrays 410 and a data write circuit 420. The data writing circuit 420 may be the data writing circuit 200 or the data writing circuit 300.
The memory includes a plurality of memory arrays 410 and the data writing circuit 420, so that correct writing of data can be realized, and only the array selection signals and the data signals need to be subjected to time sequence matching during data writing, so that the difficulty of time sequence matching can be effectively reduced.
In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.

Claims (10)

1. A data write circuit, the circuit comprising:
the controller is used for decoding a writing command to obtain a column address signal, an array selection signal and a writing identification signal, wherein the column address signal comprises a column address of a storage unit for writing data in a storage array, the array selection signal comprises a plurality of selection identification signals of the storage array, the selection identification signals are used for indicating whether the corresponding storage array writes the data, and the writing identification signals are used for indicating whether the circuit writes the data;
the multi-stage driving module is used for connecting a plurality of storage arrays of a corresponding level, the driving module of the next stage and the controller; the driving module of each stage is used for driving the data to be transmitted to the driving module of the next stage and to the data channels of a plurality of storage arrays of the corresponding level according to the writing identification signal or according to the writing identification signal and the selection identification signal of part of the storage arrays;
The read-write buffer modules are connected between the storage array and the data channels of the storage array in a one-to-one correspondence manner and are respectively connected with the controller; and each read-write buffer module is used for transmitting the data on the data channel which is correspondingly connected to the storage array which is correspondingly connected according to the write-in identification signal and the selection identification signal of the storage array which is correspondingly connected.
2. The circuit of claim 1, wherein the driving module after a first stage is configured to obtain the selection identification signal of the memory array before or after a corresponding level from the array selection signal, and drive the data to be transferred into the driving module of a next stage and onto the data channels of the plurality of memory arrays of the corresponding level according to the obtained selection identification signal and the write identification signal.
3. The circuit of claim 2, wherein the drive module after a first stage is configured to obtain the select identification signal of the memory array preceding a corresponding level from the array select signal if located in a first half of the multi-stage drive module; and if the storage array is positioned at the second half part of the multi-stage driving module, acquiring the selection identification signals of the storage array after the corresponding level from the array selection signals.
4. A circuit according to claim 3, wherein the driving module in the first half is configured to logically and the write identification signal with the obtained inverse value of each of the selection identification signals, and drive the data to be transferred to the driving module in the next stage and to be transferred to the data channels of the plurality of memory arrays in the corresponding hierarchy when the result of the logical and is a target state;
the driving module in the second half part is used for logically ANDed the writing identification signal with the obtained result of each selection identification signal logical OR, and driving the data to be transmitted to the driving module in the next stage and the data channels of a plurality of storage arrays in the corresponding level when the result of the logical OR is the target state.
5. The circuit of claim 1, wherein each of the read-write buffer modules is configured to receive the selection identification signal of the corresponding connected storage array, logically and the write identification signal with the received selection identification signal, and transmit the data on the data channel of the corresponding connection to the corresponding connected storage array when the result of the logical and is a target state.
6. The circuit of any one of claims 1-5, wherein the circuit further comprises:
the column address control modules are connected with the storage arrays in a one-to-one correspondence manner and are respectively connected with the controllers; each column address control module is used for receiving the selection identification signal of the corresponding connected storage array and controlling the data to be written into bit lines represented by the column address signals in the corresponding connected storage array according to the received selection identification signal.
7. A data write circuit, the circuit comprising:
the controller is used for decoding a writing command to obtain a column address signal and an array selection signal, wherein the column address signal comprises column addresses of storage units to be written with data in a storage array, the array selection signal comprises a plurality of selection identification signals of the storage arrays, and the selection identification signals are used for indicating whether the corresponding storage arrays write the data;
the multi-stage driving module is used for connecting a plurality of storage arrays of a corresponding level, the driving module of the next stage and the controller; the driving module of the first stage is used for driving the data to be transmitted into the driving module of the next stage and to be transmitted to the data channels of the storage arrays of the corresponding level; the driving module after the first stage is used for driving the data to be transmitted to the driving module of the next stage and to be transmitted to the data channels of a plurality of storage arrays of the corresponding level according to the selection identification signals of part of the storage arrays in the array selection signals;
The read-write buffer modules are connected between the storage array and the data channels of the storage array in a one-to-one correspondence manner and are respectively connected with the controller; and each read-write buffer module is used for transmitting the data on the data channel which is correspondingly connected to the storage array which is correspondingly connected according to the selection identification signal of the storage array which is correspondingly connected.
8. The circuit of claim 7, wherein the controller is further configured to decode a write command to obtain a write identification signal; or alternatively, the process may be performed,
generating a write identification signal according to the array selection signal;
wherein the write identification signal is used to indicate whether the circuit writes the data; the driving module of the first stage is used for driving the data to be transmitted to the driving module of the next stage and to the data channels of the storage arrays of the corresponding level according to the writing identification signal.
9. The circuit of claim 8, wherein the driver module after a first stage is configured to obtain the selection identification signal of the memory array before or after a corresponding level from the array selection signal, and drive the data to be transferred into the driver module of a next stage and onto the data channels of the plurality of memory arrays of the corresponding level according to the obtained selection identification signal and the write identification signal.
10. A memory comprising a plurality of memory arrays and a data write circuit as claimed in any one of claims 1 to 9.
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