US20220336435A1 - Memory device with a multiplexed command/address bus - Google Patents
Memory device with a multiplexed command/address bus Download PDFInfo
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- US20220336435A1 US20220336435A1 US17/856,354 US202217856354A US2022336435A1 US 20220336435 A1 US20220336435 A1 US 20220336435A1 US 202217856354 A US202217856354 A US 202217856354A US 2022336435 A1 US2022336435 A1 US 2022336435A1
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Definitions
- FIG. 6 is a schematic diagram of a memory device having two ranks of memory in accordance with an embodiment of the present technology.
- the memory device 600 may be an NVDIMM, or have another alternative module format.
- the memory device 600 includes a plurality of volatile memories 620 (e.g., DRAM memories) arranged in two ranks 621 and 622 , as well as a non-volatile memory 630 (e.g., NAND memory).
- the memory device 600 includes an edge connector 602 for connecting a first data bus 604 and a command/address bus 606 (illustrated in bold lines) to a host device.
- the edge connector 602 may include additional connections for separately controlling the two ranks 621 and 622 of memory (e.g., via two chip select terminals to provide a chip select signal to the memory device 600 in order to enable the desired rank).
- the controller 632 is configured to provide memory command/address signals to the volatile memories 620 through four memory command/address multiplexers 636 , which are configured to route memory command/address signals to the volatile memories 620 from both the drivers 633 a and 633 b of controller 632 and the outputs of the RCD 610 . Accordingly, the drivers 633 a and 633 b of controller 632 may be configured to drive the memory command/address signals at one or more levels specified by the design of the volatile memories 620 (e.g., instead of at a level specified by the design of RCD 610 ).
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- Computer Security & Cryptography (AREA)
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Abstract
A memory device includes a first plurality of volatile memories, a non-volatile memory, and a controller coupled to the non-volatile memory and including a first controller output. The memory device further includes a registering clock driver (RCD) including a first RCD output, and a first multiplexer including a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories. The first multiplexer can be configured to provide command/address signals from one of the RCD and the controller to the first plurality of volatile memories.
Description
- This application is a continuation of U.S. application Ser. No. 17/143,120, filed Jan. 6, 2021; which is a continuation of U.S. application Ser. No. 16/016,111, filed Jun. 22, 2018, now U.S. Pat. No. 10,930,632; which is a continuation of U.S. application Ser. No. 15/656,895, filed Jul. 21, 2017, now U.S. Pat. No. 10,147,712; each of which is incorporated herein by reference in its entirety.
- The present disclosure generally relates to memory devices, and more particularly relates to memory devices with multiplexed command/address busses.
- Memory devices may be provided as modules with standard physical formats and electrical characteristics to facilitate easier installation and deployment across multiple systems. One such module is a dual in-line memory module (DIMM), which is frequently used to provide volatile memory such as DRAM to computing systems. Although DRAM can be fast, and therefore well-suited to use as the main memory of computing systems, it is a volatile memory format and thus requires the continuous application of power to maintain the data stored therein. To address this limitation, other modules can provide both volatile memory (for use as the main memory of a system) and non-volatile memory (for backing up the volatile memory in case of power loss) in a single module. One such module is a non-volatile dual in-line memory module (NVDIMM).
- NVDIMMs require more complex circuitry than is provided on a DIMM, in order to handle the additional tasks an NVDIMM may be called upon to perform (e.g., power loss detection, backup and restore operations, etc.). The additional circuitry can make the design of an NVDIMM more challenging, especially as the capacity (and therefore the number of memory chips) of the modules increases and the electrical characteristics to which the module must conform to meet the demands of a standard format grow ever more stringent.
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FIG. 1 is a schematic diagram of a volatile memory module. -
FIG. 2 is a schematic diagram of a non-volatile memory module. -
FIG. 3 is a schematic diagram of a memory device in accordance with an embodiment of the present technology. -
FIG. 4 is a schematic diagram of a memory device in accordance with an embodiment of the present technology. -
FIG. 5 is a schematic diagram of a memory device in accordance with an embodiment of the present technology. -
FIG. 6 is a schematic diagram of a memory device in accordance with an embodiment of the present technology. -
FIG. 7 is a schematic diagram of a memory device in accordance with an embodiment of the present technology. -
FIG. 8 is a flow chart illustrating a method of operating a memory device in accordance with an embodiment of the present technology. - In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present technology. One skilled in the relevant art, however, will recognize that the disclosure can be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with semiconductor devices are not shown, or are not described in detail, to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to those specific embodiments disclosed herein may be within the scope of the present technology.
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FIG. 1 schematically illustrates a DIMM 100 including a plurality of DRAM memories 120 (e.g., memory dies, memory chips, memory packages or the like). The DIMM 100 includes anedge connector 102 along an edge of a substrate 101 (e.g., a printed circuit board (PCB) or the like) of the DIMM 100 for connecting adata bus 104 and a command/address bus 106 (illustrated in bold lines) to a host device. Thedata bus 104 connects theDRAM memories 120 to theedge connector 102 and receives data signals from and transmits data signals to a connected host during memory access operations (e.g., reads and writes). The DIMM 100 further includes a registering clock driver (RCD) 110 that receives command/address signals from the command/address bus 106 and generates memory command/address signals for theDRAM memories 120. The RCD 110 can present a predictable electrical load (e.g., for matching impedance, reactance, capacitance, etc.) to the host device and can re-drive memory command/address signals to theDRAM memories 120, which helps enable higher densities and increase signal integrity. The RCD 110 may also buffer the command/address signals provided by the host, and then transmit the buffered signals as memory command/address signals to theDRAM memories 120. - An NVDIMM can be configured similarly to the
DIMM 100, with the addition of non-volatile memory and supporting circuitry and devices. One such NVDIMM is illustrated schematically inFIG. 2 . NVDIMM 200 includes both a plurality ofDRAM memories 220 and a non-volatile memory (e.g., FLASH memory 230). The NVDIMM 200 includes anedge connector 202 along an edge of a substrate 201 (e.g., a PCB or the like) of the NVDIMM 200 for connecting adata bus 204 and a command/address bus 206 (illustrated in bold lines) to a host device. Thedata bus 204 connects theDRAM memories 220 to theedge connector 202 and receives data signals from and transmits data signals to a connected host during memory access operations (e.g., reads and writes). The NVDIMM 200 further includes a registering clock driver (RCD) 210 that receives command/address signals from the command/address bus 206 and generates memory command/address signals for theDRAM memories 220. - The NVDIMM 200 further includes a
controller 232 for controlling theFLASH memory 230 and performing memory management operations, such as power loss detection, backup from theDRAM memories 220 to thenon-volatile memory 230, and restore from theFLASH memory 230 to theDRAM memories 220. Thecontroller 232 may include a connection to the edge connector 202 (not shown) to facilitate detection of a power loss event (e.g., by monitoring a voltage of a power supply pin, or via a dedicated pin for sending commands from a connected host to the controller 232). - The
controller 232 is connected to theFLASH memory 230 by anon-volatile bus 234 and to theDRAM memories 220 by thedata bus 204. In this regard, thedata bus 204 may include a number ofdata multiplexers 208 to facilitate connecting theDRAM memories 220 to both the edge connector 202 (e.g., for receiving data signals from and transmitting data signals to a connected host) and to the controller 232 (e.g., for reading data signals from theDRAM memories 220 during a backup operation and transmitting data signals to theDRAM memories 220 during a restore operation). For example, in an embodiment in which each of nineDRAM memories 220 have eight I/O terminals, thedata bus 204 can include eight bus lines connecting eachDRAM memory 220 to thecorresponding data multiplexer 208, eight bus lines connecting eachdata multiplexer 208 to theedge connector 202, and eight bus lines connecting eachdata multiplexer 208 to the controller 232 (e.g., which could be provided with 72 I/O terminals). In another embodiment, a memory module similar to NVDIMM 200 could include a further nineDRAM memories 220 on a back side thereof (for 18total DRAM memories 220, each having four I/O terminals). In such an embodiment, thedata bus 204 could include four bus lines connecting each of the eighteenDRAM memories 220 to a corresponding one of eighteendata multiplexers 208, four bus lines connecting eachdata multiplexer 208 to theedge connector 202, and four bus lines connecting eachdata multiplexer 208 to the controller 232 (e.g., which could be provided with 72 I/O terminals). - The
controller 232 is further connected to the RCD 210, in order to provide command/address signals to theDRAM memories 220 during backup and restore operations. In this regard, the controller can include adriver 233 for sending command/address signals to the RCD 210, through a command/address multiplexer 236 configured to connect the RCD 210 to both theedge connector 202 and thedriver 233 of thecontroller 232. Because the command/address multiplexer 236 of NVDIMM 200 is disposed between the RCD 210 and the edge connector 202 (and thus RCD is not directly connected toedge connector 202 by the command/address bus 206), it can be challenging to ensure that RCD 210 presents a predictable electrical load (e.g., for matching impedance, reactance, capacitance, etc.) to a connected host device. - To facilitate the interchangeability of memory modules conforming to the same standard, it is desirable to provide such modules with the same physical interface (e.g., edge connector design, minimum and maximum physical dimensions, etc.) and electrical interface (e.g., pin layout, circuit impedance, current draw, operating voltage, etc.). One challenge associated with providing non-volatile memory on an NVDIMM, which is designed to the same physical and electrical characteristics of a DIMM, is the challenge of providing a predictable electrical impedance on the command/address bus while accommodating connectivity both to a host device and to an onboard controller. In this regard, matching the impedance of the command/
address bus 206 at theedge connector 202 when a command/address multiplexer 236 is provided between theedge connector 202 and the RCD 210 presents a particular challenge, especially as the memory capacity of a NVDIMM module is increased (e.g., by adding more and/or larger DRAM memories). - Accordingly, several embodiments of data storage devices and computing systems in accordance with the present technology can provide memory modules with a multiplexed command/address bus that overcomes the limitations of conventional memory modules. Several embodiments of the present technology are directed to a memory device comprising a first plurality of volatile memories and a non-volatile memory. The memory device further comprises a controller coupled to the non-volatile memory and including a first controller output, and a registering clock driver (RCD) including a first RCD output, and a first multiplexer. The first multiplexer includes a first mux input coupled to the first RCD output, a second mux input coupled to the first controller output, and a first mux output coupled to the first plurality of volatile memories.
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FIG. 3 is a schematic diagram of a memory device in accordance with an embodiment of the present technology. Thememory device 300 may be an NVDIMM, or may have an alternative module format. Thememory device 300 includes a plurality of volatile memories 320 (e.g., DRAM memories) and a non-volatile memory 330 (e.g., NAND memory). Thememory device 300 includes an external connector (e.g., edge connector 302) for connecting adata bus 304 and a command/address bus 306 (illustrated in bold lines) to a host device. Thedata bus 304 connects thevolatile memories 320 to theedge connector 302 and receives data signals from and transmits data signals to a connected host during memory access operations (e.g., reads and writes). Thememory device 300 further includes a registering clock driver (RCD) 310 that receives command/address signals from the command/address bus 306 and generates memory command/address signals for thevolatile memories 320. TheRCD 310 can present a predictable electrical load (e.g., for matching impedance, reactance, capacitance, etc.) to the host device and can re-drive memory command/address signals to thevolatile memories 320, which helps enable higher densities and increase signal integrity. TheRCD 310 may also buffer the command/address signals provided by the host, and then transmit the buffered signals as memory command/address signals to thevolatile memories 320. - The
memory device 300 further includes acontroller 332 for controlling thenon-volatile memory 330 and performing memory management operations, such as power loss detection, backup from thevolatile memories 320 to thenon-volatile memory 330, and restore from thenon-volatile memory 330 to thevolatile memories 320. Thecontroller 332 may include a connection to the edge connector 302 (not shown) to facilitate detection of a power loss event (e.g., by monitoring a voltage of a power supply pin, or via a dedicated pin for sending commands from a connected host to the controller 332). - The
controller 332 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor. Thecontroller 332 can include a processor configured to execute instructions stored in memory (e.g., embedded memory in thecontroller 332 to store instructions for various processes, logic flows, and routines). - The
controller 332 is connected to thenon-volatile memory 330 by anon-volatile bus 334 and to thevolatile memories 320 by thedata bus 304. In this regard, thedata bus 304 may include a number ofdata multiplexers 308 to facilitate connecting thevolatile memories 320 to both the edge connector 302 (e.g., for receiving data signals from and transmitting data signals to a connected host) and to the controller 332 (e.g., for reading data signals from thevolatile memories 320 during a backup operation and transmitting data signals to thevolatile memories 320 during a restore operation). For example, in an embodiment in which each of nineDRAM memories 320 have eight I/O terminals, thedata bus 304 can include eight bus lines connecting eachDRAM memory 320 to the correspondingdata multiplexer 308, eight bus lines connecting each data multiplexer 308 to theedge connector 302, and eight bus lines connecting each data multiplexer 308 to the controller 332 (e.g., which could be provided with 72 I/O terminals). In another embodiment, a memory module similar to NVDIMM 300 could include a further nineDRAM memories 320 on a back side thereof (for 18total DRAM memories 320, each having four I/O terminals). In such an embodiment, thedata bus 304 could include four bus lines connecting each of the eighteenDRAM memories 320 to a corresponding one of eighteendata multiplexers 308, four bus lines connecting each data multiplexer 308 to theedge connector 302, and four bus lines connecting each data multiplexer 308 to the controller 332 (e.g., which could be provided with 72 I/O terminals). - The
controller 332 is further connected to thevolatile memories 320 so that thecontroller 332 can provide memory command/address signals to thevolatile memories 320 during backup and restore operations. In this regard, the controller can include adriver 333 for sending memory command/address signals to thevolatile memories 320. Rather than providing command/address signals to theRCD 310, however, as in the NVDIMM illustrated inFIG. 2 , thecontroller 332 ofmemory device 300 is configured to provide memory command/address signals to thevolatile memories 320 through two memory command/address multiplexers 336, which are configured to route memory command/address signals to thevolatile memories 320 from both thedriver 333 ofcontroller 332 and the outputs of theRCD 310. Accordingly, thedriver 333 ofcontroller 332 may be configured to drive the memory command/address signals at one or more levels specified by the design of the volatile memories 320 (e.g., instead of at a level specified by the design of RCD 310). - Although in the embodiment illustrated in
FIG. 3 ,controller 332 is shown as including asingle driver 333 for providing command/address signals to all of thevolatile memories 320 of thememory device 300, in other embodiments a controller can have multiple drivers. For example,FIG. 4 is a schematic diagram of a memory device in accordance with an embodiment of the present technology. Thememory device 400 may be an NVDIMM, or have another alternative module format. Thememory device 400 includes a plurality of volatile memories 420 (e.g., DRAM memories) and a non-volatile memory 430 (e.g., NAND memory). Thememory device 400 includes anedge connector 402 for connecting adata bus 404 and a command/address bus 406 (illustrated in bold lines) to a host device. Thedata bus 404 connects thevolatile memories 420 to theedge connector 402 and receives data signals from and transmits data signals to a connected host during memory access operations (e.g., reads and writes). Thememory device 400 further includes a registering clock driver (RCD) 410 that receives command/address signals from the command/address bus 406 and generates memory command/address signals for thevolatile memories 420. TheRCD 410 can present a predictable electrical load (e.g., for matching impedance, reactance, capacitance, etc.) to the host device and can re-drive memory command/address signals to thevolatile memories 420, which helps enable higher densities and increase signal integrity. TheRCD 410 may also buffer the command/address signals provided by the host, and then transmit the buffered signals as memory command/address signals to thevolatile memories 420. - The
memory device 400 further includes acontroller 432 for controlling thenon-volatile memory 430 and performing memory management operations, such as power loss detection, backup from thevolatile memories 420 to thenon-volatile memory 430, and restore from thenon-volatile memory 430 to thevolatile memories 420. Thecontroller 432 may include a connection to the edge connector 402 (not shown) to facilitate detection of a power loss event (e.g., by monitoring a voltage of a power supply pin, or via a dedicated pin for sending commands from a connected host to the controller 432). - The
controller 432 is connected to thenon-volatile memory 430 by anon-volatile bus 434 and to thevolatile memories 420 by thedata bus 404. For simplicity's sake, thememory device 400 ofFIG. 4 is illustrated schematically with separate data buses coupling thevolatile memories 420 to theedge connector 402 and to the controller 432 (e.g., an embodiment in which eachvolatile memory 420 includes an internal DQ mux, with four DQ nets coupled by thedata bus 404 to theedge connector 402, and four DQ nets coupled by thedata bus 404 to thecontroller 432, switched via a mode register setting in the volatile memory 420), those of skill in the art will readily appreciate that different data bus configurations can be used. Thecontroller 432 is further connected to thevolatile memories 420 so that thecontroller 432 can provide memory command/address signals to thevolatile memories 420 during backup and restore operations. In this regard, the controller can includemultiple drivers volatile memories 420. As compared to an embodiment with a single driver, providing multiple drivers can improve the signal integrity of the command/address signals due to the reduced load per driver (albeit at a potentially higher cost and/or complexity). Thecontroller 432 is configured to provide memory command/address signals to thevolatile memories 420 through two memory command/address multiplexers 436, which are configured to route memory command/address signals to thevolatile memories 420 from both thecorresponding driver controller 432 and the outputs of theRCD 410. Accordingly, thedrivers controller 432 may be configured to drive the memory command/address signals at one or more levels specified by the design of the volatile memories 420 (e.g., instead of at a level specified by the design of RCD 410). - Although in the foregoing embodiments, memory devices having RCDs with multiple outputs are shown, in other embodiments an RCD can have other numbers of outputs. For example,
FIG. 5 is a schematic diagram of a memory device in accordance with an embodiment of the present technology, in which an RCD with a single output is provided. Thememory device 500 may be an NVDIMM, or have another alternative module format. Thememory device 500 includes a plurality of volatile memories 520 (e.g., DRAM memories) and a non-volatile memory 530 (e.g., NAND memory). Thememory device 500 includes anedge connector 502 for connecting adata bus 504 and a command/address bus 506 (illustrated in bold lines) to a host device. Thedata bus 504 connects thevolatile memories 520 to theedge connector 502 and receives data signals from and transmits data signals to a connected host during memory access operations (e.g., reads and writes). Thememory device 500 further includes a registering clock driver (RCD) 510 that receives command/address signals from the command/address bus 506 and generates memory command/address signals for thevolatile memories 520. TheRCD 510 can present a predictable electrical load (e.g., for matching impedance, reactance, capacitance, etc.) to the host device and can re-drive memory command/address signals to thevolatile memories 520, which helps enable higher densities and increase signal integrity. TheRCD 510 may also buffer the command/address signals provided by the host, and then transmit the buffered signals as memory command/address signals to thevolatile memories 520. - The
memory device 500 further includes acontroller 532 for controlling thenon-volatile memory 530 and performing memory management operations, such as power loss detection, backup from thevolatile memories 520 to thenon-volatile memory 530, and restore from thenon-volatile memory 530 to thevolatile memories 520. Thecontroller 532 may include a connection to the edge connector 502 (not shown) to facilitate detection of a power loss event (e.g., by monitoring a voltage of a power supply pin, or via a dedicated pin for sending commands from a connected host to the controller 532). - The
controller 532 is connected to thenon-volatile memory 530 by anon-volatile bus 534 and to thevolatile memories 520 by thedata bus 504. For simplicity's sake, thememory device 500 ofFIG. 5 is illustrated schematically with separate data buses coupling thevolatile memories 520 to theedge connector 502 and to thecontroller 532, those of skill in the art will readily appreciate that different data bus configurations can be used. Thecontroller 532 is further connected to thevolatile memories 520 so that thecontroller 532 can provide memory command/address signals to thevolatile memories 520 during backup and restore operations. In this regard, the controller can include adriver 533 for sending memory command/address signals to thevolatile memories 520. Thecontroller 532 is configured to provide memory command/address signals to thevolatile memories 520 through a memory command/address multiplexer 536, which is configured to route memory command/address signals to thevolatile memories 520 from both thedriver 533 ofcontroller 532 and the outputs of theRCD 510. Accordingly, thedriver 533 ofcontroller 532 may be configured to drive the memory command/address signals at one or more levels specified by the design of the volatile memories 520 (e.g., instead of at a level specified by the design of RCD 510). - Although in the foregoing embodiments, memory devices having a single rank of volatile memories are shown, in other embodiments a memory device can have multiple ranks of memories. For example,
FIG. 6 is a schematic diagram of a memory device having two ranks of memory in accordance with an embodiment of the present technology. Thememory device 600 may be an NVDIMM, or have another alternative module format. Thememory device 600 includes a plurality of volatile memories 620 (e.g., DRAM memories) arranged in two ranks 621 and 622, as well as a non-volatile memory 630 (e.g., NAND memory). Thememory device 600 includes anedge connector 602 for connecting afirst data bus 604 and a command/address bus 606 (illustrated in bold lines) to a host device. Theedge connector 602 may include additional connections for separately controlling the two ranks 621 and 622 of memory (e.g., via two chip select terminals to provide a chip select signal to thememory device 600 in order to enable the desired rank). - The
first data bus 604 connects thevolatile memories 620 to theedge connector 602 and receives data signals from and transmits data signals to a connected host during memory access operations (e.g., reads and writes). Thememory device 600 further includes a registering clock driver (RCD) 610 that receives command/address signals from the command/address bus 606 and generates memory command/address signals for thevolatile memories 620. TheRCD 610 can present a predictable electrical load (e.g., for matching impedance, reactance, capacitance, etc.) to the host device and can re-drive memory command/address signals to thevolatile memories 620, which helps enable higher densities and increase signal integrity. TheRCD 610 may also buffer the command/address signals provided by the host, and then transmit the buffered signals as memory command/address signals to thevolatile memories 620. - The
memory device 600 further includes acontroller 632 for controlling thenon-volatile memory 630 and performing memory management operations, such as power loss detection, backup from thevolatile memories 620 to thenon-volatile memory 630, and restore from thenon-volatile memory 630 to thevolatile memories 620. Thecontroller 632 may include a connection to the edge connector 602 (not shown) to facilitate detection of a power loss event (e.g., by monitoring a voltage of a power supply pin, or via a dedicated pin for sending commands from a connected host to the controller 632). - The
controller 632 is connected to thenon-volatile memory 630 by anon-volatile bus 634 and to thevolatile memories 620 by asecond data bus 605. In this regard, although thememory device 600 ofFIG. 6 is illustrated schematically with separate data buses coupling thevolatile memories 620 to theedge connector 602 and to the controller 632 (e.g., an embodiment in which eachvolatile memory 620 includes an internal DQ mux, with first DQ nets coupled by thefirst data bus 604 to theedge connector 602, and second DQ nets coupled by thesecond data bus 605 to thecontroller 632, switched via a mode register setting in the volatile memory 620), those of skill in the art will readily appreciate that different data bus configurations can be used. Thecontroller 632 is further connected to thevolatile memories 620 so that thecontroller 632 can provide memory command/address signals to thevolatile memories 620 during backup and restore operations. In this regard, the controller can includemultiple drivers driver 633 a sending memory command/address signals to rank 621 of thevolatile memories 620 anddriver 633 b sending memory command/address signals to rank 622 of the volatile memories 620). Thecontroller 632 is configured to provide memory command/address signals to thevolatile memories 620 through four memory command/address multiplexers 636, which are configured to route memory command/address signals to thevolatile memories 620 from both thedrivers controller 632 and the outputs of theRCD 610. Accordingly, thedrivers controller 632 may be configured to drive the memory command/address signals at one or more levels specified by the design of the volatile memories 620 (e.g., instead of at a level specified by the design of RCD 610). - Although in the foregoing embodiments, memory devices having a single RCD are shown, in other embodiments a memory device can have multiple RCDs. For example,
FIG. 7 is a schematic diagram of a memory device in accordance with an embodiment of the present technology. Thememory device 700 may be an NVDIMM, or have another alternative module format. Thememory device 700 includes a plurality of volatile memories 720 (e.g., DRAM memories) arranged in two ranks 721 and 722, as well as a non-volatile memory 730 (e.g., NAND memory). Thememory device 700 includes anedge connector 702 for connecting afirst data bus 704 and a command/address bus 706 (illustrated in bold lines) to a host device. Theedge connector 702 may include additional connections for separately controlling the two ranks 721 and 722 of memory (e.g., via two chip select terminals to provide a chip select signal to thememory device 700 in order to enable the desired rank). - The
first data bus 704 connects thevolatile memories 720 to theedge connector 702 and receives data signals from and transmits data signals to a connected host during memory access operations (e.g., reads and writes). Thememory device 700 further includes two registering clock drivers (RCD) 710 that receive command/address signals from the command/address bus 706 and generate memory command/address signals for thevolatile memories 720. TheRCDs 710 can present a predictable electrical load (e.g., for matching impedance, reactance, capacitance, etc.) to the host device and can re-drive memory command/address signals to thevolatile memories 720, which helps enable higher densities and increase signal integrity. The RCDs 710 may also buffer the command/address signals provided by the host, and then transmit the buffered signals as memory command/address signals to thevolatile memories 720. - The
memory device 700 further includes acontroller 732 for controlling thenon-volatile memory 730 and performing memory management operations, such as power loss detection, backup from thevolatile memories 720 to thenon-volatile memory 730, and restore from thenon-volatile memory 730 to thevolatile memories 720. Thecontroller 732 may include a connection to the edge connector 702 (not shown) to facilitate detection of a power loss event (e.g., by monitoring a voltage of a power supply pin, or via a dedicated pin for sending commands from a connected host to the controller 732). - The
controller 732 is connected to thenon-volatile memory 730 by anon-volatile bus 734 and to thevolatile memories 720 by asecond data bus 705. In this regard, although thememory device 700 ofFIG. 7 is illustrated schematically with separate data buses coupling thevolatile memories 720 to theedge connector 702 and to the controller 732 (e.g., an embodiment in which eachvolatile memory 720 includes an internal DQ mux, with first DQ nets coupled by thefirst data bus 704 to theedge connector 702, and second DQ nets coupled by thesecond data bus 705 to thecontroller 732, switched via a mode register setting in the volatile memory 720), those of skill in the art will readily appreciate that different data bus configurations can be used. Thecontroller 732 is further connected to thevolatile memories 720 so that thecontroller 732 can provide memory command/address signals to thevolatile memories 720 during backup and restore operations. In this regard, the controller can includemultiple drivers driver 733 a sending memory command/address signals to rank 721 of thevolatile memories 720 anddriver 733 b sending memory command/address signals to rank 722 of the volatile memories 720). Thecontroller 732 is configured to provide memory command/address signals to thevolatile memories 720 through four memory command/address multiplexers 736, which are configured to route memory command/address signals to thevolatile memories 720 from both thedrivers controller 732 and the outputs of theRCD 710. Accordingly, thedrivers controller 732 may be configured to drive the memory command/address signals at one or more levels specified by the design of the volatile memories 720 (e.g., instead of at a level specified by the design of RCD 710). - Although in the foregoing exemplary embodiments, memory devices with DRAM-format volatile memory are illustrated, those of skill in the art will readily appreciate that other volatile memory formats can be provided on a memory device similarly configured. For example, a memory device using any one of, or any combination of, DRAM, SRAM, ZRAM, thyristor-RAM or the like could be provided in alternative embodiments of the present technology.
- Although in the foregoing exemplary embodiments, memory devices with NAND-format non-volatile memory are illustrated, those of skill in the art will readily appreciate that other non-volatile memory formats can be provided on a memory device similarly configured. For example, a memory device using any one of, or any combination of, NAND, NOR, PCM, MRAM, FeRAM, ReRAM or the like could be provided in alternative embodiments of the present technology.
-
FIG. 8 is a flow chart illustrating a method of operating a memory device in accordance with an embodiment of the present technology. The method includes receiving, at a connector of the memory device, command/address signals for a volatile memory of the memory device (box 810). The method further includes providing the command/address signals from the connector to a registering clock driver (RCD) of the memory device to generate memory command/address signals (box 820). The method further includes providing the memory command/address signals from the RCD to a first input of a multiplexer (box 830). The multiplexer can include a second input connected to a non-volatile memory controller of the memory device. The method further includes providing the memory command/address signals from the multiplexer to the volatile memory of the memory device (box 840). - The method can further include detecting an event configured to trigger a backup operation (box 850). The backup operation may include providing backup command/address signals (e.g., including read commands for the volatile memory) from the non-volatile memory controller to the second input of the multiplexer (box 860). In some embodiments, the controller may first instruct the multiplexer to activate the second input of the multiplexer (e.g., and de-select the first input). The backup operation may further include providing (box 870) the backup command/address signals from the multiplexer to the volatile memory (e.g., instructing the volatile memory to read data from the volatile memory onto the data bus). If the volatile memory includes multiple volatile memories, the backup command/address signals may either be directed to the multiple volatile memories serially, simultaneously, or some combination thereof (e.g., to more than one but less than all at a time, such as a right-side-first, left-side-second approach). If the volatile memory includes internal DQ muxes, the controller may include in the backup command/address signals an instruction to select the port(s) coupled by data bus connections to the controller.
- The method can further include a restore operation, which may include providing restore command/address signals (e.g., including write commands for the volatile memory) from the non-volatile memory controller to the second input of the multiplexer (box 880). In some embodiments, the controller may first instruct the multiplexer to activate the second input of the multiplexer (e.g., and de-select the first input). The restore operation may further include providing (box 890) the restore command/address signals from the multiplexer to the volatile memory (e.g., instructing the volatile memory to write data from the data bus to the volatile memory). If the volatile memory includes multiple volatile memories, the restore command/address signals may either be directed to the multiple volatile memories serially or simultaneously, or some combination thereof (e.g., to more than one but less than all at a time, such as a right-side-first, left-side-second approach). If the volatile memory includes internal DQ muxes, the controller may include in the restore command/address signals an instruction to select the port(s) coupled by data bus connections to the controller.
- From the foregoing, it will be appreciated that specific embodiments of the invention have been described herein for purposes of illustration, but that various modifications may be made without deviating from the scope of the invention. Accordingly, the invention is not limited except as by the appended claims.
Claims (20)
1. An apparatus, comprising:
a first plurality of volatile memories;
a second plurality of volatile memories;
a non-volatile memory;
a controller coupled to the non-volatile memory;
a registering clock driver (RCD) having a first RCD output and a second RCD output;
a first command/address (C/A) multiplexer including a first C/A mux input coupled to the first RCD output, a second C/A mux input coupled to the controller, and a first C/A mux output coupled to the first plurality of volatile memories; and
a second C/A multiplexer including a third C/A mux input coupled to the second RCD output, a fourth C/A mux input coupled to the controller, and a second C/A mux output coupled to the second plurality of volatile memories.
2. The apparatus of claim 1 , wherein the RCD has a RCD input coupled to an external connector of the apparatus by a command/address bus.
3. The apparatus of claim 1 , wherein the controller includes a driver configured to generate command/address signals for the first and second pluralities of volatile memories.
4. The apparatus of claim 1 , wherein the first and second C/A multiplexers are configured to provide command/address signals from either the RCD or the controller to the first and second pluralities of volatile memories, respectively.
5. The apparatus of claim 1 , further comprising a backup power source.
6. The apparatus of claim 1 , wherein the controller is configured to generate command/address signals to copy data from the first and/or second pluralities of volatile memories to the non-volatile memory upon detecting a loss of power to the apparatus.
7. The apparatus of claim 6 , wherein the first and second C/A multiplexers are configured to ignore command/address signals from the RCD upon detecting the loss of power to the apparatus.
8. The apparatus of claim 6 , wherein the controller is configured to generate command/address signals to copy data from the non-volatile memory to the first and/or second pluralities of volatile memories upon recovery from the loss of power to the apparatus.
9. An apparatus, comprising:
a first plurality of volatile memories;
a second plurality of volatile memories;
a non-volatile memory;
a controller coupled to the non-volatile memory;
a first registering clock driver (RCD);
a second RCD;
a first command/address (C/A) multiplexer including a first C/A mux input coupled to an output of the first RCD, a second C/A mux input coupled to the controller, and a first C/A mux output coupled to the first plurality of volatile memories; and
a second C/A multiplexer including a third C/A mux input coupled to an output of the second RCD, a fourth C/A mux input coupled to the controller, and a second C/A mux output coupled to the second plurality of volatile memories.
10. The apparatus of claim 9 , wherein the first and second RCDs each have an input coupled to an external connector of the apparatus by a command/address bus.
11. The apparatus of claim 9 , wherein the controller includes a driver configured to generate command/address signals for the first and second pluralities of volatile memories.
12. The apparatus of claim 9 , further comprising a backup power source.
13. The apparatus of claim 9 , wherein the controller is configured to generate command/address signals to copy data from the first and/or second pluralities of volatile memories to the non-volatile memory upon detecting a loss of power to the apparatus.
14. The apparatus of claim 9 , wherein the controller is configured to generate command/address signals to copy data from the non-volatile memory to the first and/or second pluralities of volatile memories upon recovery from the loss of power to the apparatus.
15. An apparatus, comprising:
a substrate;
a connector on the substrate, the connector configured to receive first command/address signals;
a controller on the substrate, the controller configured to generate second command/address signals;
at least one registering clock driver (RCD) on the substrate;
a first plurality of memories on the substrate; and
a second plurality of memories on the substrate,
wherein each of the first plurality of memories is configured to receive the first command/address signals from the connector through a first RCD output of the at least one RCD and to receive the second command/address signals from the controller without intervening the at least one RCD therebetween, and
wherein each of the second plurality of memories is configured to receive the first command/address signals from the connector through a second RCD output of the at least one RCD and to receive the second command/address signals from the controller without intervening the at least one RCD therebetween.
16. The apparatus of claim 15 , wherein the controller includes a driver configured to generate the second command/address signals.
17. The apparatus of claim 15 , further comprising a backup power source.
18. The apparatus of claim 15 , wherein the second command/address signals are configured to copy data from the first and/or second pluralities of memories to a third memory on the substrate upon detecting a loss of power to the apparatus.
19. The apparatus of claim 18 , wherein the controller is configured to generate command/address signals to copy data from the third memory to the first and/or second pluralities of memories upon recovery from the loss of power to the apparatus.
20. The apparatus of claim 15 , wherein the at least one RCD comprises a first RCD including the first RCD output and a second RCD including the second RCD output.
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EP3655860B1 (en) | 2022-11-02 |
US20210125977A1 (en) | 2021-04-29 |
KR20190143454A (en) | 2019-12-30 |
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