US20220165881A1 - Method of forming transistors of different configurations - Google Patents
Method of forming transistors of different configurations Download PDFInfo
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- US20220165881A1 US20220165881A1 US17/101,212 US202017101212A US2022165881A1 US 20220165881 A1 US20220165881 A1 US 20220165881A1 US 202017101212 A US202017101212 A US 202017101212A US 2022165881 A1 US2022165881 A1 US 2022165881A1
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- 238000000034 method Methods 0.000 title abstract description 139
- 239000004065 semiconductor Substances 0.000 claims abstract description 60
- 230000000903 blocking effect Effects 0.000 claims abstract description 55
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 125000006850 spacer group Chemical group 0.000 claims description 86
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 30
- 229910052710 silicon Inorganic materials 0.000 claims description 30
- 239000010703 silicon Substances 0.000 claims description 30
- 239000000203 mixture Substances 0.000 claims description 17
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 11
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 9
- MRELNEQAGSRDBK-UHFFFAOYSA-N lanthanum(3+);oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[La+3].[La+3] MRELNEQAGSRDBK-UHFFFAOYSA-N 0.000 claims description 7
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 5
- SIWVEOZUMHYXCS-UHFFFAOYSA-N oxo(oxoyttriooxy)yttrium Chemical compound O=[Y]O[Y]=O SIWVEOZUMHYXCS-UHFFFAOYSA-N 0.000 claims description 5
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 claims description 5
- 229910001928 zirconium oxide Inorganic materials 0.000 claims description 5
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052799 carbon Inorganic materials 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 3
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 262
- 230000008569 process Effects 0.000 description 82
- 239000000463 material Substances 0.000 description 31
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 16
- 238000005229 chemical vapour deposition Methods 0.000 description 15
- 230000015572 biosynthetic process Effects 0.000 description 12
- 238000000231 atomic layer deposition Methods 0.000 description 11
- 229910052731 fluorine Inorganic materials 0.000 description 11
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 10
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 10
- 238000000151 deposition Methods 0.000 description 10
- 239000011737 fluorine Substances 0.000 description 10
- 239000007789 gas Substances 0.000 description 10
- 238000004519 manufacturing process Methods 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 238000009966 trimming Methods 0.000 description 9
- 239000003989 dielectric material Substances 0.000 description 8
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 238000000576 coating method Methods 0.000 description 6
- 229910044991 metal oxide Inorganic materials 0.000 description 6
- 150000004706 metal oxides Chemical class 0.000 description 6
- 230000003647 oxidation Effects 0.000 description 6
- 238000007254 oxidation reaction Methods 0.000 description 6
- 239000011248 coating agent Substances 0.000 description 5
- 238000001312 dry etching Methods 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- QKCGXXHCELUCKW-UHFFFAOYSA-N n-[4-[4-(dinaphthalen-2-ylamino)phenyl]phenyl]-n-naphthalen-2-ylnaphthalen-2-amine Chemical compound C1=CC=CC2=CC(N(C=3C=CC(=CC=3)C=3C=CC(=CC=3)N(C=3C=C4C=CC=CC4=CC=3)C=3C=C4C=CC=CC4=CC=3)C3=CC4=CC=CC=C4C=C3)=CC=C21 QKCGXXHCELUCKW-UHFFFAOYSA-N 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 210000002381 plasma Anatomy 0.000 description 5
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 5
- 238000001039 wet etching Methods 0.000 description 5
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- 238000001035 drying Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- RVSGESPTHDDNTH-UHFFFAOYSA-N alumane;tantalum Chemical compound [AlH3].[Ta] RVSGESPTHDDNTH-UHFFFAOYSA-N 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- 239000005350 fused silica glass Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 3
- -1 poly(vinyl pyridine) Polymers 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000000927 vapour-phase epitaxy Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 2
- HEDRZPFGACZZDS-UHFFFAOYSA-N Chloroform Chemical compound ClC(Cl)Cl HEDRZPFGACZZDS-UHFFFAOYSA-N 0.000 description 2
- 229920002396 Polyurea Polymers 0.000 description 2
- 229910002370 SrTiO3 Inorganic materials 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 2
- 229910021529 ammonia Inorganic materials 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 2
- ZDZIJHSDFUXADX-UHFFFAOYSA-N azanium hydrogen peroxide hydroxide hydrate Chemical compound O.OO.[OH-].[NH4+] ZDZIJHSDFUXADX-UHFFFAOYSA-N 0.000 description 2
- 229910002113 barium titanate Inorganic materials 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000005380 borophosphosilicate glass Substances 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- 229910052801 chlorine Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 239000005368 silicate glass Substances 0.000 description 2
- SFZCNBIFKDRMGX-UHFFFAOYSA-N sulfur hexafluoride Chemical compound FS(F)(F)(F)(F)F SFZCNBIFKDRMGX-UHFFFAOYSA-N 0.000 description 2
- 229910003468 tantalcarbide Inorganic materials 0.000 description 2
- VZGDMQKNWNREIO-UHFFFAOYSA-N tetrachloromethane Chemical compound ClC(Cl)(Cl)Cl VZGDMQKNWNREIO-UHFFFAOYSA-N 0.000 description 2
- TXEYQDLBPFQVAA-UHFFFAOYSA-N tetrafluoromethane Chemical compound FC(F)(F)F TXEYQDLBPFQVAA-UHFFFAOYSA-N 0.000 description 2
- 239000010936 titanium Substances 0.000 description 2
- 238000000038 ultrahigh vacuum chemical vapour deposition Methods 0.000 description 2
- GFQYVLUOOAAOGM-UHFFFAOYSA-N zirconium(iv) silicate Chemical compound [Zr+4].[O-][Si]([O-])([O-])[O-] GFQYVLUOOAAOGM-UHFFFAOYSA-N 0.000 description 2
- 229910002938 (Ba,Sr)TiO3 Inorganic materials 0.000 description 1
- ZCYVEMRRCGMTRW-UHFFFAOYSA-N 7553-56-2 Chemical compound [I] ZCYVEMRRCGMTRW-UHFFFAOYSA-N 0.000 description 1
- 229910015844 BCl3 Inorganic materials 0.000 description 1
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 1
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- 208000012868 Overgrowth Diseases 0.000 description 1
- GEIAQOFPUVMAGM-UHFFFAOYSA-N Oxozirconium Chemical compound [Zr]=O GEIAQOFPUVMAGM-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 1
- OBZUDFAHIZFVHI-UHFFFAOYSA-N [La].[Si]=O Chemical compound [La].[Si]=O OBZUDFAHIZFVHI-UHFFFAOYSA-N 0.000 description 1
- DBOSVWZVMLOAEU-UHFFFAOYSA-N [O-2].[Hf+4].[La+3] Chemical compound [O-2].[Hf+4].[La+3] DBOSVWZVMLOAEU-UHFFFAOYSA-N 0.000 description 1
- ILCYGSITMBHYNK-UHFFFAOYSA-N [Si]=O.[Hf] Chemical compound [Si]=O.[Hf] ILCYGSITMBHYNK-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- ONRPGGOGHKMHDT-UHFFFAOYSA-N benzene-1,2-diol;ethane-1,2-diamine Chemical compound NCCN.OC1=CC=CC=C1O ONRPGGOGHKMHDT-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000009849 deactivation Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- PXBRQCKWGAHEHS-UHFFFAOYSA-N dichlorodifluoromethane Chemical compound FC(F)(Cl)Cl PXBRQCKWGAHEHS-UHFFFAOYSA-N 0.000 description 1
- RWRIWBAIICGTTQ-UHFFFAOYSA-N difluoromethane Chemical compound FCF RWRIWBAIICGTTQ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- ZQXQADNTSSMHJI-UHFFFAOYSA-N hafnium(4+) oxygen(2-) tantalum(5+) Chemical compound [O-2].[Ta+5].[Hf+4] ZQXQADNTSSMHJI-UHFFFAOYSA-N 0.000 description 1
- KQHQLIAOAVMAOW-UHFFFAOYSA-N hafnium(4+) oxygen(2-) zirconium(4+) Chemical compound [O--].[O--].[O--].[O--].[Zr+4].[Hf+4] KQHQLIAOAVMAOW-UHFFFAOYSA-N 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- KUVFGOLWQIXGBP-UHFFFAOYSA-N hafnium(4+);oxygen(2-);titanium(4+) Chemical compound [O-2].[O-2].[O-2].[O-2].[Ti+4].[Hf+4] KUVFGOLWQIXGBP-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 229910052740 iodine Inorganic materials 0.000 description 1
- 239000011630 iodine Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910017604 nitric acid Inorganic materials 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000011295 pitch Substances 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229920002492 poly(sulfone) Polymers 0.000 description 1
- 229920000058 polyacrylate Polymers 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 239000003870 refractory metal Substances 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HWEYZGSCHQNNEH-UHFFFAOYSA-N silicon tantalum Chemical compound [Si].[Ta] HWEYZGSCHQNNEH-UHFFFAOYSA-N 0.000 description 1
- 229920005573 silicon-containing polymer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 150000003457 sulfones Chemical class 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- FAQYAMRNWDIXMY-UHFFFAOYSA-N trichloroborane Chemical compound ClB(Cl)Cl FAQYAMRNWDIXMY-UHFFFAOYSA-N 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 238000009736 wetting Methods 0.000 description 1
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-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
- H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- H—ELECTRICITY
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Definitions
- multi-gate MOSFET multi-gate metal-oxide-semiconductor field effect transistor
- a multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region.
- Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications.
- a FinFET has an elevated channel wrapped by a gate on more than one side (for example, the gate wraps a top and sidewalls of a “fin” of semiconductor material extending from a substrate).
- An MBC transistor has a gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor.
- SGT surrounding gate transistor
- GAA gate-all-around
- an MBC transistor With multiple channel members that are wrapped around by a gate structure, an MBC transistor provides good drive current performance by increasing the effective channel width. While existing methods for forming MBC transistors are generally adequate for their intended purposes, they are satisfactory in all aspects.
- FIG. 1 illustrates a flowchart of a method for forming a semiconductor device, according to one or more aspects of the present disclosure.
- FIGS. 2-22 illustrate fragmentary cross-sectional views of a workpiece during a fabrication process according to the method of FIG. 1 , according to one or more aspects of the present disclosure.
- FIG. 23 illustrates a schematic top view of an IC device that includes various MBC transistors, according to one or more aspects of the present disclosure.
- FIG. 24 illustrates a flowchart of a method for determining a parameter for performing the method of FIG. 1 , according to one or more aspects of the present disclosure.
- first and second features are formed in direct contact
- additional features may be formed between the first and second features, such that the first and second features may not be in direct contact
- present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
- the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
- the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art.
- the number or range of numbers encompasses a reasonable range including the number described, such as within +/ ⁇ 10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number.
- a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.25 nm to 5.75 nm where manufacturing tolerances associated with depositing the material layer are known to be +/ ⁇ 15% by one of ordinary skill in the art.
- the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- the present disclosure is generally related to multi-gate transistors and fabrication methods, and more particularly to methods of fabricating MBC transistors of different configurations.
- Methods of the present disclosure may include a blocking feature formation process after the formation of inner spacer features.
- the blocking feature formation process may form blocking features to selectively shut off a predetermined number of channel members to modulate the effective resistance, effective capacitance, or drive current of an MBC transistor to meet various design needs.
- the blocking features are disposed between a to-be-shut-off channel member and adjacent source/drain features to electrically isolate the to-be-shut-off channel member.
- Methods of the present disclosure allow formation of MBC transistors that have similar dimensional but different effective channel widths.
- FIG. 1 is a flowchart illustrating a method 100 of forming a semiconductor device from a workpiece according to embodiments of the present disclosure.
- Method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated in method 100 . Additional steps can be provided before, during and after the method 100 , and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity. Method 100 is described below in conjunction with FIG. 2-22 , which are fragmentary cross-sectional views of workpiece 200 at different stages of fabrication according to embodiments of the method 100 in FIG. 1 .
- the workpiece 200 will be fabricated into a semiconductor device, the workpiece 200 may be referred to herein as a semiconductor device 200 as the context requires.
- the X, Y and Z directions in FIGS. 2-20 are perpendicular to one another and are used consistently among the figures.
- like reference numerals denote like features, unless otherwise excepted.
- method 100 includes a block 102 where a workpiece 200 is provided.
- the workpiece 200 includes a substrate 202 .
- the substrate 202 may be a semiconductor substrate such as a silicon (Si) substrate.
- the substrate 202 may also include other semiconductors such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond.
- the substrate 202 may include a compound semiconductor and/or an alloy semiconductor.
- the substrate 202 may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or a germanium-on-insulator (GeOI) structure, and/or may have other suitable enhancement features.
- epi-layer epitaxial layer
- SOI silicon-on-insulator
- GeOI germanium-on-insulator
- the workpiece 200 further includes a stack 204 .
- the stack 204 includes sacrificial layers 206 of a first semiconductor composition interleaved by channel layers 208 of a second semiconductor composition.
- the first and second semiconductor composition may be different.
- the sacrificial layers 206 include silicon germanium (SiGe) and the channel layers 208 include silicon (Si).
- SiGe silicon germanium
- Si silicon
- three (3) layers of the sacrificial layers 206 and three (3) layers of the channel layers 208 are alternately arranged as illustrated in FIG. 2 , which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims.
- any number of epitaxial layers may be formed in the stack 204 .
- the number of layers depends on the desired number of channels members for the semiconductor device 200 .
- the number of channel layers 208 is between 2 and 10.
- all sacrificial layers 206 may have a substantially uniform first thickness between about 9 nm and about 10 nm and all of the channel layers 208 may have a substantially uniform second thickness between about 6 nm and about 8 nm.
- the first thickness and the second thickness may be identical or different.
- the channel layers 208 or parts thereof may serve as channel member(s) for a subsequently-formed multi-gate device and the thickness of each of the channel layers 208 is chosen based on device performance considerations.
- the sacrificial layers 206 in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel region(s) for a subsequently-formed multi-gate device and the thickness of each of the sacrificial layers 206 is chosen based on device performance considerations.
- the layers in the stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase deposition (VPE) process, and/or other suitable epitaxial growth processes.
- MBE molecular beam epitaxy
- VPE vapor phase deposition
- the sacrificial layers 206 include an epitaxially grown silicon germanium (SiGe) layer and the channel layers 208 include an epitaxially grown silicon (Si) layer.
- the sacrificial layers 206 and the channel layers 208 are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm ⁇ 3 to about 1 ⁇ 10 17 cm ⁇ 3 ), where for example, no intentional doping is performed during the epitaxial growth processes for the stack 204 .
- method 100 includes a block 104 where a fin-shaped structure 212 is formed from the stack 204 and the substrate 202 .
- FIG. 2 includes a fragmentary cross-sectional view of the workpiece 200 along the Y direction while FIG. 3 illustrates a fragmentary cross-sectional view of the workpiece 200 along the X direction.
- a hard mask layer 210 (shown in FIG. 2 ) may be deposited over the stack 204 to form an etch mask.
- the hard mask layer 210 may be a single layer or a multi-layer.
- the hard mask layer 210 may include a pad oxide layer and a pad nitride layer over the pad oxide layer.
- the fin-shaped structure 212 may be patterned from the stack 204 and the substrate 202 using lithography processes and etch processes.
- the lithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof.
- the etch process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. As shown in FIG. 3 , the etch process at block 104 forms trenches extending through the stack 204 and a portion of the substrate 202 .
- the trenches define the fin-shaped structures 212 .
- double-patterning or multi-patterning processes may be used to define fin-shaped structures that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process.
- a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin-shaped structure 212 by etching the stack 204 .
- the fin-shaped structure 212 along with the sacrificial layers 206 and the channel layers 208 therein, extends vertically along the Z direction and lengthwise along the X direction.
- an isolation feature 214 is formed adjacent the fin-shaped structure 212 .
- the isolation feature 214 may be formed in the trenches to isolate the fin-shaped structures 212 from a neighboring active region.
- the isolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214 .
- a dielectric layer is first deposited over the substrate 202 , filling the trenches with the dielectric layer.
- the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials.
- the dielectric layer may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, a spin-on coating process, and/or other suitable process.
- the deposited dielectric material is then thinned and planarized, for example by a chemical mechanical polishing (CMP) process.
- CMP chemical mechanical polishing
- the planarized dielectric layer is further recessed or pulled-back by a dry etching process, a wet etching process, and/or a combination thereof to form the STI feature 214 .
- the fin-shaped structure 212 rises above the STI feature 214 after the recessing.
- method 100 includes a block 106 where a dummy gate stack 220 is formed over a channel region 212 C of the fin-shaped structure 212 .
- FIG. 3 and FIG. 4 share the same viewing angle (along the X direction) while FIG. 5 shares the same viewing angle (along the Y direction) with FIG. 2 .
- a gate replacement process (or gate-last process) is adopted where the dummy gate stack 220 (shown in FIGS. 4 and 5 ) serves as a placeholder to undergo various processes and is to be removed and replaced by the functional gate structure. Other processes and configuration are possible.
- FIG. 4 gate replacement process
- the dummy gate stack 220 is formed over the fin-shaped structure 212 and the fin-shaped structure 212 may be divided into channel regions 212 C underlying the dummy gate stacks 220 and source/drain regions 212 SD that do not underlie the dummy gate stacks 220 .
- the channel regions 212 C are adjacent the source/drain regions 212 SD. As shown in FIG. 5 , the channel region 212 C is disposed between two source/drain regions 212 SD along the X direction.
- the formation of the dummy gate stack 220 may include deposition of layers in the dummy gate stack 220 and patterning of these layers. Referring to FIG. 4 , a dummy dielectric layer 216 , a dummy electrode layer 218 , and a gate-top hard mask layer 222 may be deposited over the workpiece 200 . In some embodiments, the dummy dielectric layer 216 may be formed on the fin-shaped structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, a thermal oxidation process, or other suitable processes. In some instances, the dummy dielectric layer 216 may include silicon oxide.
- CVD chemical vapor deposition
- the dummy dielectric layer 216 When the dummy dielectric layer 216 is formed using an oxidation process, it may be selectively formed on exposed surfaces of the fin-shaped structure 212 , as illustrated in FIG. 4 . Thereafter, the dummy electrode layer 218 may be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable processes. In some instances, the dummy electrode layer 218 may include polysilicon (poly Si). For patterning purposes, the gate-top hard mask layer 222 may be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable processes.
- the gate-top hard mask layer 222 , the dummy electrode layer 218 and the dummy dielectric layer 216 may then be patterned to form the dummy gate stack 220 , as shown in FIG. 5 .
- the patterning process may include a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof.
- the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods.
- the gate-top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 over the silicon oxide layer 223 . As shown in FIG. 5 , no dummy gate stack 220 is disposed over the source/drain region 212 SD of the fin-shaped structure 212 .
- method 100 includes a block 108 where at least one gate spacer layer 226 is deposited over the dummy gate stack 220 .
- the at least one gate spacer layer 226 is deposited conformally over the workpiece 200 , including over top surfaces and sidewalls of the dummy gate stack 220 .
- the term “conformally” may be used herein for ease of description of a layer having substantially uniform thickness over various regions.
- the at least one gate spacer layer 226 may be a single layer or a multi-layer.
- the at least one gate spacer layer 226 includes a first spacer layer 225 and a second spacer layer 227 disposed over the first spacer layer 225 .
- a composition of the first spacer layer 225 may be different from a composition of the second spacer layer 227 .
- a dielectric constant of the first spacer layer 225 is greater than a dielectric constant of the second spacer layer 227 .
- the at least one gate spacer layer 226 including the first spacer layer 225 and the second spacer layer 227 , may include silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride.
- the at least one gate spacer layer 226 may be deposited over the dummy gate stack 220 using processes such as, a CVD process, a subatmospheric CVD (SACVD) process, an ALD process, or other suitable process.
- SACVD subatmospheric CVD
- ALD atomic layer
- method 100 includes a block 110 where a source/drain region 212 SD of the fin-shaped structure 212 is recessed to form a source/drain trench 228 .
- the source/drain regions 212 SD that are not covered by the dummy gate stack 220 and sidewall portions of the gate spacer layer 226 are etched by a dry etch or a suitable etching process to form the source/drain trenches 228 .
- the dry etch process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6 ), a chlorine-containing gas (e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3 ), a bromine-containing gas (e.g., HBr and/or CHBR3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof.
- a fluorine-containing gas e.g., CF 4 , SF 6 , CH 2 F 2 , CHF 3 , and/or C 2 F 6
- a chlorine-containing gas e.g., Cl 2 , CHCl 3 , CCl 4 , and/or BCl 3
- a bromine-containing gas e.g., HBr and/or CHBR3
- the source/drain regions 212 SD of the fin-shaped structure 212 are recessed to expose sidewalls of the sacrificial layers 206 and the channel layers 208 .
- the source/drain trenches 228 extend below the stack 204 into the substrate 202 .
- FIG. 7 illustrates a cross-sectional view of the workpiece 200 viewed along the Y direction at the source/drain region 212 SD. As shown in FIG. 7 , the sacrificial layers 206 and channel layers 208 in the source/drain region 212 SD are removed at block 110 , exposing surfaces of the substrate 202 in the bottom of the source/drain trenches 228 .
- method 100 includes a block 112 where the sacrificial layers 206 are partially and selectively recessed to form first inner spacer recesses 230 .
- the sacrificial layers 206 exposed in the source/drain trenches 228 are selectively and partially recessed to form first inner spacer recesses 230 while the gate spacer layer 226 , the exposed portion of the substrate 202 , and the channel layers 208 are substantially unetched.
- the selective recess of the sacrificial layers 206 may be performed using a selective wet etch process or a selective dry etch process.
- An example selective dry etching process may include use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons.
- An example selective wet etching process may include an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). While the etch process at block 112 is selective, the exposed edge portions of the channel layers 208 may still be moderately etched or trimmed, as shown in FIG. 8 .
- method 100 includes a block 114 where inner spacer features 232 are deposited into the first inner spacer recesses 230 .
- an inner spacer material layer is conformally deposited over the workpiece 200 , including into the first inner spacer recesses 230 .
- the inner spacer material layer may include metal oxides, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material.
- the metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxide.
- the inner spacer material layer may be a single layer or a multilayer.
- the inner spacer material layer may be deposited using CVD, PECVD, SACVD, ALD or other suitable methods.
- the deposited inner spacer material layer is then etched back to remove the inner spacer material layer from the sidewalls of the channel layers 208 to form the inner spacer features 232 in the first inner spacer recesses 230 .
- the etch back operations performed at block 114 may include use of hydrogen fluoride (HF), fluorine gas (F 2 ), hydrogen (H 2 ), ammonia (NH 3 ), nitrogen trifluoride (NF 3 ), or other fluorine-based etchants.
- HF hydrogen fluoride
- F 2 fluorine gas
- H 2 hydrogen
- NH 3 ammonia
- NF 3 nitrogen trifluoride
- each of the inner spacer features 232 covers an end surface of a sacrificial layer 206 .
- method 100 includes a block 116 where a portion of the channel layers 208 in the channel regions 212 C is selectively trimmed to form second inner spacer recesses 236 .
- the portion of the channel layers 208 to be selectively trimmed is controlled by a thickness of a bottom antireflective coating (BARC) layer 234 .
- BARC bottom antireflective coating
- the number of channel layers 208 to be selectively trimmed may be controlled by controlling the thickness of the BARC layer 234 .
- the number of channel layers 208 to be selectively trimmed and eventually shut-off or blocked off is determined by the design for the semiconductor device 200 .
- the BARC layer 234 may be deposited over the workpiece 200 by spin-on coating or a suitable deposition process.
- the BARC layer 234 may include polysulfones, polyureas, polyurea sulfones, polyacrylates, poly(vinyl pyridine), or a silicon-containing polymer.
- the deposited BARC layer 234 is not deposited directly to the desired height. Instead, it is deposited to a height to a thickness greater than a designed thickness and is then etched back until a desired height is reached.
- the etch back of the BARC layer 234 may include a dry etch process that uses a hydrogen plasma, an oxygen plasma, or a combination thereof.
- the etched backed BARC layer 234 covers and protects the bottommost channel layer 208 while the other channel layers 208 remained exposed.
- the BARC layer 234 may be recessed to cover more or less channel layers 208 . For example, when all channel layers 208 in one device region are to be shut-off, the BARC layer 234 is allowed to cover all end surfaces of the channel layers 208 . For another example, when none of the channel layers 208 in another device region are to be shut-off, the BARC layer 234 does not cover any of the end surfaces of the channel layers 208 .
- the channel layers 208 in the channel regions 212 C that are not protected by the BARC layer 234 are selectively trimmed along the X direction to form the second inner spacer recesses 236 .
- the trimming at block 116 is selective to the channel layers 208 and etches the gate spacer layer 226 , the inner spacer features 232 and the BARC layer 234 at a reduced rate.
- the selective trimming of the exposed channel layers 208 may include a selective wet etch process that uses a mixture of nitric acid and hydrofluoric acid, ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or a suitable wet etchant.
- EDP ethylenediamine pyrocatechol
- TMAH tetramethylammonium hydroxide
- the selective trimming of the exposed channel layers 208 may include a selective wet etch process that uses plasma of fluorine-containing species (e.g. CF 4 , SF 6 , NF 3 , or CCl 2 F 2 ) or chlorine-containing species (e.g. C 2 , CC 2 F 2 ).
- a depth of the second inner spacer recesses 236 may be substantially similar to a depth of the first inner spacer recesses 230 along the X direction.
- the bottommost channel layer 208 is protected by the BARC layer 234 and is not trimmed at block 116 .
- the BARC layer 234 may be removed by using a suitable dry etch process or a suitable wet etch process.
- method 100 includes a block 118 where blocking inner spacer features 238 are formed in the second inner spacer recesses 236 .
- a blocking inner spacer material layer 237 is conformally deposited over the workpiece 200 , including into the second inner spacer recesses 236 .
- a composition of the blocking inner spacer material layer 237 may be similar to that of the inner spacer features 232 .
- the blocking inner spacer material layer 237 may include metal oxides, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material.
- the metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxide.
- the blocking inner spacer material layer 237 may be deposited using CVD, PECVD, SACVD, ALD or other suitable methods. The deposited blocking inner spacer material layer 237 is then etched back to remove the blocking inner spacer material layer 237 from the sidewalls of the inner spacer features 232 and the gate spacer layer 226 , thereby forming the blocking inner spacer features 238 in the second inner spacer recesses 236 .
- the etch back operations performed at block 118 may include use of hydrogen fluoride (HF), fluorine gas (F 2 ), hydrogen (H 2 ), ammonia (NH 3 ), nitrogen trifluoride (NF 3 ), or other fluorine-based etchants.
- HF hydrogen fluoride
- F 2 fluorine gas
- H 2 hydrogen
- NH 3 ammonia
- NF 3 nitrogen trifluoride
- each of the blocking inner spacer features 238 caps off end surfaces of the channel layers 208 that are not protected by the BARC layer 234 . In that sense the blocking inner spacer features 238 may also be referred to as blocking features 238 or deactivation features 238 .
- the channel layers 208 that are covered by the blocking features 238 are referred to hereinafter as covered channel layers 208 C and the channel layers 208 that are not covered by the blocking features 238 are referred to hereinafter as exposed channel layers 208 E.
- the covered channel layers 208 C and the exposed channel layers 208 E may be referred collectively as channel layers 208 .
- the workpiece 200 includes one exposed channel layer 208 E and two covered channel layers 208 C. Due to the selectively trimming at block 116 , a length of the exposed channel layer 208 E along the X direction is greater than a length of the covered channel layer 208 C by about two times the thicknesses of the blocking features 238 .
- method 100 includes a block 120 where source/drain features 240 are formed over the source/drain regions 212 SD.
- the source/drain feature 240 may be epitaxially and selectively formed from the sidewalls of the exposed channel layer 208 E and exposed surfaces of the substrate 202 , while sidewalls of the sacrificial layers 206 remain covered by the inner spacer features 232 and sidewalls of the covered channel layers 208 C remain covered by the blocking features 238 .
- Suitable epitaxial processes for block 120 include vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes.
- the epitaxial growth process at block 120 may use gaseous precursors, which interact with the composition of the substrate 202 and the channel layers 208 .
- overgrowth of the source/drain feature 240 may extend over sidewalls of the inner spacer feature 232 and the blocking features 238 .
- the source/drain feature 240 may have different compositions.
- the source/drain feature 240 may include silicon (Si) and may be doped with an n-type dopant, such as phosphorus (P) or arsenic (As).
- the source/drain feature 240 may include silicon germanium (SiGe) and is doped with a p-type dopant, such as boron (B) or gallium (Ga). While not explicitly shown in FIG. 15 , the source/drain feature 240 may include two or more epitaxial layers. For example, the source/drain feature 240 may include a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer that are doped with the same type of dopant but at different doping concentrations to reduce defect density and contact resistance.
- the source/drain feature 240 may include phosphorus-doped silicon (Si:P) when n-type MBC transistors are desired and may include boron-doped silicon germanium (SiGe:B) when p-type MBC transistors are desired.
- Si:P phosphorus-doped silicon
- SiGe:B boron-doped silicon germanium
- the exposed channel layer 208 E extends between and are coupled to the source/drain features 240
- the covered channel layers 208 C are insulated or separated from the source/drain features 240 by the blocking features 238 .
- method 100 includes a block 122 where further processes are performed.
- Such further processes may include, for example, deposition of a contact etch stop layer (CESL) 242 over the workpiece 200 (shown in FIG. 16 ), deposition of an interlayer dielectric (ILD) layer 244 over the CESL 242 (shown in FIG. 16 ), removal of the dummy gate stack 220 (shown in FIG. 17 ), selective removal of the sacrificial layers 206 in the channel region 212 C to release the channel layers 208 as channel members 2080 (shown in FIG. 18 ), and formation of a gate structure 260 over the channel region 212 C (shown in FIG. 19 ).
- CSL contact etch stop layer
- ILD interlayer dielectric
- the CESL 242 is formed prior to forming the ILD layer 244 .
- the CESL 242 includes silicon nitride, silicon oxynitride, and/or other materials known in the art.
- the CESL 242 may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition processes.
- PECVD plasma-enhanced chemical vapor deposition
- the ILD layer 244 is then deposited over the CESL 242 .
- the ILD layer 244 includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials.
- TEOS tetraethylorthosilicate
- BPSG borophosphosilicate glass
- FSG fused silica glass
- PSG phosphosilicate glass
- BSG boron doped silicon glass
- the ILD layer 244 may be deposited by a PECVD process or other suitable deposition technique.
- the workpiece 200 may be annealed to improve integrity of the ILD layer 244 .
- the CESL 242 may be disposed directly on top surfaces of the source/drain features 240 .
- the workpiece 200 may be planarized by a planarization process to expose the dummy gate stack 220 .
- the planarization process may include a chemical mechanical planarization (CMP) process.
- CMP chemical mechanical planarization
- Exposure of the dummy gate stack 220 allows the removal of the dummy gate stack 220 and release of the channel layers 208 (including the covered channel layers 208 C and the exposed channel layers 208 E) from the sacrificial layers 206 .
- the removal of the dummy gate stack 220 results in a gate trench 246 over the channel regions 212 C, as shown in FIG. 17 .
- the removal of the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220 .
- the removal of the dummy gate stack 220 may be performed using as a selective wet etch, a selective dry etch, or a combination thereof that is selective to the dummy gate stack 220 .
- sidewalls of the channel layers 208 including the covered channel layers 208 C and the exposed channel layers 208 E
- the sacrificial layers 206 in the channel region 212 C are exposed in the gate trench 246 .
- the method 100 may include operations to selectively remove the sacrificial layers 206 between the channel layers 208 (including the covered channel layers 208 C and the exposed channel layers 208 E) in the channel region 212 C.
- the selective removal of the sacrificial layers 206 releases the channel layers 208 (including the covered channel layers 208 C and the exposed channel layers 208 E) in FIG. 17 to form channel members shown in FIG. 18 .
- the exposed channel layers 208 E are released as functional channel members 2080 F and the covered channel layers 208 C are released as dummy channel members 2080 D. Because the exposed channel layer 208 E in FIG.
- the released functional channel member 2080 F is also the bottommost channel member in FIG. 18 .
- the functional channel members 2080 F and dummy channel members 2080 D may be collectively referred to as channel members 2080 throughout the present disclosure.
- the selective removal of the sacrificial layers 206 also leaves behind space 248 between channel members 2080 .
- the selective removal of the sacrificial layers 206 may be implemented by selective dry etch, selective wet etch, or other selective etch processes.
- An example selective dry etching process may include use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons.
- An example selective wet etching process may include an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture).
- APM etch e.g., ammonia hydroxide-hydrogen peroxide-water mixture.
- the selectively removal of the sacrificial layers 206 may be referred to as a channel release process.
- the method 100 may include operations to form the gate structure 260 to wrap around each of the channel members 2080 .
- the gate structure 260 is formed within the gate trench 246 and into the space 248 left behind by the removal of the sacrificial layers 206 .
- the gate structure 260 wraps around each of the channel members 2080 , including the functional channel members 2080 F and dummy channel members 2080 D.
- the gate structure 260 includes a gate dielectric layer 254 and a gate electrode layer 256 over the gate dielectric layer 254 .
- the gate dielectric layer 254 includes an interfacial layer and a high-K gate dielectric layer.
- High-K dielectric materials include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide ( ⁇ 3.9).
- the interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride.
- the interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method.
- the high-K gate dielectric layer may include hafnium oxide.
- the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO 2 ), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta 2 O 5 ), hafnium silicon oxide (HfSiO 4 ), zirconium oxide (ZrO 2 ), zirconium silicon oxide (ZrSiO 2 ), lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO), yttrium oxide (Y 2 O 3 ), SrTiO 3 (STO), BaTiO 3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO 3 (BST), silicon nit
- the gate electrode layer 256 of the gate structure 260 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide.
- the gate electrode layer 256 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or a combination thereof.
- the gate electrode layer 256 may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process.
- a CMP process may be performed to remove excessive metal, thereby providing a substantially planar top surface of the gate structure 260 .
- the gate structure 260 includes portions that interpose between channel members 2080 in the channel region 212 C.
- a first MBC transistor 270 is substantially formed.
- the first MBC transistor 270 includes a functional channel member 2080 F and two dummy channel members 2080 D that are vertically stacked along the Z direction. Each of the channel members 2080 of the first MBC transistor 270 is wrapped around by the gate structure 260 .
- the functional channel member 2080 F extends or is sandwiched between two source/drain features 240 along the X direction, while the dummy channel members 2080 D are insulated from the source/drain features 240 by the blocking features 238 .
- the blocking features 238 shuts off the conduction path between the dummy channel members 2080 D and the source/drain features 240 , rendering them disabled, deactivated, or shut-off. It can be seen that, when the gate structure 260 of the first MBC transistor 270 is energized, the dummy channel members 2080 D may be turned on but are effectively shut off by the blocking features 238 .
- the source/drain features 240 is in contact with the inner spacer features 232 , the blocking features 238 , the substrate 202 , and the functional channel member 2080 F.
- the effective channel width of the first MBC transistor 270 is the channel width of the functional channel member 2080 F, which may be about twice the Y-direction dimension of the functional channel member 2080 F. Because the dummy channel members 2080 D are not operational, the effective resistance of the first MBC transistor 270 is governed by the channel resistance of the functional channel member 2080 F.
- FIGS. 20-22 illustrate alternative MBC transistor embodiments that include different numbers of functional channel members 2080 F and dummy channel members 2080 D.
- the MBC transistor embodiments in FIG. 20-22 may also be fabricated using method 100 in FIG. 1 by varying the height of the BARC layer 234 at block 116 .
- FIG. 20 illustrates a semiconductor device 200 that includes a second MBC transistor 280 .
- the second MBC transistor 280 includes two functional channel members 2080 F and one dummy channel members 2080 D stacked over the two functional channel members 2080 F.
- the recessing of the BARC layer 234 at block 116 is performed until that the BARC layer 234 covers/protects two bottom channel layers 208 while the top channel layer 208 is left exposed for trimming. Because the second MBC transistor 280 includes two functional channel members 2080 F, the effective channel width of the second MBC transistor 280 is about twice (2) of that of the first MBC transistor 270 . Given identical channel member dimensions, the effective resistance of the second MBC transistor 280 is about one-half (1 ⁇ 2) of that of the first MBC transistor 270 due to the additional functional channel member 2080 F.
- FIG. 21 illustrates a semiconductor device 200 that includes a third MBC transistor 290 .
- the third MBC transistor 290 does not include any functional channel members 2080 F. All of the channel members in the third MBC transistor 290 are dummy channel members 2080 D.
- the recessing of the BARC layer 234 at block 116 is performed until that the BARC layer 234 covers/protects all channel layers 208 . Because the third MBC transistor 290 does not include any functional channel members 2080 F, its channel is in the mesa structure 292 that is a portion of the substrate 202 .
- the third MBC transistor 290 may serve as a reference device or a high threshold voltage transistor. Because the mesa structure 292 provides a leakage path, a drive current of an MBC transistor may be compared against a drive current of the third MBC transistor 290 . The difference or surplus of the drive current may be regarded as the net drive current of the MBC transistor after taking account of the leakage current. Because the channel in the mesa structure 292 tends to have a high threshold voltage, the third MBC transistor 290 may also serve as a high threshold voltage (Vt) transistor, an input/output transistor, or an electrostatic discharge (ESD) protection device.
- Vt high threshold voltage
- ESD electrostatic discharge
- FIG. 22 illustrates a semiconductor device 200 that includes a fourth MBC transistor 300 .
- the fourth MBC transistor 300 includes three functional channel members 2080 F and no dummy channel members 2080 D.
- the recess of the BARC layer 234 at block 116 is performed until that the BARC layer 234 no longer covers/protects any of the channel layers 208 .
- the effective channel width of the fourth MBC transistor 300 is about three (3) times of that of the first MBC transistor 270 .
- the effective resistance of the second MBC transistor 280 is about one-third (1 ⁇ 3) of that of the first MBC transistor 270 due to the two additional functional channel members 2080 F. It is noted that while embodiments illustrated in FIGS. 19-22 include three channel members (functional and dummy channel members included), the present disclosure is not so limited. A person of ordinary skill in the art, after reviewing the descriptions and illustrations of the present disclosure, would appreciate that aspects of the present disclosure may be readily applicable to MBC transistors with less or more channel members in their channel regions.
- FIG. 23 Two or more of the first MBC transistor 270 in FIG. 19 , the second MBC transistor 280 in FIG. 20 , the third MBC transistor 290 in FIG. 21 , and the fourth MBC transistor 300 in FIG. 22 may be fabricated in the same semiconductor device 200 .
- the semiconductor device 200 includes all four types of MBC transistors. Each of these four types of MBC transistors may serve different functions.
- the fourth MBC transistor 300 may serve as a standard transistor while the first MBC transistor 270 and the second MBC transistor 280 may serve as high-resistance transistor.
- the effective channel width of the fourth MBC transistor 300 is about three times (3 ⁇ ) of that of the first MBC transistor 270 and is about 1.5 times (1.5 ⁇ ) of that of the second MBC transistor 280 .
- a high-resistance transistor may be regarded as a standard transistor plug a resistor. According, one or more of the standard transistors and one or more of the high-resistance transistors may be connected to form logic gates (e.g., AND, OR, NOR, NAND logic gates) or amplifiers.
- the third MBC transistor 290 may serve as a reference transistor, a high threshold voltage transistor, an input/output transistor, or an ESD prevention device. Although all four types of MBC transistors are present in the semiconductor device 200 in FIG. 19 , the semiconductor device 200 may include two types of the MBC transistors or three types of the MBC transistors. Additionally, different types of MBC transistors according to the present disclosure may be disposed in separate regions or may be placed adjacent to one another.
- FIG. 24 illustrates a flowchart of a method 400 for determining a parameter for the method 100 .
- Method 400 includes a block 402 where a function of an MBC transistor in a semiconductor device is determined.
- the function of the MBC transistor in the semiconductor device is determined based on properties of the MBC transistor in the design of the semiconductor device. Such properties may include the effective resistance, effective capacitance, effective channel width, desired drive current, and other aspects of the transistor.
- Method 400 also includes a block 404 where a number of channel members to be shut off is determined based on the function of the MBC transistors. For example, when the MBC transistor includes three vertically stacked channel members, the function determined at block 402 forms the basis to determine the number of the channel members to be shut off.
- Method 400 further includes a block 406 where a height of the BARC layer (along the Z direction in FIGS. 10 and 11 ) necessary to shut off the number of channel members is determined. As described above with respect to block 116 of method 100 and the alternative embodiments in FIGS. 20-22 , the thickness of the BARC layer 234 at block 116 determines how many channel layers will be protected and therefore how many channel members are to be shut off by the blocking features 238 .
- method 400 performs method 100 based on the determined thickness of the BARC layer 234 .
- method 400 may be performed with respect to each of the device regions.
- a photolithography step may be needed for each additional type of MBC transistor to form different heights of the BARC layer 234 in different device regions.
- methods of the present disclosure may include a blocking feature formation process after the formation of inner spacer features.
- the blocking feature formation process may form blocking features to selectively shut off a predetermined number of channel members to modulate the effective resistance, effective capacitance, drive current, or frequency to meet various design needs.
- the present disclosure is directed to a semiconductor device.
- the semiconductor device includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.
- the gate structure is spaced apart from the first source/drain feature by a plurality of inner spacer features.
- a composition of the at least one blocking feature is identical to a composition of the plurality of inner spacer features.
- the plurality of channel members includes a bottommost channel member that is nearest to the substrate. The bottommost channel member is coupled to the first source/drain feature and the second source/drain feature. In some instances, all of the plurality of channel members are isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature. In some embodiments, the plurality of channel members are vertically stacked.
- the present disclosure is directed to a semiconductor device.
- the semiconductor device includes a first transistor and a second transistor.
- the first transistor includes a first source/drain feature and a second source/drain feature, a first plurality of channel members extending between and in contact with the first source/drain feature and the second source/drain feature, a first gate structure wrapping around each of the first plurality of channel members.
- the second transistor includes a third source/drain feature and a fourth source/drain feature, a second plurality of channel members extending between the third source/drain feature and the fourth source/drain feature, a second gate structure wrapping around each of the second plurality of channel members, and first blocking features.
- One of the second plurality of channel members is isolated from the third source/drain feature and the fourth source/drain feature by the first blocking features.
- an effective channel width of the first transistor is greater than an effective channel width of the second transistor.
- the semiconductor device may further include a third transistor that includes a fifth source/drain feature and a sixth source/drain feature, a third plurality of channel members extending between the fifth source/drain feature and the sixth source/drain feature, a third gate structure wrapping around each of the third plurality of channel members, and second blocking features. Two of the third plurality of channel members are isolated from the fifth source/drain feature and the sixth source/drain feature by the second blocking features.
- an effective channel width of the second transistor is greater than an effective channel width of the third transistor.
- the semiconductor device may further include a fourth transistor that includes a seventh source/drain feature and an eighth source/drain feature, a fourth plurality of channel members extending between the seventh source/drain feature and the eighth source/drain feature, a fourth gate structure wrapping around each of the fourth plurality of channel members, and third blocking features, wherein all of the fourth plurality of channel members are isolated from the seventh source/drain feature and the eighth source/drain feature by the third blocking features.
- a threshold voltage of the fourth transistor is greater than a threshold voltage of the first transistor.
- the fourth transistor further includes a mesa structure below the fourth plurality of channel members and the fourth gate structure.
- the mesa structure is in contact with the seventh source/drain feature and the eighth source/drain feature.
- the fourth plurality of channel members are vertically stacked.
- the first plurality of channel members include a first number of channel members
- the second plurality of channel members include a second number of channel members
- fourth plurality of channel members include a third number of channel members. The first number, the second number, and third number are the same.
- the present disclosure is directed to a method.
- the method includes forming a stack over a substrate, wherein the stack includes a plurality of silicon layers interleaved by a plurality of silicon germanium layers, forming a fin-shaped structure from the stack and the substrate, the fin-shaped structure including a channel region and a source/drain region, recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, selectively and partially recessing the plurality of silicon germanium layers to form first inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, depositing a material layer in the source/drain trench to cover sidewalls of at least one of the plurality of silicon layers, after the depositing of the material layer, selectively recessing the plurality of silicon layers that are not covered by the material layer to form second inner spacer recesses, forming second inner spacer features in the
- the forming of the second inner spacer features includes depositing an inner spacer material layer over the first inner spacer features and the second inner spacer recesses and etching back the inner spacer material layer.
- the second inner spacer features are in contact with the at least one of the plurality of silicon layers.
- the material layer includes a bottom antireflective coating (BARC) layer.
- BARC bottom antireflective coating
- a composition of the first inner spacer features is identical to a composition of the second inner spacer features.
- the method may further include determining a function of the semiconductor device, and determining a thickness of the material layer based on the function of the semiconductor device, a thickness of each of the plurality of silicon layers, and a thickness of each of the plurality of silicon germanium layers.
Abstract
The present disclosure provides semiconductor devices and methods of forming the same. A semiconductor device of the present disclosure includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.
Description
- The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs.
- For example, as integrated circuit (IC) technologies progress towards smaller technology nodes, multi-gate metal-oxide-semiconductor field effect transistor (multi-gate MOSFET, or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure, or portion thereof, disposed over more than one side of a channel region. Fin-like field effect transistors (FinFETs) and multi-bridge-channel (MBC) transistors are examples of multi-gate devices that have become popular and promising candidates for high performance and low leakage applications. A FinFET has an elevated channel wrapped by a gate on more than one side (for example, the gate wraps a top and sidewalls of a “fin” of semiconductor material extending from a substrate). An MBC transistor has a gate structure that can extend, partially or fully, around a channel region to provide access to the channel region on two or more sides. Because its gate structure surrounds the channel regions, an MBC transistor may also be referred to as a surrounding gate transistor (SGT) or a gate-all-around (GAA) transistor.
- With multiple channel members that are wrapped around by a gate structure, an MBC transistor provides good drive current performance by increasing the effective channel width. While existing methods for forming MBC transistors are generally adequate for their intended purposes, they are satisfactory in all aspects.
- The present disclosure is best understood from the following detailed description when read with the accompanying figures. It is emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
-
FIG. 1 illustrates a flowchart of a method for forming a semiconductor device, according to one or more aspects of the present disclosure. -
FIGS. 2-22 illustrate fragmentary cross-sectional views of a workpiece during a fabrication process according to the method ofFIG. 1 , according to one or more aspects of the present disclosure. -
FIG. 23 illustrates a schematic top view of an IC device that includes various MBC transistors, according to one or more aspects of the present disclosure. -
FIG. 24 illustrates a flowchart of a method for determining a parameter for performing the method ofFIG. 1 , according to one or more aspects of the present disclosure. - The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
- Further, when a number or a range of numbers is described with “about,” “approximate,” and the like, the term is intended to encompass numbers that are within a reasonable range considering variations that inherently arise during manufacturing as understood by one of ordinary skill in the art. For example, the number or range of numbers encompasses a reasonable range including the number described, such as within +/−10% of the number described, based on known manufacturing tolerances associated with manufacturing a feature having a characteristic associated with the number. For example, a material layer having a thickness of “about 5 nm” can encompass a dimension range from 4.25 nm to 5.75 nm where manufacturing tolerances associated with depositing the material layer are known to be +/−15% by one of ordinary skill in the art. Still further, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
- The present disclosure is generally related to multi-gate transistors and fabrication methods, and more particularly to methods of fabricating MBC transistors of different configurations. Methods of the present disclosure may include a blocking feature formation process after the formation of inner spacer features. The blocking feature formation process may form blocking features to selectively shut off a predetermined number of channel members to modulate the effective resistance, effective capacitance, or drive current of an MBC transistor to meet various design needs. The blocking features are disposed between a to-be-shut-off channel member and adjacent source/drain features to electrically isolate the to-be-shut-off channel member. Methods of the present disclosure allow formation of MBC transistors that have similar dimensional but different effective channel widths.
- The various aspects of the present disclosure will now be described in more detail with reference to the figures. In that regard,
FIG. 1 is a flowchart illustrating amethod 100 of forming a semiconductor device from a workpiece according to embodiments of the present disclosure.Method 100 is merely an example and is not intended to limit the present disclosure to what is explicitly illustrated inmethod 100. Additional steps can be provided before, during and after themethod 100, and some steps described can be replaced, eliminated, or moved around for additional embodiments of the method. Not all steps are described herein in detail for reasons of simplicity.Method 100 is described below in conjunction withFIG. 2-22 , which are fragmentary cross-sectional views ofworkpiece 200 at different stages of fabrication according to embodiments of themethod 100 inFIG. 1 . Because theworkpiece 200 will be fabricated into a semiconductor device, theworkpiece 200 may be referred to herein as asemiconductor device 200 as the context requires. For avoidance, the X, Y and Z directions inFIGS. 2-20 are perpendicular to one another and are used consistently among the figures. Throughout the present disclosure, like reference numerals denote like features, unless otherwise excepted. - Referring to
FIGS. 1 and 2 ,method 100 includes ablock 102 where aworkpiece 200 is provided. As shown inFIG. 2 , theworkpiece 200 includes asubstrate 202. In some embodiments, thesubstrate 202 may be a semiconductor substrate such as a silicon (Si) substrate. Thesubstrate 202 may also include other semiconductors such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, thesubstrate 202 may include a compound semiconductor and/or an alloy semiconductor. Further, thesubstrate 202 may optionally include an epitaxial layer (epi-layer), may be strained for performance enhancement, may include a silicon-on-insulator (SOI) or a germanium-on-insulator (GeOI) structure, and/or may have other suitable enhancement features. - The
workpiece 200 further includes astack 204. In some embodiments represented inFIG. 2 , thestack 204 includessacrificial layers 206 of a first semiconductor composition interleaved bychannel layers 208 of a second semiconductor composition. The first and second semiconductor composition may be different. In some embodiments, thesacrificial layers 206 include silicon germanium (SiGe) and thechannel layers 208 include silicon (Si). It is noted that three (3) layers of thesacrificial layers 206 and three (3) layers of thechannel layers 208 are alternately arranged as illustrated inFIG. 2 , which is for illustrative purposes only and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of epitaxial layers may be formed in thestack 204. The number of layers depends on the desired number of channels members for thesemiconductor device 200. In some embodiments, the number ofchannel layers 208 is between 2 and 10. - In some embodiments, all
sacrificial layers 206 may have a substantially uniform first thickness between about 9 nm and about 10 nm and all of the channel layers 208 may have a substantially uniform second thickness between about 6 nm and about 8 nm. The first thickness and the second thickness may be identical or different. As described in more detail below, the channel layers 208 or parts thereof may serve as channel member(s) for a subsequently-formed multi-gate device and the thickness of each of the channel layers 208 is chosen based on device performance considerations. Thesacrificial layers 206 in channel regions(s) may eventually be removed and serve to define a vertical distance between adjacent channel region(s) for a subsequently-formed multi-gate device and the thickness of each of thesacrificial layers 206 is chosen based on device performance considerations. - The layers in the
stack 204 may be deposited using a molecular beam epitaxy (MBE) process, a vapor phase deposition (VPE) process, and/or other suitable epitaxial growth processes. As stated above, in at least some examples, thesacrificial layers 206 include an epitaxially grown silicon germanium (SiGe) layer and the channel layers 208 include an epitaxially grown silicon (Si) layer. In some embodiments, thesacrificial layers 206 and the channel layers 208 are substantially dopant-free (i.e., having an extrinsic dopant concentration from about 0 cm−3 to about 1×1017 cm−3), where for example, no intentional doping is performed during the epitaxial growth processes for thestack 204. - Referring still to
FIGS. 1 and 3 ,method 100 includes ablock 104 where a fin-shapedstructure 212 is formed from thestack 204 and thesubstrate 202. It is noted thatFIG. 2 includes a fragmentary cross-sectional view of theworkpiece 200 along the Y direction whileFIG. 3 illustrates a fragmentary cross-sectional view of theworkpiece 200 along the X direction. To pattern thestack 204, a hard mask layer 210 (shown inFIG. 2 ) may be deposited over thestack 204 to form an etch mask. Thehard mask layer 210 may be a single layer or a multi-layer. For example, thehard mask layer 210 may include a pad oxide layer and a pad nitride layer over the pad oxide layer. The fin-shapedstructure 212 may be patterned from thestack 204 and thesubstrate 202 using lithography processes and etch processes. The lithography process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etch process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. As shown inFIG. 3 , the etch process atblock 104 forms trenches extending through thestack 204 and a portion of thesubstrate 202. The trenches define the fin-shapedstructures 212. In some implementations, double-patterning or multi-patterning processes may be used to define fin-shaped structures that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned material layer using a self-aligned process. The material layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fin-shapedstructure 212 by etching thestack 204. As shown inFIG. 3 , the fin-shapedstructure 212, along with thesacrificial layers 206 and the channel layers 208 therein, extends vertically along the Z direction and lengthwise along the X direction. - At
block 104, anisolation feature 214 is formed adjacent the fin-shapedstructure 212. In some embodiments, theisolation feature 214 may be formed in the trenches to isolate the fin-shapedstructures 212 from a neighboring active region. Theisolation feature 214 may also be referred to as a shallow trench isolation (STI) feature 214. By way of example, in some embodiments, a dielectric layer is first deposited over thesubstrate 202, filling the trenches with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and/or other suitable materials. In various examples, the dielectric layer may be deposited by a CVD process, a subatmospheric CVD (SACVD) process, a flowable CVD process, a spin-on coating process, and/or other suitable process. The deposited dielectric material is then thinned and planarized, for example by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or pulled-back by a dry etching process, a wet etching process, and/or a combination thereof to form theSTI feature 214. The fin-shapedstructure 212 rises above theSTI feature 214 after the recessing. - Referring to
FIGS. 1, 4 and 5 ,method 100 includes ablock 106 where adummy gate stack 220 is formed over achannel region 212C of the fin-shapedstructure 212. It is noted thatFIG. 3 andFIG. 4 share the same viewing angle (along the X direction) whileFIG. 5 shares the same viewing angle (along the Y direction) withFIG. 2 . In some embodiments, a gate replacement process (or gate-last process) is adopted where the dummy gate stack 220 (shown inFIGS. 4 and 5 ) serves as a placeholder to undergo various processes and is to be removed and replaced by the functional gate structure. Other processes and configuration are possible. In some embodiments illustrated inFIG. 5 , thedummy gate stack 220 is formed over the fin-shapedstructure 212 and the fin-shapedstructure 212 may be divided intochannel regions 212C underlying the dummy gate stacks 220 and source/drain regions 212SD that do not underlie the dummy gate stacks 220. Thechannel regions 212C are adjacent the source/drain regions 212SD. As shown inFIG. 5 , thechannel region 212C is disposed between two source/drain regions 212SD along the X direction. - The formation of the
dummy gate stack 220 may include deposition of layers in thedummy gate stack 220 and patterning of these layers. Referring toFIG. 4 , adummy dielectric layer 216, adummy electrode layer 218, and a gate-tophard mask layer 222 may be deposited over theworkpiece 200. In some embodiments, thedummy dielectric layer 216 may be formed on the fin-shapedstructure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, a thermal oxidation process, or other suitable processes. In some instances, thedummy dielectric layer 216 may include silicon oxide. When thedummy dielectric layer 216 is formed using an oxidation process, it may be selectively formed on exposed surfaces of the fin-shapedstructure 212, as illustrated inFIG. 4 . Thereafter, thedummy electrode layer 218 may be deposited over thedummy dielectric layer 216 using a CVD process, an ALD process, or other suitable processes. In some instances, thedummy electrode layer 218 may include polysilicon (poly Si). For patterning purposes, the gate-tophard mask layer 222 may be deposited on thedummy electrode layer 218 using a CVD process, an ALD process, or other suitable processes. The gate-tophard mask layer 222, thedummy electrode layer 218 and thedummy dielectric layer 216 may then be patterned to form thedummy gate stack 220, as shown inFIG. 5 . For example, the patterning process may include a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and/or other etching methods. In some embodiments, the gate-tophard mask layer 222 may include asilicon oxide layer 223 and asilicon nitride layer 224 over thesilicon oxide layer 223. As shown inFIG. 5 , nodummy gate stack 220 is disposed over the source/drain region 212SD of the fin-shapedstructure 212. - Referring to
FIGS. 1 and 6 ,method 100 includes ablock 108 where at least onegate spacer layer 226 is deposited over thedummy gate stack 220. In some embodiments, the at least onegate spacer layer 226 is deposited conformally over theworkpiece 200, including over top surfaces and sidewalls of thedummy gate stack 220. The term “conformally” may be used herein for ease of description of a layer having substantially uniform thickness over various regions. The at least onegate spacer layer 226 may be a single layer or a multi-layer. In the depicted embodiments, the at least onegate spacer layer 226 includes afirst spacer layer 225 and asecond spacer layer 227 disposed over thefirst spacer layer 225. A composition of thefirst spacer layer 225 may be different from a composition of thesecond spacer layer 227. In some implementation, a dielectric constant of thefirst spacer layer 225 is greater than a dielectric constant of thesecond spacer layer 227. The at least onegate spacer layer 226, including thefirst spacer layer 225 and thesecond spacer layer 227, may include silicon oxide, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The at least onegate spacer layer 226 may be deposited over thedummy gate stack 220 using processes such as, a CVD process, a subatmospheric CVD (SACVD) process, an ALD process, or other suitable process. For ease of reference, the at least onegate spacer layer 226 may also be referred to thegate spacer layer 226 or topgate spacer layer 226. - Referring to
FIGS. 1 and 7 ,method 100 includes ablock 110 where a source/drain region 212SD of the fin-shapedstructure 212 is recessed to form a source/drain trench 228. In some embodiments, the source/drain regions 212SD that are not covered by thedummy gate stack 220 and sidewall portions of thegate spacer layer 226 are etched by a dry etch or a suitable etching process to form the source/drain trenches 228. For example, the dry etch process may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and/or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and/or BCl3), a bromine-containing gas (e.g., HBr and/or CHBR3), an iodine-containing gas, other suitable gases and/or plasmas, and/or combinations thereof. In some embodiments represented inFIG. 7 , the source/drain regions 212SD of the fin-shapedstructure 212 are recessed to expose sidewalls of thesacrificial layers 206 and the channel layers 208. In some implementations, the source/drain trenches 228 extend below thestack 204 into thesubstrate 202.FIG. 7 illustrates a cross-sectional view of theworkpiece 200 viewed along the Y direction at the source/drain region 212SD. As shown inFIG. 7 , thesacrificial layers 206 andchannel layers 208 in the source/drain region 212SD are removed atblock 110, exposing surfaces of thesubstrate 202 in the bottom of the source/drain trenches 228. - Referring to
FIGS. 1 and 8 ,method 100 includes ablock 112 where thesacrificial layers 206 are partially and selectively recessed to form first inner spacer recesses 230. Thesacrificial layers 206 exposed in the source/drain trenches 228 are selectively and partially recessed to form first inner spacer recesses 230 while thegate spacer layer 226, the exposed portion of thesubstrate 202, and the channel layers 208 are substantially unetched. In an embodiment where the channel layers 208 consist essentially of silicon (Si) andsacrificial layers 206 consist essentially of silicon germanium (SiGe), the selective recess of thesacrificial layers 206 may be performed using a selective wet etch process or a selective dry etch process. An example selective dry etching process may include use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An example selective wet etching process may include an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). While the etch process atblock 112 is selective, the exposed edge portions of the channel layers 208 may still be moderately etched or trimmed, as shown inFIG. 8 . - Referring to
FIGS. 1 and 9 ,method 100 includes ablock 114 where inner spacer features 232 are deposited into the first inner spacer recesses 230. After the first inner spacer recesses 230 are formed, an inner spacer material layer is conformally deposited over theworkpiece 200, including into the first inner spacer recesses 230. The inner spacer material layer may include metal oxides, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxide. While not explicitly shown, the inner spacer material layer may be a single layer or a multilayer. In some implementations, the inner spacer material layer may be deposited using CVD, PECVD, SACVD, ALD or other suitable methods. The deposited inner spacer material layer is then etched back to remove the inner spacer material layer from the sidewalls of the channel layers 208 to form the inner spacer features 232 in the first inner spacer recesses 230. In some implementations, the etch back operations performed atblock 114 may include use of hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. As shown inFIG. 9 , upon conclusion of the operations atblock 114, each of the inner spacer features 232 covers an end surface of asacrificial layer 206. - Referring to
FIGS. 1, 10, 11, and 12 ,method 100 includes ablock 116 where a portion of the channel layers 208 in thechannel regions 212C is selectively trimmed to form second inner spacer recesses 236. In some embodiments, the portion of the channel layers 208 to be selectively trimmed is controlled by a thickness of a bottom antireflective coating (BARC)layer 234. In other words, the number ofchannel layers 208 to be selectively trimmed may be controlled by controlling the thickness of theBARC layer 234. As will be described further below, the number ofchannel layers 208 to be selectively trimmed and eventually shut-off or blocked off is determined by the design for thesemiconductor device 200. An example process for selectively trimming a portion of the channel layers 208 to form second inner spacer recesses 236 is illustrated inFIGS. 10-12 . Referring toFIG. 10 , theBARC layer 234 may be deposited over theworkpiece 200 by spin-on coating or a suitable deposition process. In some implementations, theBARC layer 234 may include polysulfones, polyureas, polyurea sulfones, polyacrylates, poly(vinyl pyridine), or a silicon-containing polymer. In some instances, the depositedBARC layer 234 is not deposited directly to the desired height. Instead, it is deposited to a height to a thickness greater than a designed thickness and is then etched back until a desired height is reached. The etch back of theBARC layer 234 may include a dry etch process that uses a hydrogen plasma, an oxygen plasma, or a combination thereof. In the embodiment depicted inFIG. 10 , the etched backedBARC layer 234 covers and protects thebottommost channel layer 208 while theother channel layers 208 remained exposed. As will also be described below, depending on the design for thesemiconductor device 200, theBARC layer 234 may be recessed to cover more or less channel layers 208. For example, when all channellayers 208 in one device region are to be shut-off, theBARC layer 234 is allowed to cover all end surfaces of the channel layers 208. For another example, when none of the channel layers 208 in another device region are to be shut-off, theBARC layer 234 does not cover any of the end surfaces of the channel layers 208. - Referring to
FIG. 11 , the channel layers 208 in thechannel regions 212C that are not protected by theBARC layer 234 are selectively trimmed along the X direction to form the second inner spacer recesses 236. The trimming atblock 116 is selective to the channel layers 208 and etches thegate spacer layer 226, the inner spacer features 232 and theBARC layer 234 at a reduced rate. In some embodiments, the selective trimming of the exposedchannel layers 208 may include a selective wet etch process that uses a mixture of nitric acid and hydrofluoric acid, ethylenediamine pyrocatechol (EDP), tetramethylammonium hydroxide (TMAH), or a suitable wet etchant. In some other embodiments, the selective trimming of the exposedchannel layers 208 may include a selective wet etch process that uses plasma of fluorine-containing species (e.g. CF4, SF6, NF3, or CCl2F2) or chlorine-containing species (e.g. C2, CC2F2). In some instances, a depth of the second inner spacer recesses 236 may be substantially similar to a depth of the first inner spacer recesses 230 along the X direction. InFIG. 11 , thebottommost channel layer 208 is protected by theBARC layer 234 and is not trimmed atblock 116. Referring toFIG. 12 , after the selective trimming of the exposedchannel layers 208, theBARC layer 234 may be removed by using a suitable dry etch process or a suitable wet etch process. - Referring to
FIGS. 1, 13 and 14 ,method 100 includes ablock 118 where blocking inner spacer features 238 are formed in the second inner spacer recesses 236. After the second inner spacer recesses 236 are formed, a blocking innerspacer material layer 237 is conformally deposited over theworkpiece 200, including into the second inner spacer recesses 236. A composition of the blocking innerspacer material layer 237 may be similar to that of the inner spacer features 232. In some embodiments, the blocking innerspacer material layer 237 may include metal oxides, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or a low-k dielectric material. The metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxide. In some implementations, the blocking innerspacer material layer 237 may be deposited using CVD, PECVD, SACVD, ALD or other suitable methods. The deposited blocking innerspacer material layer 237 is then etched back to remove the blocking innerspacer material layer 237 from the sidewalls of the inner spacer features 232 and thegate spacer layer 226, thereby forming the blocking inner spacer features 238 in the second inner spacer recesses 236. In some implementations, the etch back operations performed atblock 118 may include use of hydrogen fluoride (HF), fluorine gas (F2), hydrogen (H2), ammonia (NH3), nitrogen trifluoride (NF3), or other fluorine-based etchants. As shown inFIG. 14 , upon conclusion of the operations atblock 118, each of the blocking inner spacer features 238 caps off end surfaces of the channel layers 208 that are not protected by theBARC layer 234. In that sense the blocking inner spacer features 238 may also be referred to as blocking features 238 or deactivation features 238. - Reference is still made to
FIG. 14 . For ease of reference and identification, the channel layers 208 that are covered by the blocking features 238 are referred to hereinafter as coveredchannel layers 208C and the channel layers 208 that are not covered by the blocking features 238 are referred to hereinafter as exposedchannel layers 208E. The coveredchannel layers 208C and the exposedchannel layers 208E may be referred collectively as channel layers 208. In the embodiments represented inFIG. 14 , theworkpiece 200 includes one exposedchannel layer 208E and two covered channel layers 208C. Due to the selectively trimming atblock 116, a length of the exposedchannel layer 208E along the X direction is greater than a length of the coveredchannel layer 208C by about two times the thicknesses of the blocking features 238. - Referring to
FIGS. 1 and 15 ,method 100 includes ablock 120 where source/drain features 240 are formed over the source/drain regions 212SD. The source/drain feature 240 may be epitaxially and selectively formed from the sidewalls of the exposedchannel layer 208E and exposed surfaces of thesubstrate 202, while sidewalls of thesacrificial layers 206 remain covered by the inner spacer features 232 and sidewalls of the coveredchannel layers 208C remain covered by the blocking features 238. Suitable epitaxial processes forblock 120 include vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and/or other suitable processes. The epitaxial growth process atblock 120 may use gaseous precursors, which interact with the composition of thesubstrate 202 and the channel layers 208. In some embodiments represented inFIG. 15 , overgrowth of the source/drain feature 240 may extend over sidewalls of theinner spacer feature 232 and the blocking features 238. Depending on the conductivity type of the MBC transistor on thesemiconductor device 200, the source/drain feature 240 may have different compositions. When the MBC transistor is n-type, the source/drain feature 240 may include silicon (Si) and may be doped with an n-type dopant, such as phosphorus (P) or arsenic (As). When the MBC transistor is p-type, the source/drain feature 240 may include silicon germanium (SiGe) and is doped with a p-type dopant, such as boron (B) or gallium (Ga). While not explicitly shown inFIG. 15 , the source/drain feature 240 may include two or more epitaxial layers. For example, the source/drain feature 240 may include a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer that are doped with the same type of dopant but at different doping concentrations to reduce defect density and contact resistance. In one embodiment, the source/drain feature 240 may include phosphorus-doped silicon (Si:P) when n-type MBC transistors are desired and may include boron-doped silicon germanium (SiGe:B) when p-type MBC transistors are desired. As shown inFIG. 15 , while the exposedchannel layer 208E extends between and are coupled to the source/drain features 240, the covered channel layers 208C are insulated or separated from the source/drain features 240 by the blocking features 238. - Referring to
FIGS. 1 and 16-19 ,method 100 includes ablock 122 where further processes are performed. Such further processes may include, for example, deposition of a contact etch stop layer (CESL) 242 over the workpiece 200 (shown inFIG. 16 ), deposition of an interlayer dielectric (ILD)layer 244 over the CESL 242 (shown inFIG. 16 ), removal of the dummy gate stack 220 (shown inFIG. 17 ), selective removal of thesacrificial layers 206 in thechannel region 212C to release the channel layers 208 as channel members 2080 (shown inFIG. 18 ), and formation of agate structure 260 over thechannel region 212C (shown inFIG. 19 ). Referring now toFIGS. 16 , theCESL 242 is formed prior to forming theILD layer 244. In some examples, theCESL 242 includes silicon nitride, silicon oxynitride, and/or other materials known in the art. TheCESL 242 may be formed by ALD, plasma-enhanced chemical vapor deposition (PECVD) process and/or other suitable deposition processes. TheILD layer 244 is then deposited over theCESL 242. In some embodiments, theILD layer 244 includes materials such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. TheILD layer 244 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of theILD layer 244, theworkpiece 200 may be annealed to improve integrity of theILD layer 244. As shown inFIG. 16 , theCESL 242 may be disposed directly on top surfaces of the source/drain features 240. - Referring still to
FIG. 16 , after the deposition of theCESL 242 and theILD layer 244, theworkpiece 200 may be planarized by a planarization process to expose thedummy gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. Exposure of thedummy gate stack 220 allows the removal of thedummy gate stack 220 and release of the channel layers 208 (including the coveredchannel layers 208C and the exposedchannel layers 208E) from thesacrificial layers 206. The removal of thedummy gate stack 220 results in agate trench 246 over thechannel regions 212C, as shown inFIG. 17 . The removal of thedummy gate stack 220 may include one or more etching processes that are selective to the material of thedummy gate stack 220. For example, the removal of thedummy gate stack 220 may be performed using as a selective wet etch, a selective dry etch, or a combination thereof that is selective to thedummy gate stack 220. After the removal of thedummy gate stack 220, sidewalls of the channel layers 208 (including the coveredchannel layers 208C and the exposedchannel layers 208E) and thesacrificial layers 206 in thechannel region 212C are exposed in thegate trench 246. - Referring to
FIG. 18 , after the removal of thedummy gate stack 220, themethod 100 may include operations to selectively remove thesacrificial layers 206 between the channel layers 208 (including the coveredchannel layers 208C and the exposedchannel layers 208E) in thechannel region 212C. The selective removal of thesacrificial layers 206 releases the channel layers 208 (including the coveredchannel layers 208C and the exposedchannel layers 208E) inFIG. 17 to form channel members shown inFIG. 18 . As illustrated inFIG. 18 , the exposedchannel layers 208E are released asfunctional channel members 2080F and the covered channel layers 208C are released asdummy channel members 2080D. Because the exposedchannel layer 208E inFIG. 17 is the bottommost channel layer that is closest to the substrate, the releasedfunctional channel member 2080F is also the bottommost channel member inFIG. 18 . For ease of reference, thefunctional channel members 2080F anddummy channel members 2080D may be collectively referred to aschannel members 2080 throughout the present disclosure. The selective removal of thesacrificial layers 206 also leaves behindspace 248 betweenchannel members 2080. The selective removal of thesacrificial layers 206 may be implemented by selective dry etch, selective wet etch, or other selective etch processes. An example selective dry etching process may include use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. An example selective wet etching process may include an APM etch (e.g., ammonia hydroxide-hydrogen peroxide-water mixture). The selectively removal of thesacrificial layers 206 may be referred to as a channel release process. - Referring now to
FIG. 19 , themethod 100 may include operations to form thegate structure 260 to wrap around each of thechannel members 2080. In some embodiments, thegate structure 260 is formed within thegate trench 246 and into thespace 248 left behind by the removal of thesacrificial layers 206. In this regard, thegate structure 260 wraps around each of thechannel members 2080, including thefunctional channel members 2080F anddummy channel members 2080D. Thegate structure 260 includes agate dielectric layer 254 and agate electrode layer 256 over thegate dielectric layer 254. In some embodiments, while not explicitly shown in the figures, thegate dielectric layer 254 includes an interfacial layer and a high-K gate dielectric layer. High-K dielectric materials, as used and described herein, include dielectric materials having a high dielectric constant, for example, greater than that of thermal silicon oxide (˜3.9). The interfacial layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interfacial layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and/or other suitable method. The high-K gate dielectric layer may include hafnium oxide. Alternatively, the high-K gate dielectric layer may include other high-K dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable material. The high-K gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and/or other suitable methods. - The
gate electrode layer 256 of thegate structure 260 may include a single layer or alternatively a multi-layer structure, such as various combinations of a metal layer with a selected work function to enhance the device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, a metal alloy or a metal silicide. By way of example, thegate electrode layer 256 may include titanium nitride (TiN), titanium aluminum (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), tantalum aluminum (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metal materials or a combination thereof. In various embodiments, thegate electrode layer 256 may be formed by ALD, PVD, CVD, e-beam evaporation, or other suitable process. In various embodiments, a CMP process may be performed to remove excessive metal, thereby providing a substantially planar top surface of thegate structure 260. Thegate structure 260 includes portions that interpose betweenchannel members 2080 in thechannel region 212C. - Reference is made to
FIG. 19 . Upon conclusion of the operations atblock 122, afirst MBC transistor 270 is substantially formed. Thefirst MBC transistor 270 includes afunctional channel member 2080F and twodummy channel members 2080D that are vertically stacked along the Z direction. Each of thechannel members 2080 of thefirst MBC transistor 270 is wrapped around by thegate structure 260. Thefunctional channel member 2080F extends or is sandwiched between two source/drain features 240 along the X direction, while thedummy channel members 2080D are insulated from the source/drain features 240 by the blocking features 238. The blocking features 238 shuts off the conduction path between thedummy channel members 2080D and the source/drain features 240, rendering them disabled, deactivated, or shut-off. It can be seen that, when thegate structure 260 of thefirst MBC transistor 270 is energized, thedummy channel members 2080D may be turned on but are effectively shut off by the blocking features 238. The source/drain features 240 is in contact with the inner spacer features 232, the blocking features 238, thesubstrate 202, and thefunctional channel member 2080F. Because twodummy channel members 2080D of thefirst MBC transistor 270 are not operational, the effective channel width of thefirst MBC transistor 270 is the channel width of thefunctional channel member 2080F, which may be about twice the Y-direction dimension of thefunctional channel member 2080F. Because thedummy channel members 2080D are not operational, the effective resistance of thefirst MBC transistor 270 is governed by the channel resistance of thefunctional channel member 2080F. -
FIGS. 20-22 illustrate alternative MBC transistor embodiments that include different numbers offunctional channel members 2080F anddummy channel members 2080D. The MBC transistor embodiments inFIG. 20-22 may also be fabricated usingmethod 100 inFIG. 1 by varying the height of theBARC layer 234 atblock 116.FIG. 20 illustrates asemiconductor device 200 that includes asecond MBC transistor 280. Unlike thefirst MBC transistor 270 inFIG. 19 , thesecond MBC transistor 280 includes twofunctional channel members 2080F and onedummy channel members 2080D stacked over the twofunctional channel members 2080F. To fabricate thesecond MBC transistor 280 usingmethod 100, the recessing of theBARC layer 234 atblock 116 is performed until that theBARC layer 234 covers/protects two bottom channel layers 208 while thetop channel layer 208 is left exposed for trimming. Because thesecond MBC transistor 280 includes twofunctional channel members 2080F, the effective channel width of thesecond MBC transistor 280 is about twice (2) of that of thefirst MBC transistor 270. Given identical channel member dimensions, the effective resistance of thesecond MBC transistor 280 is about one-half (½) of that of thefirst MBC transistor 270 due to the additionalfunctional channel member 2080F. -
FIG. 21 illustrates asemiconductor device 200 that includes athird MBC transistor 290. Unlike thefirst MBC transistor 270 inFIG. 19 , thethird MBC transistor 290 does not include anyfunctional channel members 2080F. All of the channel members in thethird MBC transistor 290 aredummy channel members 2080D. To fabricate thethird MBC transistor 290 usingmethod 100, the recessing of theBARC layer 234 atblock 116 is performed until that theBARC layer 234 covers/protects all channel layers 208. Because thethird MBC transistor 290 does not include anyfunctional channel members 2080F, its channel is in themesa structure 292 that is a portion of thesubstrate 202. Thethird MBC transistor 290 may serve as a reference device or a high threshold voltage transistor. Because themesa structure 292 provides a leakage path, a drive current of an MBC transistor may be compared against a drive current of thethird MBC transistor 290. The difference or surplus of the drive current may be regarded as the net drive current of the MBC transistor after taking account of the leakage current. Because the channel in themesa structure 292 tends to have a high threshold voltage, thethird MBC transistor 290 may also serve as a high threshold voltage (Vt) transistor, an input/output transistor, or an electrostatic discharge (ESD) protection device. -
FIG. 22 illustrates asemiconductor device 200 that includes afourth MBC transistor 300. Unlike thefirst MBC transistor 270 inFIG. 19 , thefourth MBC transistor 300 includes threefunctional channel members 2080F and nodummy channel members 2080D. To fabricate thefourth MBC transistor 300 usingmethod 100, the recess of theBARC layer 234 atblock 116 is performed until that theBARC layer 234 no longer covers/protects any of the channel layers 208. Because thefourth MBC transistor 300 includes threefunctional channel members 2080F, the effective channel width of thefourth MBC transistor 300 is about three (3) times of that of thefirst MBC transistor 270. Given identical channel member dimensions, the effective resistance of thesecond MBC transistor 280 is about one-third (⅓) of that of thefirst MBC transistor 270 due to the two additionalfunctional channel members 2080F. It is noted that while embodiments illustrated inFIGS. 19-22 include three channel members (functional and dummy channel members included), the present disclosure is not so limited. A person of ordinary skill in the art, after reviewing the descriptions and illustrations of the present disclosure, would appreciate that aspects of the present disclosure may be readily applicable to MBC transistors with less or more channel members in their channel regions. - Reference is made to
FIG. 23 . Two or more of thefirst MBC transistor 270 inFIG. 19 , thesecond MBC transistor 280 inFIG. 20 , thethird MBC transistor 290 inFIG. 21 , and thefourth MBC transistor 300 inFIG. 22 may be fabricated in thesame semiconductor device 200. In the depicted embodiment, thesemiconductor device 200 includes all four types of MBC transistors. Each of these four types of MBC transistors may serve different functions. In some embodiments, thefourth MBC transistor 300 may serve as a standard transistor while thefirst MBC transistor 270 and thesecond MBC transistor 280 may serve as high-resistance transistor. As described above, the effective channel width of thefourth MBC transistor 300 is about three times (3×) of that of thefirst MBC transistor 270 and is about 1.5 times (1.5×) of that of thesecond MBC transistor 280. In circuit design, a high-resistance transistor may be regarded as a standard transistor plug a resistor. According, one or more of the standard transistors and one or more of the high-resistance transistors may be connected to form logic gates (e.g., AND, OR, NOR, NAND logic gates) or amplifiers. Thethird MBC transistor 290 may serve as a reference transistor, a high threshold voltage transistor, an input/output transistor, or an ESD prevention device. Although all four types of MBC transistors are present in thesemiconductor device 200 inFIG. 19 , thesemiconductor device 200 may include two types of the MBC transistors or three types of the MBC transistors. Additionally, different types of MBC transistors according to the present disclosure may be disposed in separate regions or may be placed adjacent to one another. -
FIG. 24 illustrates a flowchart of amethod 400 for determining a parameter for themethod 100.Method 400 includes ablock 402 where a function of an MBC transistor in a semiconductor device is determined. In some embodiments, the function of the MBC transistor in the semiconductor device is determined based on properties of the MBC transistor in the design of the semiconductor device. Such properties may include the effective resistance, effective capacitance, effective channel width, desired drive current, and other aspects of the transistor.Method 400 also includes ablock 404 where a number of channel members to be shut off is determined based on the function of the MBC transistors. For example, when the MBC transistor includes three vertically stacked channel members, the function determined atblock 402 forms the basis to determine the number of the channel members to be shut off. In this aspect, increasing the number of channel members to be shut off increases the effective resistance and reduces effective channel width of the MBC transistor.Method 400 further includes ablock 406 where a height of the BARC layer (along the Z direction inFIGS. 10 and 11 ) necessary to shut off the number of channel members is determined. As described above with respect to block 116 ofmethod 100 and the alternative embodiments inFIGS. 20-22 , the thickness of theBARC layer 234 atblock 116 determines how many channel layers will be protected and therefore how many channel members are to be shut off by the blocking features 238. With respect tomethod 100, athicker BARC layer 234 protectsmore channel layers 208 from trimming and leads to morefunctional channel members 2080F and athinner BARC layer 234 protects less channel layers 208 from trimming and lead to moredummy channel members 2080D. Finally, atblock 408,method 400 performsmethod 100 based on the determined thickness of theBARC layer 234. To implement thesemiconductor device 200 inFIG. 23 ,method 400 may be performed with respect to each of the device regions. In some embodiments, a photolithography step may be needed for each additional type of MBC transistor to form different heights of theBARC layer 234 in different device regions. - Although not intended to be limiting, one or more embodiments of the present disclosure provide many benefits to a semiconductor device and the formation thereof. For example, methods of the present disclosure may include a blocking feature formation process after the formation of inner spacer features. The blocking feature formation process may form blocking features to selectively shut off a predetermined number of channel members to modulate the effective resistance, effective capacitance, drive current, or frequency to meet various design needs.
- In one exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a first source/drain feature and a second source/drain feature over a substrate, a plurality of channel members extending between the first source/drain feature and the second source/drain feature, a gate structure wrapping around each of the plurality of channel members, and at least one blocking feature. At least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.
- In some embodiments, the gate structure is spaced apart from the first source/drain feature by a plurality of inner spacer features. A composition of the at least one blocking feature is identical to a composition of the plurality of inner spacer features. In some instances, the plurality of channel members includes a bottommost channel member that is nearest to the substrate. The bottommost channel member is coupled to the first source/drain feature and the second source/drain feature. In some instances, all of the plurality of channel members are isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature. In some embodiments, the plurality of channel members are vertically stacked.
- In another exemplary aspect, the present disclosure is directed to a semiconductor device. The semiconductor device includes a first transistor and a second transistor. The first transistor includes a first source/drain feature and a second source/drain feature, a first plurality of channel members extending between and in contact with the first source/drain feature and the second source/drain feature, a first gate structure wrapping around each of the first plurality of channel members. The second transistor includes a third source/drain feature and a fourth source/drain feature, a second plurality of channel members extending between the third source/drain feature and the fourth source/drain feature, a second gate structure wrapping around each of the second plurality of channel members, and first blocking features. One of the second plurality of channel members is isolated from the third source/drain feature and the fourth source/drain feature by the first blocking features.
- In some embodiments, an effective channel width of the first transistor is greater than an effective channel width of the second transistor. In some implementations, the semiconductor device may further include a third transistor that includes a fifth source/drain feature and a sixth source/drain feature, a third plurality of channel members extending between the fifth source/drain feature and the sixth source/drain feature, a third gate structure wrapping around each of the third plurality of channel members, and second blocking features. Two of the third plurality of channel members are isolated from the fifth source/drain feature and the sixth source/drain feature by the second blocking features.
- In some embodiments, an effective channel width of the second transistor is greater than an effective channel width of the third transistor. In some implementations, the semiconductor device may further include a fourth transistor that includes a seventh source/drain feature and an eighth source/drain feature, a fourth plurality of channel members extending between the seventh source/drain feature and the eighth source/drain feature, a fourth gate structure wrapping around each of the fourth plurality of channel members, and third blocking features, wherein all of the fourth plurality of channel members are isolated from the seventh source/drain feature and the eighth source/drain feature by the third blocking features. In some instances, a threshold voltage of the fourth transistor is greater than a threshold voltage of the first transistor. In some embodiments, the fourth transistor further includes a mesa structure below the fourth plurality of channel members and the fourth gate structure. The mesa structure is in contact with the seventh source/drain feature and the eighth source/drain feature. In some embodiments, the fourth plurality of channel members are vertically stacked. In some implementations, the first plurality of channel members include a first number of channel members, the second plurality of channel members include a second number of channel members, fourth plurality of channel members include a third number of channel members. The first number, the second number, and third number are the same.
- In yet another exemplary aspect, the present disclosure is directed to a method. The method includes forming a stack over a substrate, wherein the stack includes a plurality of silicon layers interleaved by a plurality of silicon germanium layers, forming a fin-shaped structure from the stack and the substrate, the fin-shaped structure including a channel region and a source/drain region, recessing the source/drain region to form a source/drain trench that exposes sidewalls of the plurality of silicon layers and the plurality of silicon germanium layers, selectively and partially recessing the plurality of silicon germanium layers to form first inner spacer recesses, forming first inner spacer features in the first inner spacer recesses, depositing a material layer in the source/drain trench to cover sidewalls of at least one of the plurality of silicon layers, after the depositing of the material layer, selectively recessing the plurality of silicon layers that are not covered by the material layer to form second inner spacer recesses, forming second inner spacer features in the second inner spacer recesses, and after the forming of the second inner spacer features, depositing a source/drain feature in the source/drain trench.
- In some embodiments, the forming of the second inner spacer features includes depositing an inner spacer material layer over the first inner spacer features and the second inner spacer recesses and etching back the inner spacer material layer. In some implementations, the second inner spacer features are in contact with the at least one of the plurality of silicon layers. In some instances, the material layer includes a bottom antireflective coating (BARC) layer. In some embodiments, a composition of the first inner spacer features is identical to a composition of the second inner spacer features. In some instances, the method may further include determining a function of the semiconductor device, and determining a thickness of the material layer based on the function of the semiconductor device, a thickness of each of the plurality of silicon layers, and a thickness of each of the plurality of silicon germanium layers.
- The foregoing outlines features of several embodiments so that those of ordinary skill in the art may better understand the aspects of the present disclosure. Those of ordinary skill in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Claims (21)
1. A semiconductor device, comprising:
a first source/drain feature and a second source/drain feature over a substrate;
a plurality of channel members extending between the first source/drain feature and the second source/drain feature;
a gate structure wrapping around each of the plurality of channel members; and
at least one blocking feature,
wherein at least one of the plurality of channel members is isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.
2. The semiconductor device of claim 1 ,
wherein the gate structure is spaced apart from the first source/drain feature by a plurality of inner spacer features,
wherein a composition of the at least one blocking feature is identical to a composition of the plurality of inner spacer features.
3. The semiconductor device of claim 1 ,
wherein the plurality of channel members comprises a bottommost channel member that is nearest to the substrate,
wherein the bottommost channel member is coupled to the first source/drain feature and the second source/drain feature.
4. The semiconductor device of claim 1 , wherein all of the plurality of channel members are isolated from the first source/drain feature and the second source/drain feature by the at least one blocking feature.
5. The semiconductor device of claim 1 , wherein the plurality of channel members are vertically stacked.
6. A semiconductor device, comprising:
a first transistor, the first transistor comprising:
a first source/drain feature and a second source/drain feature,
a first plurality of channel members extending between and in contact with the first source/drain feature and the second source/drain feature,
a first gate structure wrapping around each of the first plurality of channel members, and
a second transistor, the second transistor comprising:
a third source/drain feature and a fourth source/drain feature,
a second plurality of channel members extending between the third source/drain feature and the fourth source/drain feature,
a second gate structure wrapping around each of the second plurality of channel members, and
first blocking features, wherein one of the second plurality of channel members is isolated from the third source/drain feature and the fourth source/drain feature by the first blocking features.
7. The semiconductor device of claim 6 , wherein an effective channel width of the first transistor is greater than an effective channel width of the second transistor.
8. The semiconductor device of claim 6 , further comprising:
a third transistor, the third transistor comprising:
a fifth source/drain feature and a sixth source/drain feature,
a third plurality of channel members extending between the fifth source/drain feature and the sixth source/drain feature,
a third gate structure wrapping around each of the third plurality of channel members, and
second blocking features, wherein two of the third plurality of channel members are isolated from the fifth source/drain feature and the sixth source/drain feature by the second blocking features.
9. The semiconductor device of claim 8 , wherein an effective channel width of the second transistor is greater than an effective channel width of the third transistor.
10. The semiconductor device of claim 6 , further comprising:
a fourth transistor, the fourth transistor comprising:
a seventh source/drain feature and an eighth source/drain feature,
a fourth plurality of channel members extending between the seventh source/drain feature and the eighth source/drain feature,
a fourth gate structure wrapping around each of the fourth plurality of channel members, and
third blocking features, wherein all of the fourth plurality of channel members are isolated from the seventh source/drain feature and the eighth source/drain feature by the third blocking features.
11. The semiconductor device of claim 10 , wherein a threshold voltage of the fourth transistor is greater than a threshold voltage of the first transistor.
12. The semiconductor device of claim 10 ,
wherein the fourth transistor further comprises a mesa structure below the fourth plurality of channel members and the fourth gate structure,
wherein the mesa structure is in contact with the seventh source/drain feature and the eighth source/drain feature.
13. The semiconductor device of claim 10 , wherein the fourth plurality of channel members are vertically stacked.
14. The semiconductor device of claim 10 ,
wherein the first plurality of channel members comprise a first number of channel members,
wherein the second plurality of channel members comprise a second number of channel members,
wherein the fourth plurality of channel members comprise a third number of channel members,
wherein the first number, the second number, and the third number are the same.
15-20. (canceled)
21. A semiconductor structure, comprising:
a first source/drain feature and a second source/drain feature over a substrate; and
a plurality of channel members extending between the first source/drain feature and the second source/drain feature along a direction,
wherein a first channel member of the plurality of channel members is in direct contact with the first source/drain feature and the second source/drain feature,
wherein a second channel member of the plurality of channel members is spaced apart from the first source/drain feature by a first blocking feature and spaced apart from the second source/drain feature by a second blocking feature.
22. The semiconductor structure of claim 21 , wherein the second channel member is disposed over the first channel member.
23. The semiconductor structure of claim 21 , wherein a length of the first channel member along the direction is greater than a length of the second channel member along the direction.
24. The semiconductor structure of claim 21 ,
wherein the plurality of channel members comprise silicon,
wherein the first blocking feature and the second blocking feature comprise aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, silicon oxide, silicon oxycarbonitride, silicon nitride, silicon oxynitride, or carbon-rich silicon carbonitride.
25. The semiconductor structure of claim 21 , further comprising:
a gate structure wrapping around each of the plurality of channel members.
26. The semiconductor structure of claim 25 , wherein the gate structure is spaced apart from the first source/drain feature by a plurality of inner spacer features.
Priority Applications (5)
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US17/101,212 US11362217B1 (en) | 2020-11-23 | 2020-11-23 | Method of forming transistors of different configurations |
TW110126258A TW202221928A (en) | 2020-11-23 | 2021-07-16 | Semiconductor device |
CN202110879905.0A CN114284265A (en) | 2020-11-23 | 2021-08-02 | Semiconductor device with a plurality of semiconductor chips |
US17/838,560 US11715803B2 (en) | 2020-11-23 | 2022-06-13 | Method of forming transistors of different configurations |
US18/357,523 US20230369513A1 (en) | 2020-11-23 | 2023-07-24 | Method of forming transistors of different configurations |
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US17/101,212 US11362217B1 (en) | 2020-11-23 | 2020-11-23 | Method of forming transistors of different configurations |
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US17/838,560 Division US11715803B2 (en) | 2020-11-23 | 2022-06-13 | Method of forming transistors of different configurations |
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US20220165881A1 true US20220165881A1 (en) | 2022-05-26 |
US11362217B1 US11362217B1 (en) | 2022-06-14 |
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ID=80868359
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US17/101,212 Active US11362217B1 (en) | 2020-11-23 | 2020-11-23 | Method of forming transistors of different configurations |
US17/838,560 Active US11715803B2 (en) | 2020-11-23 | 2022-06-13 | Method of forming transistors of different configurations |
US18/357,523 Pending US20230369513A1 (en) | 2020-11-23 | 2023-07-24 | Method of forming transistors of different configurations |
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Also Published As
Publication number | Publication date |
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US11362217B1 (en) | 2022-06-14 |
US20230369513A1 (en) | 2023-11-16 |
US11715803B2 (en) | 2023-08-01 |
CN114284265A (en) | 2022-04-05 |
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US20220310851A1 (en) | 2022-09-29 |
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