US20220059352A1

US20220059352A1 - GaN Devices With Ion Implanted Ohmic Contacts and Method of Fabricating Devices Incorporating the Same

Info

Publication number: US20220059352A1
Application number: US17/520,821
Authority: US
Inventors: Travis J. Anderson; James C. Gallagher; Marko J. Tadjer; Alan G. Jacobs; Boris N. Feigelson
Original assignee: US Department of Navy
Current assignee: US Department of Navy
Priority date: 2019-07-26
Filing date: 2021-11-08
Publication date: 2022-02-24
Also published as: US11532478B2; US20220059353A1; US20210028020A1; US20230207323A1; US20220254639A1; US11201058B2; US11817318B2

Abstract

A method for activating implanted dopants and repairing damage to dopant-implanted GaN to form n-type or p-type GaN. A GaN substrate is implanted with n- or p-type ions and is subjected to a high-temperature anneal to activate the implanted dopants and to produce planar n- or p-type doped areas within the GaN having an activated dopant concentration of about 10¹⁸-10²²cm⁻³. An initial annealing at a temperature at which the GaN is stable at a predetermined process temperature for a predetermined time can be conducted before the high-temperature anneal. A thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step. The high-temperature annealing can be conducted under N₂pressure to increase the stability of the GaN. The annealing can be conducted using laser annealing or rapid thermal annealing (RTA).

Description

CROSS-REFERENCE

This application is a Divisional of and claims the benefit of priority under 35 U.S.C. § 120 based on U.S. patent application Ser. No. 16/927,061 filed on Jul. 13, 2020, which is a Nonprovisional of and claims the benefit of priority under 35 U.S.C. § 119 based on Provisional U.S. Patent Application No. 62/878,766 filed on Jul. 26, 2019. The prior applications and all cited references are hereby incorporated by reference into the present disclosure in their entirety.

FEDERALLY-SPONSORED RESEARCH AND DEVELOPMENT

The United States Government has ownership rights in this invention. Licensing inquiries may be directed to Office of Technology Transfer, US Naval Research Laboratory, Code 1004, Washington, D.C. 20375, USA; +1.202.767.7230; techtran@nrl.navy.mil, referencing Navy Case #111399.

TECHNICAL FIELD

The present disclosure relates to GaN-based electronic devices, and in particular to ion-implanted ohmic contacts to such GaN-based devices and methods for fabricating lateral and vertical electronic devices incorporating such ion-implanted ohmic contacts.

BACKGROUND

GaN is a superior material for the fabrication of high frequency and high power devices. The high electron mobility transistor (HEMT) has proven to be a groundbreaking technology for RF power amplifiers for both civilian and defense applications. To achieve high power density and high efficiency in such devices, extremely low resistance ohmic contacts are required for the source and drain region of the transistor. The present industry standard for fabrication of low resistance ohmic contacts is the selective area regrowth method, which can form highly conductive N+ GaN regions.
However, ion implantation offers several advantages over the selective area regrowth method. Ion implantation reduces the number of steps in the fabrication process, prevents impurity formation from occurring at the implant/regrowth interface, allows the process to make the device truly planar thus reducing the number of critical field points, and allows tailoring of both vertical and lateral profile doping. The cycle time required for ion implantation and activation annealing is much less than for epitaxial growth, multiple wafers can be run at the same time, thus substantially improving throughput, and the identical process can be applied to both Ga-polar and N-polar structures without any special modifications. In addition, lateral devices such as photoconductive switches and p-n junction gated field effect transistors (LJFET), as well as vertical devices such as p-n junction gated field effect transistors (JFET), current aperture vertical electron transistors (CAVET), double diffused metal oxide semiconductor field effect transistors (DMOS), and trench MOSFET devices could all also potentially utilize this technology, since selective-area doping is required for all of these devices.
Ion implantation is the industry standard method for doping Si and SiC devices. However, since activation of ion implants in GaN requires temperatures above the decomposition temperature, this method is not presently used commercially for GaN-based devices. Previous work by researchers at the Naval Research Laboratory, including some of the inventors of the present invention, has demonstrated that Mg ion implantation is possible through a symmetric multicycle rapid thermal annealing (SMRTA) and that Mg ion implantation through the SMRTA process can make p-type GaN. See J. D. Greenlee et al., “Comparison of AlN Encapsulants for Bulk GaN Multicycle Rapid Thermal Annealing,” ECSJ. Solid State Sci. Technol. 4, P 403-P 407 (2015); M. J. Tadjer, et al., “Selective p-type Doping of GaN:Si by Mg Ion Implantation and Multicycle Rapid Thermal Annealing,” ECS J. Solid State Sci. Technol. 5, P 124-P 127 (2016
The SMRTA process includes an annealing sequence consisting of periods of annealing at conventional annealing temperatures with spikes to metastable temperature regimes, combined with the application of nitrogen overpressure to stabilize the GaN crystal and increase the temperature at which it can be annealed as well as placement of a thermally stable cap on the upper surface of the GaN crystal to protect its surface from dissociating into Ga and N at the high metastable annealing temperatures. See U.S. Pat. No. 8,518,808 to Feigelson et al., “Defects Annealing and Impurities Activation in III-Nitride Compound,” U.S. Pat. No. 9,543,168 to Feigelson et al., “Defects Annealing and Impurities Activation in Semiconductors at Thermodynamically Non-Stable Conditions,” and U.S. Patent Application Publication No. 2019/0341261, “Implanted Dopant Activation for Wide Bandgap Semiconductor Electronics,” all of which share at least one inventor in common with the present disclosure.

SUMMARY

This summary is intended to introduce, in simplified form, a selection of concepts that are further described in the Detailed Description. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. Instead, it is merely presented as a brief overview of the subject matter described and claimed herein.
The present invention provides epitaxial GaN devices having highly doped ion-implanted n- or p-type contact regions under metal contacts, where the contact regions have activated dopant concentrations of from about 10¹⁸cm⁻³to about 10²²cm⁻³or more and where the doped regions are planar to the epitaxial GaN surface, and further provides methods for activating implanted dopants and repairing damage to dopant-implanted GaN so as to form the n-type or p-type regions in GaN.
To form n-type regions in GaN, a GaN substrate is masked and the exposed areas are implanted with n-type ions such as Si or Ge. The n-implanted GaN is annealed at high temperatures to activate the implanted n-type dopants, i.e., to produce electrical carriers in the material and to produce planar areas of activated n-type GaN within the GaN substrate. In some embodiments, the ion-implanted GaN can optionally be subjected to a first annealing at temperatures at which the GaN remains stable. In some embodiments, a thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing, while in other embodiments, the high-temperature annealing can be conducted under moderate N₂pressure to increase the stability of the GaN and reduce the evolution of the N₂from the GaN. In still other embodiments, the annealing can be conducted using transient annealing techniques such as laser annealing or rapid thermal annealing (RTA) to reduce exposure of GaN to a metastable regime.
To form p-type GaN regions, a GaN substrate is masked and the exposed areas are implanted with p-type ions such as Mg or Be. The p-implanted GaN is then first annealed at temperatures at which the GaN remains stable and then is annealed at high temperatures to activate the implanted p-type dopants, i.e., to produce electrical carriers in the material and to produce planar areas of activated p-type GaN within the GaN substrate. In some embodiments, a thermally stable cap can be applied to the GaN substrate to suppress nitrogen evolution from the GaN surface during the high-temperature annealing step, while in other embodiments, the high-temperature annealing can be conducted under moderate N₂pressure to increase the stability of the GaN and reduce the evolution of the N₂from the GaN. In still other embodiments, the annealing can be conducted using transient annealing techniques such as laser annealing or rapid thermal annealing (RTA) to reduce exposure of GaN to a metastable regime.
Ohmic contacts can then be formed on the n- or p-type areas of the GaN as appropriate to form vertical or lateral electrical devices such as JFETs, CAVETs, DMOS devices, MOSFET devices, HEMT devices, or PCSS devices.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plot illustrating aspects of vapor pressure of nitrogen over GaN under a range of temperatures.

FIGS. 2A-2H provide a flow diagram illustrating exemplary process steps in a method for forming ion-implanted GaN ohmic contacts and for fabricating electronic devices incorporating such ion-implanted GaN ohmic contacts in accordance with the present invention.

FIGS. 3A and 3B are photographic images illustrating damage caused by thermal annealing GaN above the thermal decomposition limit when a protective cap is not used cap (FIG. 3A) and reduced damage when a protective cap is used (FIG. 3B).

FIG. 4 is a plot illustrating spectral broadening observed of the Raman A₁(LO) peak indicating damage to a GaN sample incurred due to ion implantation and subsequent recovery after the sample is annealed at high temperatures.

FIGS. 5A-5C are plots illustrating electrical properties of unannealed ion-implanted GaN samples and ion-implanted GaN sample that have been annealed in accordance with the present invention.

DETAILED DESCRIPTION

The aspects and features of the present invention summarized above can be embodied in various forms. The following description shows, by way of illustration, combinations and configurations in which the aspects and features can be put into practice. It is understood that the described aspects, features, and/or embodiments are merely examples, and that one skilled in the art may utilize other aspects, features, and/or embodiments or make structural and functional modifications without departing from the scope of the present disclosure.
The present invention provides epitaxial GaN devices having highly doped ion-implanted n- or p-type contact regions under metal contacts, where the contact regions have activated dopant concentrations of about 10¹⁸cm⁻³to about 10²²cm⁻³and where the doped regions are planar to the epitaxial GaN surface, and further provides methods for activating implanted dopants and repairing damage to dopant-implanted GaN so as to form the n-type or p-type regions in GaN.
The activated ion-implanted n-type and p-type regions in GaN can be is achieved using components of the SMRTA process developed by inventors at NRL to create n-type or p-type GaN using ion implantation of Si or other-dopants into GaN. N-type dopants are significantly more abundant in the GaN materials system, exhibit lower electrical activation energy than p-type dopants and can be activated at lower temperatures. Thus, while the use of overpressure and application of a thermally stable cap such as is used in the SMRTA process greatly facilitates dopant activation, the temperature spikes to metastable temperature regimes used in the SMRTA process is not necessary to activate n-type dopants, nor is pressure always necessary to activate n-type dopants.
Implantation of n- or p-type dopants in accordance with the present invention can be performed on unintentionally doped GaN, semi-insulating GaN such as carbon doped GaN, or on AlGaN/GaN heterostructures situated on GaN, SiC, Si, sapphire, or composite engineered substrates.
Implantation of dopants into GaN damages the lattice structure of the GaN crystal and causes it to have low mobility and become highly resistive. To repair this lattice damage after implantation and activate the implanted dopant impurities, the GaN structure must be annealed, with the annealing taking place at high temperatures at which the ion-implanted GaN crystal is metastable at atmospheric pressure, i.e., above the equilibrium thermal decomposition limit of about 850° C., all the while maintaining the structural integrity of the GaN crystal. The annealing temperature required to activate the implanted dopants and repair the damage caused by the dopant implantation is typically in the 900-1600° C. range for n-type dopants and 1200-1600° C. range for p-type dopants.
However, as can be seen from the phase diagram shown in FIG. 1, GaN decomposes into its constituent elements Ga+N when heated to approximately 850° C. at atmospheric pressure. Mitigation of this decomposition is critical since nitrogen vacancies and other complexes formed by the decomposition cause leakage paths and degrade device performance.
Thus, in accordance with the present invention, the ion-implanted GaN must be protected during this metastable annealing to properly activate dopants and mitigate damage to the device structure. This protection of the GaN can be achieved by any one or a combination of the following approaches developed by the inventors as part of the SMRTA technique described in U.S. Pat. Nos. 8,518,808, 9,543,168, and U.S. Patent Application Publication No. 2019/0341261, supra.
An exemplary process flow for forming highly doped activated ion-implanted planar n-type regions in GaN in accordance with the present invention is illustrated by the block schematics shown in FIGS. 2A-2H.
As shown in FIG. 2A, the process begins with the deposition of a GaN film 202 on a SiC substrate 201, where the GaN film can be formed by any suitable technique known in the art such as MOCVD, HVPE, or MBE. The GaN can optionally be initially doped with carbon (with the GaN thus being denoted as S.I. GaN:C in the FIGURES) to make it semi-insulating.
In a second step in a process for fabricating an electronic device incorporating n-type GaN in accordance with the present invention, as illustrated in FIG. 2B, a sacrificial mask 203, e.g., a mask from standard photolithography photoresist or a hard mask, is deposited on an upper surface of the GaN to protect areas of the sample which are not to be implanted by Si. In a third step, illustrated in FIG. 2C, photomask 203 is selectively removed to expose regions 204 of the GaN to be implanted with n-type dopants, and the dopants are implanted into the exposed regions of the GaN to form doped regions 205, where implantation can be accomplished using any suitable implantation tool known in the art. Following implantation, in the next step, the mask is removed, as illustrated in FIG. 2D, to expose the GaN surface for further processing.
In one approach, aspects of which are illustrated in FIG. 2E, one or more thermally stable caps 206 can be applied to the upper surface of the n-implanted GaN to suppress nitrogen evolution from the GaN surface. The cap can comprise AlN, SiN, or other stable materials or composite structures of multiple materials are capable of protecting the crystal from decomposition.
In another approach, moderate Na pressure can be applied during annealing with the Na pressure increasing the stability of the GaN and reducing the evolution of Na from the GaN crystal. Application of an Na overpressure of up to about 100 bar in combination with use of a protective cap has been shown to stabilize the GaN at temperatures exceeding 1200° C. for short times.
In still another approach, transient annealing techniques such as laser annealing or rapid thermal annealing (RTA) can be used to reduce exposure of GaN to a metastable regime and kinetically limit decomposition or nitrogen evolution. See U.S. Pat. Nos. 8,518,808 and 9,543,168, supra; see also U.S. Patent Application Publication No. 2019/0341261, supra.
Irrespective of the approach used for this high-temperature annealing, it has been found that improved annealing of the n-implanted GaN can often be achieved by means of an optional first annealing step, where the n-implanted GaN is initially annealed for a predetermined period of time at a predetermined temperature when GaN is still stable before it is annealed at metastable temperatures. This initial stable annealing reduces the initial defect populations in the GaN and improves its tolerance of metastable annealing. See J. D. Greenlee et al., “Process optimization of multicycle rapid thermal annealing of Mg-implanted GaN,” 2014 IEEE Workshop on Wide Bandgap Power Devices and Applications, Knoxville, Tenn., 2014, pp. 59-62; see also J. D. Greenlee et al., “From MRTA to SMRTA: Improvements in Activating Implanted Dopants in GaN,” ECS Transactions 69(14):97-102. The specific time and temperature of this initial stable annealing can be tailored to the maximum temperature at which the GaN is stable at the process pressure and for durations necessary to improve resultant GaN mobility or activation, but typically is done below about 850° C. under atmospheric pressure for up to several hours but can be done at up to 1050° C. for a few seconds.
In the next step of a process for fabricating an electronic device incorporating ion-implanted GaN in accordance with the present invention, as illustrated in FIG. 2F the n-implanted GaN is then annealed at high temperatures to activate the implanted n-type dopants, i.e., to produce electrical carriers in the material and to produce activated planar n-type regions 207 within the GaN. Such annealing is typically conducted at temperatures of about 900 to about 1600° C. and at pressures ranging from 1 atm to about 100 bar. The annealing time in this step can vary from a few seconds to about an hour, with higher temperatures needing less time.
If a protective cap was applied to protect the GaN surface from damage during the metastable annealing, in the next step of a process for fabricating an electronic device incorporating regions of n-type GaN in accordance with the present invention, as illustrated in FIG. 2G, the protective cap is then removed to expose the annealed n-type areas in the GaN, where removal can be achieved using any suitable method known in the art, such as by means of plasma etching or by means of chemical etching using hydrofluoric acid (HF), potassium hydroxide (KOH), or the AZ400K developer available from AZ Industries.
Finally, as illustrated in FIG. 2H, ohmic contacts 208 a/208 b are deposited on an upper surface of the n-GaN areas of the GaN crystal, with the material and placement of the contacts being configured as appropriate for the specific device structure and design considerations.
The implantation and annealing process in accordance with the present invention results in a GaN substrate with highly n-doped GaN regions having an activated n-type dopant concentration of about 10¹⁸cm⁻³to about 10²²cm⁻³, where the doped regions are planar to the epitaxial GaN film.
Highly p-doped regions in GaN with activated p-type dopant ions having a concentration of about 10¹⁸cm⁻³to about 10²²cm⁻³can be similarly produced by doping the GaN with p-type dopants such as Mg or Be. However, activation of such p-type dopants typically requires annealing at higher temperatures or for longer durations to further reduce ion implantation damage.
Producing such highly p-doped regions in GaN typically requires the initial annealing step that is optional for n-doped GaN, before the doped GaN is subjected to high temperature annealing, i.e., an initial anneal at a temperature at which GaN is still stable at the process pressure and process time, e.g., below about 850° C. for several hours at atmospheric pressure or up to about 1050° C. for a few minutes at atmospheric pressure. Following this initial annealing step, the p-doped GaN is subjected to a metastable annealing regime similar to that described above with respect to n-doped GaN to activate the implanted p-type dopants, i.e., to produce electrical carriers in the material and to produce activated planar p-type regions within the GaN. As with the annealing of n-doped GaN, such annealing is typically conducted at temperatures of about 1200 to about 1600° C. and at pressures ranging from 1 atm to about 100 bar. The annealing time in this step can vary from a few seconds to about an hour, with higher temperatures needing less time. The protective measures described above, such as the deposition of a protective cap or the application of nitrogen overpressure, can be employed to prevent the GaN from decomposing into Ga and N₂during this high-temperature annealing.
The result of the annealing process in accordance with the present invention is a GaN substrate which has one or more regions having a high (10¹⁸cm⁻³to about 10²²cm⁻³) concentration of activated p-type dopants, where the highly doped regions are planar to the epitaxial GaN surface.
As noted above, one way to protect the GaN from decomposing into its constituent elements during the metastable annealing step is to deposit a thermally stable cap onto the GaN surface. The beneficial effects of using such a cap can be seen from the images shown in FIGS. 3A and 3B. FIG. 3A shows the surface of an ion-implanted GaN sample and shows multiple areas where the surface of the GaN is damaged. In contrast, the GaN sample shown in FIG. 3B was protected by a cap during high-temperature metastable annealing in accordance with the present invention, and as can be seen from FIG. 3B, is free from any visible defects.
As noted above, the annealing temperature required to activate the implanted dopants and repair the damage caused by the dopant implantation is typically in the 900-1600° C. range for n-type dopants and 1200-1600° C. range for p-type dopants. The benefits of this high-temperature annealing can be seen from the plots in FIG. 4. The crystal damage caused by n-dopant implantation can be observed using the Ai peak in a Raman spectra, as illustrated by the plots in FIG. 4A. The dotted line 401 in FIG. 4 shows the Raman peak for a raw, unimplanted sample. After n-dopant implantation, the Raman peak broadens (line 402), indicating Raman dispersion from implant-induced vacancies and damage. Annealing at both 1150° C. (403) and 1180° C. (404) narrows the width of the Raman peak to bring it closer to the peak shown by the unimplanted sample, indicating recovery of the damage to the GaN crystal introduced by ion implantation.
The results of annealing under different conditions are shown by the plots in FIGS. 5A-5C. The plot in FIG. 5A shows that the resistivity of an n-doped GaN sample drops as the annealing temperature increases until it reaches a minimum above an annealing temperature of around 1050° C. This minimum resistivity also corresponds to a minimum in contact resistivity in the 10⁻⁶Ω-cm scale, as seen by the plot in FIG. 5B, which illustrates that low contact resistance, beyond that exhibited by both unimplanted and unannealed samples, can be obtained after the implanted samples are annealed.
The impact of the annealing process on the unimplanted regions is equally important to device operation as these must remain capable of sustaining high electric field. To this end, any additional damage introduced by decomposition of the crystal is critical. The plot in FIG. 5C illustrates the current traveling through unimplanted regions of the GaN sample between implanted contacts as a function of voltage for devices annealed at different temperatures (plot lines 501-506) for 5 minutes at 30 atm pressure fabricated as described above with respect to FIGS. 1A-1H. The reference curve 507 for a device fabricated from unimplanted and unannealed GaN shows a breakdown around 3000 V. As can be seen from the plots in FIG. 5C, annealing under non-optimized conditions, either too cold to reduce the ion implantation damage (lines 501 and unannealed 508) or too hot, which generates additional defects ( lines 503, 504, 505, 506) decreases breakdown voltage and increases leakage current by at least a factor of 2, under more optimal conditions of annealing near 1050° C. (line 502) the breakdown voltage increases beyond that exhibited by the as-grown, unimplanted, unannealed material.
The highly doped planar ion-implanted n- and p-type GaN produced by the implantation and annealing process in accordance with the present invention can be incorporated into many different electronic devices known in the art, including vertical devices such as JFETs, CAVETs, DMOS devices, and MOSFET devices and lateral devices such as HEMTs and PCSS devices,
All of these devices can be synthesized with fewer processing steps by using the n-type ion implantation technique and annealing processes of the present invention. Most notably though, this process can be used to significantly simplify the contact process in both Ga-polar and N-polar High Electron Mobility Transistors (HEMTs) as described above by obviating the need for regrowth of contacts, thus eliminating a slow and costly step as well as removing an interface which causes leakage and breakdown pathways. Another significant aspect of the process of the present invention is that it can potentially be performed in a foundry with modifications to the fabrication sequence and/or process tools.
A method for activating implanted dopants and repairing damage caused by the dopant implantation has been described. Although particular embodiments, aspects, and features have been described and illustrated, one skilled in the art would readily appreciate that the invention described herein is not limited to only those embodiments, aspects, and features but also contemplates any and all modifications and alternative embodiments that are within the spirit and scope of the underlying invention described and claimed herein. The present application contemplates any and all modifications within the spirit and scope of the underlying invention described and claimed herein, and all such modifications and alternative embodiments are deemed to be within the scope and spirit of the present disclosure.

Claims

What is claimed is:

1. An epitaxial GaN substrate having at least one selectively formed activated n-type doped region therein;

wherein the activated n-type doped region is planar to a surface of the epitaxial GaN substrate and has a concentration of electrically activated ion-implanted n-type dopants of about 10¹⁸cm⁻³to about 10²²cm⁻³.

2. The epitaxial GaN substrate according to claim 1, wherein the n-type dopants are Si or Ge.

3. An epitaxial GaN substrate having at least one selectively formed activated p-type doped region therein;

wherein the activated p-type doped region is planar to a surface of the epitaxial GaN substrate and has a concentration of electrically activated ion-implanted p-type dopants of about 10¹⁸cm⁻³to about 10²²cm⁻³.

4. The epitaxial GaN substrate according to claim 3, wherein the p-type dopants are Mg or Be.