US20210399047A1 - Heterojunction thin film diode - Google Patents
Heterojunction thin film diode Download PDFInfo
- Publication number
- US20210399047A1 US20210399047A1 US16/907,065 US202016907065A US2021399047A1 US 20210399047 A1 US20210399047 A1 US 20210399047A1 US 202016907065 A US202016907065 A US 202016907065A US 2021399047 A1 US2021399047 A1 US 2021399047A1
- Authority
- US
- United States
- Prior art keywords
- diode
- type
- type layer
- layer
- array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title description 14
- 239000002019 doping agent Substances 0.000 claims abstract description 25
- 230000015654 memory Effects 0.000 claims abstract description 20
- 230000008859 change Effects 0.000 claims abstract description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 83
- 239000000758 substrate Substances 0.000 claims description 26
- 239000004065 semiconductor Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 22
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims description 13
- 239000003989 dielectric material Substances 0.000 claims description 13
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 12
- 229910052751 metal Inorganic materials 0.000 claims description 11
- 239000002184 metal Substances 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 10
- 229910052710 silicon Inorganic materials 0.000 claims description 10
- 239000010703 silicon Substances 0.000 claims description 10
- 238000000151 deposition Methods 0.000 claims description 7
- 229910052732 germanium Inorganic materials 0.000 claims description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- 229910052785 arsenic Inorganic materials 0.000 claims description 4
- 239000010949 copper Substances 0.000 claims description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 claims description 4
- 229910052698 phosphorus Inorganic materials 0.000 claims description 4
- 229910052716 thallium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- -1 thallium nitride Chemical class 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910052787 antimony Inorganic materials 0.000 claims description 2
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052802 copper Inorganic materials 0.000 claims description 2
- 229910052733 gallium Inorganic materials 0.000 claims description 2
- 229910052738 indium Inorganic materials 0.000 claims description 2
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 2
- 150000002739 metals Chemical class 0.000 claims description 2
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 239000011574 phosphorus Substances 0.000 claims description 2
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 18
- 238000003491 array Methods 0.000 abstract description 13
- 239000011787 zinc oxide Substances 0.000 description 8
- 239000002135 nanosheet Substances 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000000231 atomic layer deposition Methods 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000000873 masking effect Effects 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- 238000004549 pulsed laser deposition Methods 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- WUPHOULIZUERAE-UHFFFAOYSA-N 3-(oxolan-2-yl)propanoic acid Chemical compound OC(=O)CCC1CCCO1 WUPHOULIZUERAE-UHFFFAOYSA-N 0.000 description 2
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 2
- KXNLCSXBJCPWGL-UHFFFAOYSA-N [Ga].[As].[In] Chemical compound [Ga].[As].[In] KXNLCSXBJCPWGL-UHFFFAOYSA-N 0.000 description 2
- 229910052980 cadmium sulfide Inorganic materials 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 238000005234 chemical deposition Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 229910000927 Ge alloy Inorganic materials 0.000 description 1
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 1
- 229910000676 Si alloy Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910003697 SiBN Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- MDPILPRLPQYEEN-UHFFFAOYSA-N aluminium arsenide Chemical compound [As]#[Al] MDPILPRLPQYEEN-UHFFFAOYSA-N 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000013473 artificial intelligence Methods 0.000 description 1
- 238000013528 artificial neural network Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- AQCDIIAORKRFCD-UHFFFAOYSA-N cadmium selenide Chemical compound [Cd]=[Se] AQCDIIAORKRFCD-UHFFFAOYSA-N 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000000615 nonconductor Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
-
- H01L27/2409—
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/88—Tunnel-effect diodes
-
- H01L45/12—
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
- H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/72—Array wherein the access device being a diode
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
Definitions
- the present invention relates to diodes, methods of making diodes, and uses of diodes in circuitry. More specifically, the invention relates to low leakage current thin film diodes, making thin film diodes, and using thin film diodes in circuits like semiconductor memories.
- Diodes are electrical components that permit current flow when forward biased, e.g. a voltage is applied in a forward direction, but do not permit current flow when reversed biased, e.g. when the voltage is applied in a reverse direction.
- Thin film diodes are manufactured in semiconductor processes and are integrated ubiquitously in electronic circuitry.
- a diode will have a low resistance when forward biased and infinite resistance when reversed biased.
- the ratio of current through the diode while the diode is forward biased, e.g. in the “on” state, to the current through the diode while reversed biased, e.g. in the “off state”, should be very high. This ratio is called the “on/off ratio”.
- diodes are easily integrated in semiconductor layers, e.g. on semiconductor substrates, manufacture of diodes on dielectric surfaces is more difficult.
- diode structure with a high on/off ratio that can be made in both semiconductor circuitry and on dielectric surfaces that are encountered in back end of the line (BEOL).
- BEOL back end of the line
- PCMs phase change memories
- stack diodes and/or array elements on multiple levels on one or more dielectric substrates there is a need for a diode structure with a high on/off ratio that can be made in both semiconductor circuitry and on dielectric surfaces that are encountered in back end of the line (BEOL).
- PCMs phase change memories
- a diode is made of a p-type layer and an n-type layer connected in series between a bottom and top electrode.
- the p-type layer has a p-type thickness below 20 nanometers (nm), a p-type dopant, and a p-type dopant concentration.
- the n-type layer has an interface with the p-type layer.
- An optional, very thin inter-facial layer (ITL) can be disposed between the p-type and n-type layer. The interface forms a p-n junction and the diode.
- the n-type layer has an n-type thickness below 20 nm, an n-type dopant, and an n-type dopant concentration.
- the p-type and n-type layer can be deposited/stacked in either order so the bottom electrode can be connected to either the p-type layer or the n-type layer.
- the top electrode is connected to the other of the p-type layer and the n-type layer.
- the p-type dopant concentration and the n-type dopant concentration are high enough to keep a total resistance across the diode at less than 250 ⁇ when the diode is forward biased while still retaining the characteristics of a diode.
- the ratio of an ON current to an OFF current is greater than 2.5 ⁇ 10 4 .
- Example arrays include memory arrays using diodes and phase change memories (PCMs) connected in series as array elements.
- PCMs phase change memories
- the arrays can be stacked in layers and can be made/embodied in the back-end-of-the line (BEOL).
- BEOL back-end-of-the line
- FIG. 1 is a cross-section view of one embodiment of an interim layered structure, e.g. a nanosheet stack.
- FIG. 2 is a cross-section view of an alternative embodiment of an interim layered structure.
- FIG. 3 is a cross-section view of alternative embodiments of a heterojunction thin film diode.
- FIG. 4 is an isometric view of one embodiment of a phase change memory structure using heterojunction thin film diodes.
- FIG. 5 is a circuit schematic of one embodiment of a phase change memory structure using heterojunction thin film diodes.
- FIG. 6 is a flow chart of one method of making an embodiment of a heterojunction thin film diode.
- Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, expert and artificial intelligence systems, functional circuitry, neural networks, etc.
- portable communications devices e.g., cell and smart phones
- solid-state media storage devices e.g., solid-state media storage devices
- expert and artificial intelligence systems e.g., cell and smart phones
- functional circuitry e.g., neural networks, etc.
- Systems and hardware incorporating the semiconductor devices and structures are contemplated embodiments of the invention.
- height refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional or elevation views measured from a bottom surface to a top surface of the element, and/or measured with respect to a surface on which the element is located.
- element e.g., a layer, trench, hole, opening, etc.
- a “depth” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional or elevation views measured from a top surface to a bottom surface of the element. Terms such as “thick”, “thickness”, “thin” or derivatives thereof may be used in place of “height” where indicated.
- lateral refers to a side surface of an element (e.g., a layer, opening, etc.), such as a left or right-side surface in the drawings.
- width or “length” refers to a size of an element (e.g., a layer, trench, hole, opening, etc.) in the drawings measured from a side surface to an opposite surface of the element. Terms such as “thick”, “thickness”, “thin” or derivatives thereof may be used in place of “width” or “length” where indicated.
- terms such as “on”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element is present on a second element, wherein intervening elements may be present between the first element and the second element.
- the term “directly” used in connection with the terms “on”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop,” “disposed on,” or the terms “in contact” or “direct contact” means that a first element and a second element are connected without any intervening elements, such as, for example, intermediary conducting, insulating or semiconductor layers, present between the first element and the second element.
- FIG. 1 is a cross-section view of one embodiment of an interim layered structure 100 , e.g. a nanosheet stack 100 .
- the beginning layered structure 100 is a layer of nanosheets disposed on a substrate 105 .
- Nanosheet 120 is a layer of conductive material that is used as a first electrode or contact 120 of a diode 160 .
- Layers 130 and 140 are each made of p-type or n-type materials, disposed adjacent to one another (in either order) to form a p-n junction 160 that makes the diode 160 .
- Nanosheet layer 150 is another layer of conductive material that is used as a second electrode 150 or contact of the diode 160 .
- the substrate 105 is made of a semiconductor material(s) including: a single element (e.g., silicon or germanium); primarily a single element (e.g., a doped material), for example doped silicon; a compound semiconductor, for example, gallium arsenide (GaAs); or a semiconductor alloy, for example silicon-germanium (SiGe).
- a single element e.g., silicon or germanium
- primarily a single element e.g., a doped material
- doped silicon e.g., silicon
- GaAs gallium arsenide
- SiGe silicon-germanium
- Non-limiting examples of the substrate 105 materials include one or more semiconductor materials like silicon (Si), SiGe, Si:C (carbon doped silicon), germanium (Ge), carbon doped silicon germanium (SiGe:C), Si alloys, Ge alloys, III-V materials (e.g., GaAs, Indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), aluminum arsenide (AlAs), etc.), II-V materials (e.g., cadmium selenide (CdSe), cadmium sulfide (CdS), or any combination thereof), or other like semiconductors.
- III-V materials e.g., GaAs, Indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), aluminum arsenide (AlAs), etc.
- II-V materials e.g.,
- the substrate 105 includes both semiconductor materials and dielectric materials.
- a buried oxide layer, BOX (e.g., SiO2) is buried in the substrate 105 .
- diode 160 can be used in layers of semiconductor devices that include other active or passive elements like field effect transistors (FETs), capacitors, inductors, etc.
- FETs field effect transistors
- capacitors capacitors
- inductors etc.
- the substrate 105 is made of a dielectric or insulating material.
- Dielectric materials include, but are not limited to: dielectric oxides (e.g. silicon oxide, SiOx); dielectric nitrides (e.g., silicon nitride, SiN; siliconborocarbonitride, SiBCN; siliconcarbonitride, SiCN; and siliconboronitride SiBN); dielectric oxynitrides (e.g., silicon oxycarbonitride, SiOCN, and silicon oxynitride, SiON); silicon carbide (SiC); silicon oxycarbide (SiCO); or any combination thereof or the like.
- dielectric oxides e.g. silicon oxide, SiOx
- dielectric nitrides e.g., silicon nitride, SiN; siliconborocarbonitride, SiBCN; siliconcarbonitride, SiCN; and siliconboronitride SiBN
- dielectric oxynitrides e.g., silicon oxy
- Dielectric materials are often encountered in the back-end-of-the-line (BEOL) where the dielectric materials act as electrical insulators. Since the BEOL provides a plurality of interconnection layers, the layers of the BEOL often have conductive interconnections running through the dielectric/insulating layers.
- BEOL back-end-of-the-line
- the layers ( 120 , 130 , 140 , and 150 ) of the diode 160 can be formed by deposition. Therefore, the heterojunction thin film diode 160 can be formed using one or more of BEOL dielectric layers as the substrate 105 .
- multiple diodes 160 can be made in a stacked formation(s) of multiple layers of diodes 160 (e.g., a three-dimensional, 3D, stacking) on one or more dielectric layers/substrates 105 in the BEOL. Accordingly, the diode 160 structure and methods of making the diode(s) 160 enable diode circuitry, e.g. used with phase change memories (PCMs), to be formed in the BEOL and that are compatible with BEOL manufacturing processes.
- PCMs phase change memories
- Layers 130 and 140 are made of either a p-type or an n-type material. Layers 130 and 140 have opposite types. For example, layer 130 is a p-type material and layer 140 is an n-type material. Alternatively, layer 140 is the p-type material and layer 130 is the n-type material. Since layers 130 and 140 are of opposite types, a p-n junction 160 forming the diode 160 is created at the interface 160 of the layers 130 and 140 . While the order of the layers 130 and 140 does not matter in creating the diode 160 (only that the layers, 130 and 140 , are in substantial contact and opposite in type), the direction of current flow or blockage will change, e.g.
- the diode 160 has a heterojunction because layers 130 and 140 forming the p-n junction are made from two different materials.
- the first electrode or contact 120 and the second electrode or contact of the diode 160 are each made of a layer 120 ( 150 ) of conductive material, e.g. metal.
- conductive material e.g. metal.
- metals include: copper, Cu; tungsten, W; aluminum, Al; nickel, Ni; thallium nitride, Tl3N; and titanium nitride, TiN.
- the first 120 and second 150 electrodes are made of Al.
- the first electrode 120 may be electrically insulated from the substrate 105 .
- the first electrode 120 and/or second electrode 150 can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Radio Frequency Chemical Vapor Deposition (RFCVD,) Physical Vapor Deposition (PVD), Pulsed Laser Deposition (PLD), Liquid Source Misted Chemical Deposition (LSMCD), and/or sputtering.
- ALD atomic layer deposition
- CVD chemical vapor deposition
- PECVD Plasma Enhanced Chemical Vapor Deposition
- RFCVD Radio Frequency Chemical Vapor Deposition
- PVD Physical Vapor Deposition
- PLD Pulsed Laser Deposition
- LMCD Liquid Source Misted Chemical Deposition
- sputtering atomic layer deposition
- ALD atomic layer deposition
- CVD chemical vapor deposition
- PECVD Plasma Enhanced Chemical Vapor Deposition
- RFCVD Radio Frequency Chemical Vapor Deposition
- PVD Physical Vap
- the thickness 125 of the first electrode 120 and the thickness 155 of the second electrode 150 is between 50 nanometers (nm) and 100 nm.
- the p-type layer 130 ( 140 ) and the n-type layer 140 ( 130 ) are made of semiconductor materials.
- semiconductor materials include silicon (Si), germanium (Ge), and silicon germanium (SiGe).
- the p-type layer 130 ( 140 ) and the n-type layer 140 ( 130 ) can be deposited by ALD, CVD, PECVD, RFCVD, PVD, PLD, and Liquid Source Misted Chemical Deposition (LSMCD).
- the thicknesses ( 135 , 145 ) of these layers ( 130 , 140 ) is between 5 nm and 30 nm, respectively. In some embodiments, the thicknesses ( 135 , 145 ) are less than 20 nm.
- the p-type layer 130 ( 140 ) and the n-type layer 140 ( 130 ) are doped.
- the p-type layers 130 ( 140 ) is doped with dopants selected from a non-limited group of boron (B), gallium (Ga), indium (In), and thallium (Ti).
- the n-type layer 140 ( 130 ) is doped with dopants selected from a non-limited group of phosphorus (P), arsenic (As), and antimony (Sb).
- the n-type layer 140 ( 130 ) is a doped metallic layer 140 ( 130 ).
- the n-type layer 140 ( 130 ) can be made of a metal like Al doped with zinc oxide (ZnO).
- the doping levels of the p-type 130 ( 140 ) and n-type 140 ( 130 ) layers There is a trade-off consideration with the doping levels of the p-type 130 ( 140 ) and n-type 140 ( 130 ) layers.
- the p-type 130 ( 140 ) and n-type 140 ( 130 ) layers have to be highly conductive.
- the interface 160 will behave more like an electrical contact than a diode and/or the leakage current when reversed biased will be too high.
- the doping level/concentration for the p-type layer 130 ( 140 ) is between 1 ⁇ 10 18 cm ⁇ 3 and 1 ⁇ 10 21 cm ⁇ 3 and the doping level/concentration for the n-type layer 140 ( 130 ) is between 1 ⁇ 10 18 cm ⁇ 3 and 4%.
- the p-type layer 130 ( 140 ) is Ge or SiGe doped with P or As at a concentration between 1 ⁇ 10 19 cm ⁇ 3 and 1 ⁇ 10 21 cm ⁇ 3 and the n-type layer 140 ( 130 ) is Ge or SiGe doped with P or As at a concentration between 1 ⁇ 10 19 cm ⁇ 3 and 1 ⁇ 10 21 cm ⁇ 3 .
- the n-type layer 140 ( 130 ) is a thin metallic film between 5 and 20 nm thick 145 made of Al doped with ZnO at a concentration between 1% and 4%.
- FIG. 2 is a cross-section view of an alternative embodiment of an interim layered structure 100 .
- a very thin inter-facial layer (ITL) 250 is disposed between the p-type 130 ( 140 ) and n-type 140 ( 130 ) layers.
- the ITL 250 is has a thickness 255 between 1 nm and 5 nm. In some embodiments, the ITL 250 has a thickness 255 of about 3 nm.
- the ITL 250 creates a tunneling barrier between the p-type 130 ( 140 ) and n-type 140 ( 130 ) layers. Because of the ITL 250 thinness 255 , the barrier has little effect when the diode is forward biased. However, when the diode is reversed biased, the barrier increases greatly. Therefore, in the reversed biased configuration the ITL 250 significantly reduces the leakage current and improves the on/off current ratio of the diode.
- the ITL 250 is made of a dielectric material that is deposited by one or more of the deposition techniques described above. In some embodiments, the ITL 250 is made of silicon dioxide (SiO 2 ) or aluminum oxide (Al 2 O 3 ).
- FIG. 3 is a cross-section view of alternative embodiments of a heterojunction thin film diode 300 .
- the embodiment is shown with an ITL 250 but an embodiment without an ITL 250 is also contemplated without loss of generality.
- the diode 160 with the ITL 250 is shown as diode 360 .
- the substrate 105 can be made of semiconductor material or dielectric material without loss of generality.
- the p-type 130 ( 140 ) and n-type 140 ( 130 ) layers can be in reversed positions.
- Material 325 is removed on either side (and front and back, not shown) of the structure 300 by known masking and etching methods. As shown in FIG. 4 , these masking/etching steps can create a pattern of diodes 160 / 360 in one or more arrays with spacing between the diodes 160 / 360 . The etching can occur in multiple steps using different chemistries as different layers ( 120 , 130 , 250 , 140 , and 150 ) are etched away.
- bottom 120 and/or top 150 electrode layers can be employed to make the bottom 120 and/or top 150 electrode layers longer/wider 310 than the length/width of the p-type 130 ( 140 ) and n-type 140 ( 130 ) layers and ITL 250 .
- the bottom 120 and/or top 150 electrode layers can be extended 310 to create 3D structures like those described in the memory structures below.
- the p-type 130 layer is made of Ge at a doping concentration between 1 ⁇ 10 18 cm ⁇ 3 and 1 ⁇ 10 21 cm ⁇ 3 .
- the n-type layer 140 is made of Al doped with ZnO at a doping concentration between 0.1% and 8%.
- the top 150 and bottom 120 electrodes are made of a metal, like Al.
- the resistance of the layers and the contact interfaces between the layers and metal electrodes ( 120 , 150 ) are each determined to calculate the total series resistance of the device 300 .
- the contact resistance 320 of the interface 320 between the metal (Al) bottom electrode 120 and the Ge p-type layer 130 can be as low as 1 ⁇ 10 ⁇ 10 ⁇ -cm 2 with the levels of doping in the example. Accordingly, for a diode 160 with a width 330 of 100 nm and a depth (not shown) of 100 nm (i.e. a diode 160 of 100 nm ⁇ 100 nm size/surface area) the contact resistance 320 will be about 1 ⁇ . For instance:
- a 100 nm distance (here both width 330 and depth, not shown) is 10 ⁇ 5 cm.
- the resistance of p-type (Ge) layer 130 is:
- the resistance of the n-type (Al:ZnO) layer 140 is:
- nm is the thickness 145 of the n-type layer 140 and 0.005 ⁇ -cm is the resistivity of Al doped with ZnO at the given concentration.
- the contact resistance at the interface 340 between the n-type (Al:ZnO) layer 140 and the metal (Al) top electrode 150 can be as low as 1 ⁇ 10 ⁇ 8 ⁇ -cm 2 with the levels of doping in the example, yielding a contact resistance at this interface 340 of
- the total series resistance R T of the device 160 is:
- the doping levels/concentration of the p-type layer 130 and the n-type layer 140 are made high to keep the resistance of both of the p-type 130 and n-type 140 layers low, but these doping concentrations are low enough to still maintain the p-n junction interface 160 / 360 as a diode.
- the contact resistance 320 to the p-Ge layer 130 is very low but the contact resistance to the Al:ZnO 140 is higher.
- V off V on /2. i.
- the On/Off current ratio is 2.5 ⁇ 10 4 .
- One example design criterion for an N ⁇ N array of diodes is that:
- N is the dimension of one side of a square array of diodes.
- diodes 160 / 360 having an On/Off current ratio, I on /I off , of 2.5 ⁇ 10 4 or better can be used in diode arrays where N ⁇ N is up to 1000 ⁇ 1000 and still satisfy this design requirement.
- FIG. 4 is an isometric view of an array 400 of heterojunction thin film diodes ( 160 , 360 ) used with an array of phase change memories (PCM), each PCM typically 425 .
- PCM phase change memories
- PCMs 425 are known circuit elements that manifest two or more states, e.g. resistance values, that can be set and reset and read to store/retrieve a memory state.
- the array 400 is disposed on a substrate 105 .
- the substrate 105 can be made of a dielectric, rather than a semiconductor material, as described above.
- the array is made of one or more array elements, typical 410 .
- An array element can be a diode ( 160 , 360 ) alone.
- an array element is a diode ( 160 , 360 ) in series with a PCM, 425 between a bottom array 420 B and a top array 450 electrode.
- each array layer 475 has one or more bottom array elements ( 410 B, typically 410 ).
- the bottom array elements ( 410 B, 410 ) have a first bottom array electrode ( 420 B, typically 420 ), a bottom diode ( 160 , 360 , 460 B, typically 460 ), a bottom PCM ( 425 B, typically 425 ), and a first top array electrode ( 450 ).
- a second or top array layer ( 475 T, 475 ) is stacked upon the first or bottom array layer ( 475 B, 475 ).
- the second or top array layer 475 T has one or more top array elements ( 410 T, typically 410 ).
- Each of the top array elements 410 T has a second bottom array electrode ( 420 T, typically 420 ), a top diode ( 160 , 360 , 460 T, typically 460 ), a top PCM ( 425 T, typically 425 ), and a second top array electrode 450 .
- the first top array electrode 450 and the second top array electrode 450 are the same element, namely a common top array electrode 450 .
- one or more of the bottom array elements 410 B and one or more of the top array elements 410 T are connected in common by the top electrode 450 .
- the top array layer 475 T is a “flipped” version of the bottom array layer 475 B.
- the diodes ( 160 , 360 , 460 ) in one or more of the bottom 410 B and top 410 T array elements 410 T have the same polarity or direction.
- each of the one or more bottom 410 B and top 410 T array elements 410 T connected in common has a diode 460 with the same layer position for the p-type 130 ( 140 ) and n-type 140 ( 130 ) layers.
- one or more bottom 410 B array elements has the bottom diode 460 B with the p-type 140 ( 130 ) and n-type 130 ( 140 ) layers reverse from the top diode 460 T in an associated or connected top 410 T array element 410 T.
- the bottom 410 B and top 410 T array elements would be connected in series.
- top electrode 450 of the bottom array element 410 B is connected to the second bottom electrode ( 120 , 420 T).
- connections/configuration of the array 400 can be adjusted by both how the array elements 410 are interconnected and/or how they are constructed.
- the first 120 and second 150 electrodes are shown elongated 310 .
- the elongated 310 first 120 and second 150 electrode can become or be connected to the respective array electrodes ( 420 , 450 ) that connect two or more array elements 410 .
- Alternate embodiments are envisioned where one or more of the first array 420 and second array 450 electrodes connect to just one, two, or many array elements 410 .
- FIG. 5 is a circuit schematic 500 of a phase change memory structure using heterojunction thin film diodes ( 160 , 360 , in this schematic typically 560 ).
- the diodes ( 160 , 360 , 560 ) are made the same way, e.g. the diodes ( 160 , 360 , 560 ) and have the same polarity because the p-type layer 130 ( 140 ) and the n-type layer 140 ( 130 ) are layered in the same sequence for each of the diodes ( 160 , 360 , 560 ).
- top diode ( 560 T, typically 560 ) and bottom diode ( 560 B, typically 560 ) are connected though a respective top PCM ( 525 T, typically 525 ) and bottom PCM ( 525 B, typically 525 ) so that the top electrodes ( 150 , 550 ) of the diodes are connected in common 550 through their respective PCMs 525 .
- a current flows through the respective diode 560 and its associated PCB 525 .
- a top voltage 575 T can be read across the top PCM 525 T and/or a bottom voltage 575 B (typically 575 ) can be read across the bottom PCM 525 B.
- a lower voltage 575 reading indicates the respective PCM 525 is in a lower resistive or first memory state.
- a higher voltage 575 reading indicates the respective PCM 525 is in a higher resistive or second memory state. If the polarity of the applied voltage reverse biases either the top 525 T and/or bottom 525 B diode 525 , no or very little current will flow through the “Off” diode 560 and its associated PCM 525 because the diodes ( 160 , 360 , 560 ) have such a low leakage current and such a high On/Off current ratio. In such “Off” condition no or little voltage 575 will be read.
- FIG. 6 is a flow chart of the method of making 600 a heterojunction thin film diode ( 160 , 360 ).
- the method 600 begins with step 610 which forms a layered structure 100 , either on a semiconductor or dielectric substrate 105 .
- the layered structure 100 formed on a dielectric substrate 105 can be formed at the BEOL.
- the layered structure includes the substrate 105 , the first/bottom electrode 120 , the p-type layer 130 ( 140 ), the n-type layer 140 ( 130 ), and the second/top electrode 150 .
- the p-type 140 ( 130 ) and n-type 130 ( 140 ) layers can be formed in reverse order.
- an ITL layer 250 is formed between the p-type layer 130 ( 140 ) and the n-type layer 140 ( 130 ). Further details including doping levels are included in the description of FIGS. 1 and 2 .
- an etching is formed to define one or more diode ( 160 , 360 ) structures 300 .
- the first/bottom 120 and/or second/top 150 electrodes can be formed under a single device ( 160 , 360 ) and/or can be elongated 310 by known lithographic techniques to connect to two or more devices ( 160 , 360 ), e.g. array elements 140 .
- array layers 475 can be stacked one upon the other 475 to form multiple different array configurations.
- PCMs 425 can be integrated into the arrays 400 to create memory structures, e.g. in the BEOL, either at one level 475 or at two or more multiple levels ( 475 B, 475 T, 475 ).
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
- The present invention relates to diodes, methods of making diodes, and uses of diodes in circuitry. More specifically, the invention relates to low leakage current thin film diodes, making thin film diodes, and using thin film diodes in circuits like semiconductor memories.
- Diodes are electrical components that permit current flow when forward biased, e.g. a voltage is applied in a forward direction, but do not permit current flow when reversed biased, e.g. when the voltage is applied in a reverse direction. Thin film diodes are manufactured in semiconductor processes and are integrated ubiquitously in electronic circuitry.
- Ideally, a diode will have a low resistance when forward biased and infinite resistance when reversed biased. In other words, the ratio of current through the diode while the diode is forward biased, e.g. in the “on” state, to the current through the diode while reversed biased, e.g. in the “off state”, should be very high. This ratio is called the “on/off ratio”.
- However, physical diodes have leakage current—the current flow through the diode when diode is reversed biased. As circuitry becomes denser, e.g. there are more diodes per surface area on a substrate, the aggregate leakage current of large numbers of diodes in the circuitry can cause excess heating of the circuitry and higher power losses.
- In addition, while diodes are easily integrated in semiconductor layers, e.g. on semiconductor substrates, manufacture of diodes on dielectric surfaces is more difficult.
- There is a need for a diode structure with a high on/off ratio that can be made in both semiconductor circuitry and on dielectric surfaces that are encountered in back end of the line (BEOL). There is also a need to manufacture structures of diodes, e.g. used with phase change memories (PCMs), in the BEOL. Further, there is a need to stack diodes and/or array elements on multiple levels on one or more dielectric substrates.
- According to some embodiments, a diode is made of a p-type layer and an n-type layer connected in series between a bottom and top electrode. The p-type layer has a p-type thickness below 20 nanometers (nm), a p-type dopant, and a p-type dopant concentration. The n-type layer has an interface with the p-type layer. An optional, very thin inter-facial layer (ITL) can be disposed between the p-type and n-type layer. The interface forms a p-n junction and the diode. The n-type layer has an n-type thickness below 20 nm, an n-type dopant, and an n-type dopant concentration. The p-type and n-type layer can be deposited/stacked in either order so the bottom electrode can be connected to either the p-type layer or the n-type layer. The top electrode is connected to the other of the p-type layer and the n-type layer.
- The p-type dopant concentration and the n-type dopant concentration are high enough to keep a total resistance across the diode at less than 250Ω when the diode is forward biased while still retaining the characteristics of a diode. In some embodiments, the ratio of an ON current to an OFF current is greater than 2.5×104.
- Arrays of diodes and methods of making diodes are disclosed. Example arrays include memory arrays using diodes and phase change memories (PCMs) connected in series as array elements. The arrays can be stacked in layers and can be made/embodied in the back-end-of-the line (BEOL).
- Various embodiments of the present invention will be described below in more detail, with reference to the accompanying drawings, now briefly described. The Figures show various apparatus, structures, and related method steps of the present invention.
-
FIG. 1 is a cross-section view of one embodiment of an interim layered structure, e.g. a nanosheet stack. -
FIG. 2 is a cross-section view of an alternative embodiment of an interim layered structure. -
FIG. 3 is a cross-section view of alternative embodiments of a heterojunction thin film diode. -
FIG. 4 is an isometric view of one embodiment of a phase change memory structure using heterojunction thin film diodes. -
FIG. 5 is a circuit schematic of one embodiment of a phase change memory structure using heterojunction thin film diodes. -
FIG. 6 is a flow chart of one method of making an embodiment of a heterojunction thin film diode. - It is to be understood that embodiments of the present invention are not limited to the illustrative methods, apparatus, structures, systems and devices disclosed herein but instead are more broadly applicable to other alternative and broader methods, apparatus, structures, systems and devices that become evident to those skilled in the art given this disclosure.
- In addition, it is to be understood that the various layers, structures, and/or regions shown in the accompanying drawings are not drawn to scale, and that one or more layers, structures, and/or regions of a type commonly used may not be explicitly shown in a given drawing. This does not imply that the layers, structures, and/or regions not explicitly shown are omitted from the actual devices.
- In addition, certain elements may be left out of a view for the sake of clarity and/or simplicity when explanations are not necessarily focused on such omitted elements. Moreover, the same or similar reference numbers used throughout the drawings are used to denote the same or similar features, elements, or structures, and thus, a detailed explanation of the same or similar features, elements, or structures may not be repeated for each of the drawings.
- The semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Suitable hardware and systems for implementing embodiments of the invention may include, but are not limited to, personal computers, communication networks, electronic commerce systems, portable communications devices (e.g., cell and smart phones), solid-state media storage devices, expert and artificial intelligence systems, functional circuitry, neural networks, etc. Systems and hardware incorporating the semiconductor devices and structures are contemplated embodiments of the invention.
- As used herein, “height” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional or elevation views measured from a bottom surface to a top surface of the element, and/or measured with respect to a surface on which the element is located.
- Conversely, a “depth” refers to a vertical size of an element (e.g., a layer, trench, hole, opening, etc.) in the cross-sectional or elevation views measured from a top surface to a bottom surface of the element. Terms such as “thick”, “thickness”, “thin” or derivatives thereof may be used in place of “height” where indicated.
- As used herein, “lateral,” “lateral side,” “side,” and “lateral surface” refer to a side surface of an element (e.g., a layer, opening, etc.), such as a left or right-side surface in the drawings.
- As used herein, “width” or “length” refers to a size of an element (e.g., a layer, trench, hole, opening, etc.) in the drawings measured from a side surface to an opposite surface of the element. Terms such as “thick”, “thickness”, “thin” or derivatives thereof may be used in place of “width” or “length” where indicated.
- As used herein, terms such as “upper”, “lower”, “right”, “left”, “vertical”, “horizontal”, “top”, “bottom”, and derivatives thereof shall relate to the disclosed structures and methods, as oriented in the drawing figures. For example, as used herein, “vertical” refers to a direction perpendicular to the top surface of the substrate in the elevation views, and “horizontal” refers to a direction parallel to the top surface of the substrate in the elevation views.
- As used herein, unless otherwise specified, terms such as “on”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop” mean that a first element is present on a second element, wherein intervening elements may be present between the first element and the second element. As used herein, unless otherwise specified, the term “directly” used in connection with the terms “on”, “overlying”, “atop”, “on top”, “positioned on” or “positioned atop,” “disposed on,” or the terms “in contact” or “direct contact” means that a first element and a second element are connected without any intervening elements, such as, for example, intermediary conducting, insulating or semiconductor layers, present between the first element and the second element.
- It is understood that these terms might be affected by the orientation of the device described. For example, while the meaning of these descriptions might change if the device was rotated upside down, the descriptions remain valid because they describe relative relationships between features of the invention.
- Refer now to the Figures.
-
FIG. 1 is a cross-section view of one embodiment of an interim layeredstructure 100, e.g. ananosheet stack 100. - The beginning
layered structure 100 is a layer of nanosheets disposed on asubstrate 105.Nanosheet 120 is a layer of conductive material that is used as a first electrode orcontact 120 of adiode 160.Layers p-n junction 160 that makes thediode 160.Nanosheet layer 150 is another layer of conductive material that is used as asecond electrode 150 or contact of thediode 160. - In one embodiment, the
substrate 105 is made of a semiconductor material(s) including: a single element (e.g., silicon or germanium); primarily a single element (e.g., a doped material), for example doped silicon; a compound semiconductor, for example, gallium arsenide (GaAs); or a semiconductor alloy, for example silicon-germanium (SiGe). Non-limiting examples of thesubstrate 105 materials include one or more semiconductor materials like silicon (Si), SiGe, Si:C (carbon doped silicon), germanium (Ge), carbon doped silicon germanium (SiGe:C), Si alloys, Ge alloys, III-V materials (e.g., GaAs, Indium gallium arsenide (InGaAs), indium arsenide (InAs), indium phosphide (InP), aluminum arsenide (AlAs), etc.), II-V materials (e.g., cadmium selenide (CdSe), cadmium sulfide (CdS), or any combination thereof), or other like semiconductors. In addition, multiple layers of the semiconductor materials can make up thesubstrate 105. In some embodiments, thesubstrate 105 includes both semiconductor materials and dielectric materials. In some silicon on insulator (SOI) implementations, a buried oxide layer, BOX, (e.g., SiO2) is buried in thesubstrate 105. - These embodiments of the
diode 160 can be used in layers of semiconductor devices that include other active or passive elements like field effect transistors (FETs), capacitors, inductors, etc. - In other embodiments, the
substrate 105 is made of a dielectric or insulating material. Dielectric materials include, but are not limited to: dielectric oxides (e.g. silicon oxide, SiOx); dielectric nitrides (e.g., silicon nitride, SiN; siliconborocarbonitride, SiBCN; siliconcarbonitride, SiCN; and siliconboronitride SiBN); dielectric oxynitrides (e.g., silicon oxycarbonitride, SiOCN, and silicon oxynitride, SiON); silicon carbide (SiC); silicon oxycarbide (SiCO); or any combination thereof or the like. - Dielectric materials are often encountered in the back-end-of-the-line (BEOL) where the dielectric materials act as electrical insulators. Since the BEOL provides a plurality of interconnection layers, the layers of the BEOL often have conductive interconnections running through the dielectric/insulating layers.
- In embodiments of the invention, the layers (120, 130, 140, and 150) of the
diode 160 can be formed by deposition. Therefore, the heterojunctionthin film diode 160 can be formed using one or more of BEOL dielectric layers as thesubstrate 105. In addition,multiple diodes 160 can be made in a stacked formation(s) of multiple layers of diodes 160 (e.g., a three-dimensional, 3D, stacking) on one or more dielectric layers/substrates 105 in the BEOL. Accordingly, thediode 160 structure and methods of making the diode(s) 160 enable diode circuitry, e.g. used with phase change memories (PCMs), to be formed in the BEOL and that are compatible with BEOL manufacturing processes. -
Layers Layers layer 130 is a p-type material andlayer 140 is an n-type material. Alternatively,layer 140 is the p-type material andlayer 130 is the n-type material. Sincelayers p-n junction 160 forming thediode 160 is created at theinterface 160 of thelayers layers first electrode 120 to thesecond electrode 150 or visa versa, depending on the ordering of the type of materials inlayers layered structure 100. Thediode 160 has a heterojunction becauselayers - The first electrode or contact 120 and the second electrode or contact of the
diode 160 are each made of a layer 120 (150) of conductive material, e.g. metal. Non-limiting examples of metals include: copper, Cu; tungsten, W; aluminum, Al; nickel, Ni; thallium nitride, Tl3N; and titanium nitride, TiN. In some embodiments, the first 120 and second 150 electrodes are made of Al. In some embodiments, thefirst electrode 120 may be electrically insulated from thesubstrate 105. - The
first electrode 120 and/orsecond electrode 150 can be deposited by atomic layer deposition (ALD), chemical vapor deposition (CVD), Plasma Enhanced Chemical Vapor Deposition (PECVD), Radio Frequency Chemical Vapor Deposition (RFCVD,) Physical Vapor Deposition (PVD), Pulsed Laser Deposition (PLD), Liquid Source Misted Chemical Deposition (LSMCD), and/or sputtering. - In some embodiments, the
thickness 125 of thefirst electrode 120 and thethickness 155 of thesecond electrode 150 is between 50 nanometers (nm) and 100 nm. - In some embodiments, the p-type layer 130 (140) and the n-type layer 140 (130) are made of semiconductor materials. Non-limiting examples of these semiconductor materials include silicon (Si), germanium (Ge), and silicon germanium (SiGe).
- The p-type layer 130 (140) and the n-type layer 140 (130) can be deposited by ALD, CVD, PECVD, RFCVD, PVD, PLD, and Liquid Source Misted Chemical Deposition (LSMCD). The thicknesses (135, 145) of these layers (130, 140) is between 5 nm and 30 nm, respectively. In some embodiments, the thicknesses (135, 145) are less than 20 nm.
- The p-type layer 130 (140) and the n-type layer 140 (130) are doped. As an example, the p-type layers 130 (140) is doped with dopants selected from a non-limited group of boron (B), gallium (Ga), indium (In), and thallium (Ti). The n-type layer 140 (130) is doped with dopants selected from a non-limited group of phosphorus (P), arsenic (As), and antimony (Sb).
- In alternative embodiments, the n-type layer 140 (130) is a doped metallic layer 140 (130). As a non-limiting example, the n-type layer 140 (130) can be made of a metal like Al doped with zinc oxide (ZnO).
- There is a trade-off consideration with the doping levels of the p-type 130 (140) and n-type 140 (130) layers. To achieve a low resistance, e.g. high “on current” when the
diode 160 is forward biased, the p-type 130 (140) and n-type 140 (130) layers have to be highly conductive. However, if one or both layers is too conductive, e.g. too highly doped, theinterface 160 will behave more like an electrical contact than a diode and/or the leakage current when reversed biased will be too high. - In some embodiments, the doping level/concentration for the p-type layer 130 (140) is between 1×1018 cm−3 and 1×1021 cm−3 and the doping level/concentration for the n-type layer 140 (130) is between 1×1018 cm−3 and 4%.
- In some embodiments, the p-type layer 130 (140) is Ge or SiGe doped with P or As at a concentration between 1×1019 cm−3 and 1×1021 cm−3 and the n-type layer 140 (130) is Ge or SiGe doped with P or As at a concentration between 1×1019 cm−3 and 1×1021 cm−3. In alternative embodiments, the n-type layer 140 (130) is a thin metallic film between 5 and 20 nm thick 145 made of Al doped with ZnO at a concentration between 1% and 4%.
-
FIG. 2 is a cross-section view of an alternative embodiment of an interimlayered structure 100. In this embodiment, a very thin inter-facial layer (ITL) 250 is disposed between the p-type 130 (140) and n-type 140 (130) layers. In some embodiments, theITL 250 is has athickness 255 between 1 nm and 5 nm. In some embodiments, theITL 250 has athickness 255 of about 3 nm. - While the p-type 130 (140) and n-type 140 (130) layers are substantially in contact, the
ITL 250 creates a tunneling barrier between the p-type 130 (140) and n-type 140 (130) layers. Because of theITL 250thinness 255, the barrier has little effect when the diode is forward biased. However, when the diode is reversed biased, the barrier increases greatly. Therefore, in the reversed biased configuration theITL 250 significantly reduces the leakage current and improves the on/off current ratio of the diode. - In some embodiments, the
ITL 250 is made of a dielectric material that is deposited by one or more of the deposition techniques described above. In some embodiments, theITL 250 is made of silicon dioxide (SiO2) or aluminum oxide (Al2O3). -
FIG. 3 is a cross-section view of alternative embodiments of a heterojunctionthin film diode 300. The embodiment is shown with anITL 250 but an embodiment without anITL 250 is also contemplated without loss of generality. Thediode 160 with theITL 250 is shown asdiode 360. As discussed above, thesubstrate 105 can be made of semiconductor material or dielectric material without loss of generality. In addition, as discussed above, the p-type 130 (140) and n-type 140 (130) layers can be in reversed positions. -
Material 325 is removed on either side (and front and back, not shown) of thestructure 300 by known masking and etching methods. As shown inFIG. 4 , these masking/etching steps can create a pattern ofdiodes 160/360 in one or more arrays with spacing between thediodes 160/360. The etching can occur in multiple steps using different chemistries as different layers (120, 130, 250, 140, and 150) are etched away. - In alternative embodiments, techniques can be employed to make the bottom 120 and/or top 150 electrode layers longer/wider 310 than the length/width of the p-type 130 (140) and n-type 140 (130) layers and
ITL 250. Using known masking and/or deposition techniques, the bottom 120 and/or top 150 electrode layers can be extended 310 to create 3D structures like those described in the memory structures below. - A non-limiting example is now presented. In this example embodiment, the p-
type 130 layer is made of Ge at a doping concentration between 1×1018 cm−3 and 1×1021 cm−3. The n-type layer 140 is made of Al doped with ZnO at a doping concentration between 0.1% and 8%. There is noILT layer 250. The top 150 and bottom 120 electrodes are made of a metal, like Al. - The resistance of the layers and the contact interfaces between the layers and metal electrodes (120, 150) are each determined to calculate the total series resistance of the
device 300. - The
contact resistance 320 of theinterface 320 between the metal (Al)bottom electrode 120 and the Ge p-type layer 130 (e.g. measured by the I-V curve slope at zero volts) can be as low as 1×10−10 Ω-cm2 with the levels of doping in the example. Accordingly, for adiode 160 with awidth 330 of 100 nm and a depth (not shown) of 100 nm (i.e. adiode 160 of 100 nm×100 nm size/surface area) thecontact resistance 320 will be about 1Ω. For instance: -
R 320=1×10−10 Ω-cm2/(10−5 cm×10−5 cm)=1Ω, i. - where a 100 nm distance (here both
width 330 and depth, not shown) is 10−5 cm. - Similarly, the resistance of p-type (Ge)
layer 130 is: -
R 130=0.005 Ω-cm*20 nm/(10−5 cm×10−5 cm)=100 Ω, i. - where 20 nm is the
thickness 135 of the p-type layer and 0.005 Ω-cm is the resistivity of Ge. - The resistance of the n-type (Al:ZnO)
layer 140 is: -
R 140=0.0014 Ω-cm*20 nm/(10−5 cm×10−5 cm)=28Ω, i. - where 20 nm is the
thickness 145 of the n-type layer 140 and 0.005 Ω-cm is the resistivity of Al doped with ZnO at the given concentration. - Finally, the contact resistance at the
interface 340 between the n-type (Al:ZnO)layer 140 and the metal (Al)top electrode 150 can be as low as 1×10−8 Ω-cm2 with the levels of doping in the example, yielding a contact resistance at thisinterface 340 of -
R 340=1×10−8 Ω-cm2/(10−5 cm×10−5 cm)=100Ω, i. - for the 10−5 cm×10−5
cm size diode 160/360. - Therefore, the total series resistance RT of the
device 160 is: -
R T =R 320 +R 130 +R 140 +R 340,=approximately 200Ω, i. - where the major contributions to the total resistance is the resistance of the p-
type layer 130, R130, and the n-type layer 140, R140. - Accordingly, the doping levels/concentration of the p-
type layer 130 and the n-type layer 140 are made high to keep the resistance of both of the p-type 130 and n-type 140 layers low, but these doping concentrations are low enough to still maintain thep-n junction interface 160/360 as a diode. - These values are specific for p-Ge and Al:ZnO example junction. The
contact resistance 320 to the p-Ge layer 130 is very low but the contact resistance to the Al:ZnO 140 is higher. - In this example, a forward voltage of 1 volt (V) across a total resistance, RT, of approximately 200Ω, will result in a forward current through the
diode 160, I, equal to 1 V/200Ω=0.5 mA=5 MA/cm2. - Based on the measured I-V of this example Al:ZnO/
Ge diode 160 and a theoretical total forward resistance of 200Ω forward currents at different voltages are provided in the table below: -
Voltage 0.5 V 0.75 V 1 V 1.5 V 2 V 3 V Current 20 A/cm2 200 A/cm2 2 kA/cm2 10 kA/cm2 50 MA/ cm 2100 MA/cm2 - Where “MA” is 106 Amperes and “kA” is 103 Amperes.
- The current, I, was calculated as I=50 MA/cm2 at 2V. The current at other voltages are calculated from the diode I-V curve, assuming I=50 MA/cm2 at 2V.
- Analysis was performed to determine the “on/off ratio”. A comparison was made between the forward current, or “ON current”, at a forward bias voltage Von, to an “OFF Current” when reverse biasing the
diode 160 at a reverse bias voltage, Voff, is applied, where -
V off =V on/2. i. - As a non-limiting example, at a Von=2V the forward current through the diode 160 Ion=50 MA/cm2 while at Voff=1V, the leakage current, Ioff=2 k A/cm2.
- In this example, the On/Off current ratio is 2.5×104.
- One example design criterion for an N×N array of diodes is that:
-
I off <I on/(10×N) at V off =V on/2, or 1. -
I on /I off>(10×N), 2. - where N is the dimension of one side of a square array of diodes.
- Therefore,
diodes 160/360 having an On/Off current ratio, Ion/Ioff, of 2.5×104 or better can be used in diode arrays where N×N is up to 1000×1000 and still satisfy this design requirement. - To create larger N×N arrays that meet this design requirement, the p-
type layer 130 can be made from Si or SiGe which will reduce the On/Off current ratio when Voff=Von/2. -
FIG. 4 is an isometric view of anarray 400 of heterojunction thin film diodes (160, 360) used with an array of phase change memories (PCM), each PCM typically 425. - PCMs 425 are known circuit elements that manifest two or more states, e.g. resistance values, that can be set and reset and read to store/retrieve a memory state.
- The
array 400 is disposed on asubstrate 105. For arrays built in the BEOL, alternative embodiments of thesubstrate 105 can be made of a dielectric, rather than a semiconductor material, as described above. - In one form, the array is made of one or more array elements, typical 410. An array element can be a diode (160, 360) alone. In the
PCM array embodiment 400 shown, an array element is a diode (160, 360) in series with a PCM, 425 between a bottom array 420B and a top array 450 electrode. - One or more of the array elements 425 can be stack upon one 475 another 475. For example, in the
PCM array embodiment 400, there is a first array layer (475B, typically 475), each array layer 475 has one or more bottom array elements (410B, typically 410). The bottom array elements (410B, 410) have a first bottom array electrode (420B, typically 420), a bottom diode (160, 360, 460B, typically 460), a bottom PCM (425B, typically 425), and a first top array electrode (450). - In this embodiment, a second or top array layer (475T, 475) is stacked upon the first or bottom array layer (475B, 475). The second or top array layer 475T has one or more top array elements (410T, typically 410). Each of the top array elements 410T has a second bottom array electrode (420T, typically 420), a top diode (160, 360, 460T, typically 460), a top PCM (425T, typically 425), and a second top array electrode 450.
- Note that in this embodiment, the first top array electrode 450 and the second top array electrode 450 are the same element, namely a common top array electrode 450. In other words, one or more of the bottom array elements 410B and one or more of the top array elements 410T are connected in common by the top electrode 450. In a sense, in this
embodiment 400, the top array layer 475T is a “flipped” version of the bottom array layer 475B. - In addition, note that in this embodiment 400 (and that shown in
FIG. 5 ), the diodes (160, 360, 460) in one or more of the bottom 410B and top 410T array elements 410T have the same polarity or direction. In other words, each of the one or more bottom 410B and top 410T array elements 410T connected in common has a diode 460 with the same layer position for the p-type 130 (140) and n-type 140 (130) layers. - In alternative embodiments, one or more bottom 410B array elements has the bottom diode 460B with the p-type 140 (130) and n-type 130 (140) layers reverse from the top diode 460T in an associated or connected top 410T array element 410T. In these cases, the bottom 410B and top 410T array elements would be connected in series. In other words, in this alternative embodiment, top electrode 450 of the bottom array element 410B is connected to the second bottom electrode (120, 420T).
- Accordingly, the connections/configuration of the
array 400 can be adjusted by both how the array elements 410 are interconnected and/or how they are constructed. - In the embodiment shown 400, the first 120 and second 150 electrodes are shown elongated 310. The elongated 310 first 120 and second 150 electrode can become or be connected to the respective array electrodes (420, 450) that connect two or more array elements 410. Alternate embodiments are envisioned where one or more of the first array 420 and second array 450 electrodes connect to just one, two, or many array elements 410.
-
FIG. 5 is a circuit schematic 500 of a phase change memory structure using heterojunction thin film diodes (160, 360, in this schematic typically 560). - In this embodiment, the diodes (160, 360, 560) are made the same way, e.g. the diodes (160, 360, 560) and have the same polarity because the p-type layer 130 (140) and the n-type layer 140 (130) are layered in the same sequence for each of the diodes (160, 360, 560). The top diode (560T, typically 560) and bottom diode (560B, typically 560) are connected though a respective top PCM (525T, typically 525) and bottom PCM (525B, typically 525) so that the top electrodes (150, 550) of the diodes are connected in common 550 through their respective PCMs 525.
- When the common connection 550 is at a lower voltage, e.g. ground voltage, and a higher voltage is applied to the
bottom electrode 120 of top diode 560T (i.e. bottom electrode 520T, typically 520, or 120) and/or thebottom electrode 120 of bottom diode 560B (i.e. bottom electrode 520B, typically 520, or 120), a current flows through the respective diode 560 and its associated PCB 525. A top voltage 575T (typically 575) can be read across the top PCM 525T and/or a bottom voltage 575B (typically 575) can be read across the bottom PCM 525B. A lower voltage 575 reading indicates the respective PCM 525 is in a lower resistive or first memory state. A higher voltage 575 reading indicates the respective PCM 525 is in a higher resistive or second memory state. If the polarity of the applied voltage reverse biases either the top 525T and/or bottom 525B diode 525, no or very little current will flow through the “Off” diode 560 and its associated PCM 525 because the diodes (160, 360, 560) have such a low leakage current and such a high On/Off current ratio. In such “Off” condition no or little voltage 575 will be read. -
FIG. 6 is a flow chart of the method of making 600 a heterojunction thin film diode (160, 360). - The
method 600 begins withstep 610 which forms alayered structure 100, either on a semiconductor ordielectric substrate 105. Thelayered structure 100 formed on adielectric substrate 105 can be formed at the BEOL. The layered structure includes thesubstrate 105, the first/bottom electrode 120, the p-type layer 130 (140), the n-type layer 140 (130), and the second/top electrode 150. The p-type 140 (130) and n-type 130 (140) layers can be formed in reverse order. Optionally, anITL layer 250 is formed between the p-type layer 130 (140) and the n-type layer 140 (130). Further details including doping levels are included in the description ofFIGS. 1 and 2 . - In
step 620 of the process, an etching is formed to define one or more diode (160, 360)structures 300. The first/bottom 120 and/or second/top 150 electrodes can be formed under a single device (160, 360) and/or can be elongated 310 by known lithographic techniques to connect to two or more devices (160, 360),e.g. array elements 140. - In
step 630 array layers 475 can be stacked one upon the other 475 to form multiple different array configurations. PCMs 425 can be integrated into thearrays 400 to create memory structures, e.g. in the BEOL, either at one level 475 or at two or more multiple levels (475B, 475T, 475). - The descriptions of the various embodiments of the present invention have been presented for purposes of illustration but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. For example, the semiconductor devices, structures, and methods disclosed in accordance with embodiments of the present invention can be employed in applications, hardware, and/or electronic systems. Systems and hardware incorporating the semiconductor devices are contemplated embodiments of the invention.
- The terminology used herein was chosen to explain the principles of the embodiments and the practical application or technical improvement over technologies found in the marketplace or to otherwise enable others of ordinary skill in the art to understand the embodiments disclosed herein. Devices, components, elements, features, apparatus, systems, structures, techniques, and methods described with different terminology that perform substantially the same function, work in the substantial the same way, have substantially the same use, and/or perform the similar steps are contemplated as embodiments of this invention.
Claims (20)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/907,065 US20210399047A1 (en) | 2020-06-19 | 2020-06-19 | Heterojunction thin film diode |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US16/907,065 US20210399047A1 (en) | 2020-06-19 | 2020-06-19 | Heterojunction thin film diode |
Publications (1)
Publication Number | Publication Date |
---|---|
US20210399047A1 true US20210399047A1 (en) | 2021-12-23 |
Family
ID=79022031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US16/907,065 Pending US20210399047A1 (en) | 2020-06-19 | 2020-06-19 | Heterojunction thin film diode |
Country Status (1)
Country | Link |
---|---|
US (1) | US20210399047A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025220A (en) * | 1996-06-18 | 2000-02-15 | Micron Technology, Inc. | Method of forming a polysilicon diode and devices incorporating such diode |
US20070015328A1 (en) * | 2005-07-18 | 2007-01-18 | Sharp Laboratories Of America, Inc. | MSM binary switch memory device |
US20080232160A1 (en) * | 2007-02-27 | 2008-09-25 | International Business Machines Corporation | Rectifying element for a crosspoint based memory array architecture |
US20100315857A1 (en) * | 2009-06-12 | 2010-12-16 | Sonehara Takeshi | Resistance change memory |
US20140241050A1 (en) * | 2013-02-27 | 2014-08-28 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
-
2020
- 2020-06-19 US US16/907,065 patent/US20210399047A1/en active Pending
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025220A (en) * | 1996-06-18 | 2000-02-15 | Micron Technology, Inc. | Method of forming a polysilicon diode and devices incorporating such diode |
US20070015328A1 (en) * | 2005-07-18 | 2007-01-18 | Sharp Laboratories Of America, Inc. | MSM binary switch memory device |
US20080232160A1 (en) * | 2007-02-27 | 2008-09-25 | International Business Machines Corporation | Rectifying element for a crosspoint based memory array architecture |
US20100315857A1 (en) * | 2009-06-12 | 2010-12-16 | Sonehara Takeshi | Resistance change memory |
US20140241050A1 (en) * | 2013-02-27 | 2014-08-28 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10177076B2 (en) | Air gap and air spacer pinch off | |
US8513636B2 (en) | Vertical diodes for non-volatile memory device | |
US20030164492A1 (en) | Diverse band gap energy level semiconductor device | |
US11557663B2 (en) | Twin gate tunnel field-effect transistor (FET) | |
US11901356B2 (en) | Three-dimensional semiconductor devices | |
US11004750B2 (en) | Middle of the line contact formation | |
TWI784950B (en) | Broken bandgap contact | |
CN103403867B (en) | Nonvolatile resistance change element | |
US10832964B1 (en) | Replacement contact formation for gate contact over active region with selective metal growth | |
US11626287B2 (en) | Semiconductor device with improved contact resistance and via connectivity | |
US20190319021A1 (en) | Perpendicular stacked field-effect transistor device | |
US20070102724A1 (en) | Vertical diode doped with antimony to avoid or limit dopant diffusion | |
US20210399047A1 (en) | Heterojunction thin film diode | |
WO2023099293A1 (en) | Staggered stacked semiconductor devices | |
US20230099767A1 (en) | Vertical field-effect transistor with wrap-around contact structure | |
KR20190139410A (en) | Semiconductor device, and method for manufacturing the same | |
US11476163B2 (en) | Confined gate recessing for vertical transport field effect transistors | |
US11189701B1 (en) | Bipolar junction transistor with vertically integrated resistor | |
US20230178597A1 (en) | Semiconductor structures with low top contact resistance | |
US9087576B1 (en) | Low temperature fabrication method for a three-dimensional memory device and structure | |
US20230135219A1 (en) | Resistor structures of integrated circuit devices including stacked transistors and methods of forming the same | |
US20240154009A1 (en) | Semiconductor structure having a backside contact with backside sidewall spacers | |
US20240128318A1 (en) | Semiconductor structure with fully wrapped-around backside contact | |
US20240136253A1 (en) | Isolation rail between backside power rails | |
KR102674860B1 (en) | Source contact structure and manufacturing method of 3D memory device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW YORK Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LI, NING;SADANA, DEVENDRA K.;KIM, WANKI;SIGNING DATES FROM 20200618 TO 20200619;REEL/FRAME:052994/0379 |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: NON FINAL ACTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: RESPONSE TO NON-FINAL OFFICE ACTION ENTERED AND FORWARDED TO EXAMINER |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: FINAL REJECTION MAILED |
|
STPP | Information on status: patent application and granting procedure in general |
Free format text: DOCKETED NEW CASE - READY FOR EXAMINATION |